amiro-lld / include / alld_dw1000_regs.h @ 188ba2a7
History | View | Annotate | Download (80.022 KB)
| 1 | fce9feec | Robin Ewers | /*! ------------------------------------------------------------------------------------------------------------------
|
|---|---|---|---|
| 2 | * @file deca_regs.h
|
||
| 3 | * @brief DW1000 Register Definitions
|
||
| 4 | * This file supports assembler and C development for DW1000 enabled devices
|
||
| 5 | *
|
||
| 6 | * @attention
|
||
| 7 | *
|
||
| 8 | * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
|
||
| 9 | *
|
||
| 10 | * All rights reserved.
|
||
| 11 | *
|
||
| 12 | */
|
||
| 13 | |||
| 14 | #ifndef _DECA_REGS_H_
|
||
| 15 | #define _DECA_REGS_H_
|
||
| 16 | |||
| 17 | #ifdef __cplusplus
|
||
| 18 | extern "C" { |
||
| 19 | #endif
|
||
| 20 | |||
| 21 | #include <amiro-lld.h> |
||
| 22 | #if defined(AMIROLLD_CFG_USE_DW1000) || defined(__DOXYGEN__)
|
||
| 23 | |||
| 24 | /****************************************************************************//** |
||
| 25 | * @brief Bit definitions for register DEV_ID
|
||
| 26 | **/
|
||
| 27 | #define DEV_ID_ID 0x00 /* Device ID register, includes revision info (0xDECA0130) */ |
||
| 28 | #define DEV_ID_LEN (4) |
||
| 29 | /* mask and shift */
|
||
| 30 | #define DEV_ID_REV_MASK 0x0000000FUL /* Revision */ |
||
| 31 | #define DEV_ID_VER_MASK 0x000000F0UL /* Version */ |
||
| 32 | #define DEV_ID_MODEL_MASK 0x0000FF00UL /* The MODEL identifies the device. The DW1000 is device type 0x01 */ |
||
| 33 | #define DEV_ID_RIDTAG_MASK 0xFFFF0000UL /* Register Identification Tag 0XDECA */ |
||
| 34 | |||
| 35 | /****************************************************************************//** |
||
| 36 | * @brief Bit definitions for register EUI_64
|
||
| 37 | **/
|
||
| 38 | #define EUI_64_ID 0x01 /* IEEE Extended Unique Identifier (63:0) */ |
||
| 39 | #define EUI_64_OFFSET 0x00 |
||
| 40 | #define EUI_64_LEN (8) |
||
| 41 | |||
| 42 | /****************************************************************************//** |
||
| 43 | * @brief Bit definitions for register PANADR
|
||
| 44 | **/
|
||
| 45 | #define PANADR_ID 0x03 /* PAN ID (31:16) and Short Address (15:0) */ |
||
| 46 | #define PANADR_LEN (4) |
||
| 47 | /*mask and shift */
|
||
| 48 | #define PANADR_SHORT_ADDR_OFFSET 0 /* In bytes */ |
||
| 49 | #define PANADR_SHORT_ADDR_MASK 0x0000FFFFUL /* Short Address */ |
||
| 50 | #define PANADR_PAN_ID_OFFSET 2 /* In bytes */ |
||
| 51 | #define PANADR_PAN_ID_MASK 0xFFFF00F0UL /* PAN Identifier */ |
||
| 52 | |||
| 53 | /****************************************************************************//** |
||
| 54 | * @brief Bit definitions for register 0x05
|
||
| 55 | **/
|
||
| 56 | #define REG_05_ID_RESERVED 0x05 |
||
| 57 | |||
| 58 | /****************************************************************************//** |
||
| 59 | * @brief Bit definitions for register SYS_CFG
|
||
| 60 | **/
|
||
| 61 | #define SYS_CFG_ID 0x04 /* System Configuration (31:0) */ |
||
| 62 | #define SYS_CFG_LEN (4) |
||
| 63 | /*mask and shift */
|
||
| 64 | #define SYS_CFG_MASK 0xF047FFFFUL /* access mask to SYS_CFG_ID */ |
||
| 65 | #define SYS_CFG_FF_ALL_EN 0x000001FEUL /* Frame filtering options all frames allowed */ |
||
| 66 | /*offset 0 */
|
||
| 67 | #define SYS_CFG_FFE 0x00000001UL /* Frame Filtering Enable. This bit enables the frame filtering functionality */ |
||
| 68 | #define SYS_CFG_FFBC 0x00000002UL /* Frame Filtering Behave as a Co-ordinator */ |
||
| 69 | #define SYS_CFG_FFAB 0x00000004UL /* Frame Filtering Allow Beacon frame reception */ |
||
| 70 | #define SYS_CFG_FFAD 0x00000008UL /* Frame Filtering Allow Data frame reception */ |
||
| 71 | #define SYS_CFG_FFAA 0x00000010UL /* Frame Filtering Allow Acknowledgment frame reception */ |
||
| 72 | #define SYS_CFG_FFAM 0x00000020UL /* Frame Filtering Allow MAC command frame reception */ |
||
| 73 | #define SYS_CFG_FFAR 0x00000040UL /* Frame Filtering Allow Reserved frame types */ |
||
| 74 | #define SYS_CFG_FFA4 0x00000080UL /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */ |
||
| 75 | /*offset 8 */
|
||
| 76 | #define SYS_CFG_FFA5 0x00000100UL /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */ |
||
| 77 | #define SYS_CFG_HIRQ_POL 0x00000200UL /* Host interrupt polarity */ |
||
| 78 | #define SYS_CFG_SPI_EDGE 0x00000400UL /* SPI data launch edge */ |
||
| 79 | #define SYS_CFG_DIS_FCE 0x00000800UL /* Disable frame check error handling */ |
||
| 80 | #define SYS_CFG_DIS_DRXB 0x00001000UL /* Disable Double RX Buffer */ |
||
| 81 | #define SYS_CFG_DIS_PHE 0x00002000UL /* Disable receiver abort on PHR error */ |
||
| 82 | #define SYS_CFG_DIS_RSDE 0x00004000UL /* Disable Receiver Abort on RSD error */ |
||
| 83 | #define SYS_CFG_FCS_INIT2F 0x00008000UL /* initial seed value for the FCS generation and checking function */ |
||
| 84 | /*offset 16 */
|
||
| 85 | #define SYS_CFG_PHR_MODE_SHFT 16 |
||
| 86 | #define SYS_CFG_PHR_MODE_00 0x00000000UL /* Standard Frame mode */ |
||
| 87 | #define SYS_CFG_PHR_MODE_11 0x00030000UL /* Long Frames mode */ |
||
| 88 | #define SYS_CFG_DIS_STXP 0x00040000UL /* Disable Smart TX Power control */ |
||
| 89 | #define SYS_CFG_RXM110K 0x00400000UL /* Receiver Mode 110 kbps data rate */ |
||
| 90 | /*offset 24 */
|
||
| 91 | #define SYS_CFG_RXWTOE 0x10000000UL /* Receive Wait Timeout Enable. */ |
||
| 92 | #define SYS_CFG_RXAUTR 0x20000000UL /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */ |
||
| 93 | #define SYS_CFG_AUTOACK 0x40000000UL /* Automatic Acknowledgement Enable */ |
||
| 94 | #define SYS_CFG_AACKPEND 0x80000000UL /* Automatic Acknowledgement Pending bit control */ |
||
| 95 | |||
| 96 | |||
| 97 | /****************************************************************************//** |
||
| 98 | * @brief Bit definitions for register SYS_TIME
|
||
| 99 | **/
|
||
| 100 | #define SYS_TIME_ID 0x06 /* System Time Counter (40-bit) */ |
||
| 101 | #define SYS_TIME_OFFSET 0x00 |
||
| 102 | #define SYS_TIME_LEN (5) /* Note 40 bit register */ |
||
| 103 | |||
| 104 | |||
| 105 | /****************************************************************************//** |
||
| 106 | * @brief Bit definitions for register 0x07
|
||
| 107 | **/
|
||
| 108 | #define REG_07_ID_RESERVED 0x07 |
||
| 109 | |||
| 110 | /****************************************************************************//** |
||
| 111 | * @brief Bit definitions for register TX_FCTRL
|
||
| 112 | **/
|
||
| 113 | #define TX_FCTRL_ID 0x08 /* Transmit Frame Control */ |
||
| 114 | #define TX_FCTRL_LEN (5) /* Note 40 bit register */ |
||
| 115 | /*masks (low 32 bit) */
|
||
| 116 | #define TX_FCTRL_TFLEN_MASK 0x0000007FUL /* bit mask to access Transmit Frame Length */ |
||
| 117 | #define TX_FCTRL_TFLE_MASK 0x00000380UL /* bit mask to access Transmit Frame Length Extension */ |
||
| 118 | #define TX_FCTRL_FLE_MASK 0x000003FFUL /* bit mask to access Frame Length field */ |
||
| 119 | #define TX_FCTRL_TXBR_MASK 0x00006000UL /* bit mask to access Transmit Bit Rate */ |
||
| 120 | #define TX_FCTRL_TXPRF_MASK 0x00030000UL /* bit mask to access Transmit Pulse Repetition Frequency */ |
||
| 121 | #define TX_FCTRL_TXPSR_MASK 0x000C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ |
||
| 122 | #define TX_FCTRL_PE_MASK 0x00300000UL /* bit mask to access Preamble Extension */ |
||
| 123 | #define TX_FCTRL_TXPSR_PE_MASK 0x003C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ |
||
| 124 | #define TX_FCTRL_SAFE_MASK_32 0xFFFFE3FFUL /* FSCTRL has fields which should always be writen zero */ |
||
| 125 | /*offset 0 */
|
||
| 126 | /*offset 8 */
|
||
| 127 | #define TX_FCTRL_TXBR_110k 0x00000000UL /* Transmit Bit Rate = 110k */ |
||
| 128 | #define TX_FCTRL_TXBR_850k 0x00002000UL /* Transmit Bit Rate = 850k */ |
||
| 129 | #define TX_FCTRL_TXBR_6M 0x00004000UL /* Transmit Bit Rate = 6.8M */ |
||
| 130 | #define TX_FCTRL_TXBR_SHFT (13) /* shift to access Data Rate field */ |
||
| 131 | #define TX_FCTRL_TR 0x00008000UL /* Transmit Ranging enable */ |
||
| 132 | #define TX_FCTRL_TR_SHFT (15) /* shift to access Ranging bit */ |
||
| 133 | /*offset 16 */
|
||
| 134 | #define TX_FCTRL_TXPRF_SHFT (16) /* shift to access Pulse Repetition Frequency field */ |
||
| 135 | #define TX_FCTRL_TXPRF_4M 0x00000000UL /* Transmit Pulse Repetition Frequency = 4 Mhz */ |
||
| 136 | #define TX_FCTRL_TXPRF_16M 0x00010000UL /* Transmit Pulse Repetition Frequency = 16 Mhz */ |
||
| 137 | #define TX_FCTRL_TXPRF_64M 0x00020000UL /* Transmit Pulse Repetition Frequency = 64 Mhz */ |
||
| 138 | #define TX_FCTRL_TXPSR_SHFT (18) /* shift to access Preamble Symbol Repetitions field */ |
||
| 139 | #define TX_FCTRL_PE_SHFT (20) /* shift to access Preamble length Extension to allow specification of non-standard values */ |
||
| 140 | #define TX_FCTRL_TXPSR_PE_16 0x00000000UL /* bit mask to access Preamble Extension = 16 */ |
||
| 141 | #define TX_FCTRL_TXPSR_PE_64 0x00040000UL /* bit mask to access Preamble Extension = 64 */ |
||
| 142 | #define TX_FCTRL_TXPSR_PE_128 0x00140000UL /* bit mask to access Preamble Extension = 128 */ |
||
| 143 | #define TX_FCTRL_TXPSR_PE_256 0x00240000UL /* bit mask to access Preamble Extension = 256 */ |
||
| 144 | #define TX_FCTRL_TXPSR_PE_512 0x00340000UL /* bit mask to access Preamble Extension = 512 */ |
||
| 145 | #define TX_FCTRL_TXPSR_PE_1024 0x00080000UL /* bit mask to access Preamble Extension = 1024 */ |
||
| 146 | #define TX_FCTRL_TXPSR_PE_1536 0x00180000UL /* bit mask to access Preamble Extension = 1536 */ |
||
| 147 | #define TX_FCTRL_TXPSR_PE_2048 0x00280000UL /* bit mask to access Preamble Extension = 2048 */ |
||
| 148 | #define TX_FCTRL_TXPSR_PE_4096 0x000C0000UL /* bit mask to access Preamble Extension = 4096 */ |
||
| 149 | /*offset 22 */
|
||
| 150 | #define TX_FCTRL_TXBOFFS_SHFT (22) /* Shift to access transmit buffer index offset */ |
||
| 151 | #define TX_FCTRL_TXBOFFS_MASK 0xFFC00000UL /* bit mask to access Transmit buffer index offset 10-bit field */ |
||
| 152 | /*offset 32 */
|
||
| 153 | #define TX_FCTRL_IFSDELAY_MASK 0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */ |
||
| 154 | |||
| 155 | /****************************************************************************//** |
||
| 156 | * @brief Bit definitions for register TX_BUFFER
|
||
| 157 | **/
|
||
| 158 | #define TX_BUFFER_ID 0x09 /* Transmit Data Buffer */ |
||
| 159 | #define TX_BUFFER_LEN (1024) |
||
| 160 | |||
| 161 | /****************************************************************************//** |
||
| 162 | * @brief Bit definitions for register DX_TIME
|
||
| 163 | **/
|
||
| 164 | #define DX_TIME_ID 0x0A /* Delayed Send or Receive Time (40-bit) */ |
||
| 165 | #define DX_TIME_LEN (5) |
||
| 166 | |||
| 167 | /****************************************************************************//** |
||
| 168 | * @brief Bit definitions for register 0x08
|
||
| 169 | **/
|
||
| 170 | #define REG_0B_ID_RESERVED 0x0B |
||
| 171 | |||
| 172 | /****************************************************************************//** |
||
| 173 | * @brief Bit definitions for register RX_FWTO
|
||
| 174 | **/
|
||
| 175 | #define RX_FWTO_ID 0x0C /* Receive Frame Wait Timeout Period */ |
||
| 176 | #define RX_FWTO_OFFSET 0x00 |
||
| 177 | #define RX_FWTO_LEN (2) /* doc bug*/ |
||
| 178 | /*mask and shift */
|
||
| 179 | #define RX_FWTO_MASK 0xFFFF |
||
| 180 | |||
| 181 | /****************************************************************************//** |
||
| 182 | * @brief Bit definitions for register SYS_CTRL
|
||
| 183 | **/
|
||
| 184 | #define SYS_CTRL_ID 0x0D /* System Control Register */ |
||
| 185 | #define SYS_CTRL_OFFSET 0x00 |
||
| 186 | #define SYS_CTRL_LEN (4) |
||
| 187 | /*masks */
|
||
| 188 | #define SYS_CTRL_MASK_32 0x010003CFUL /* System Control Register access mask (all unused fields should always be writen as zero) */ |
||
| 189 | /*offset 0 */
|
||
| 190 | #define SYS_CTRL_SFCST 0x00000001UL /* Suppress Auto-FCS Transmission (on this frame) */ |
||
| 191 | #define SYS_CTRL_TXSTRT 0x00000002UL /* Start Transmitting Now */ |
||
| 192 | #define SYS_CTRL_TXDLYS 0x00000004UL /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */ |
||
| 193 | #define SYS_CTRL_CANSFCS 0x00000008UL /* Cancel Suppression of auto-FCS transmission (on the current frame) */ |
||
| 194 | #define SYS_CTRL_TRXOFF 0x00000040UL /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */ |
||
| 195 | #define SYS_CTRL_WAIT4RESP 0x00000080UL /* Wait for Response */ |
||
| 196 | /*offset 8 */
|
||
| 197 | #define SYS_CTRL_RXENAB 0x00000100UL /* Enable Receiver Now */ |
||
| 198 | #define SYS_CTRL_RXDLYE 0x00000200UL /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/ |
||
| 199 | /*offset 16 */
|
||
| 200 | /*offset 24 */
|
||
| 201 | #define SYS_CTRL_HSRBTOGGLE 0x01000000UL /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */ |
||
| 202 | #define SYS_CTRL_HRBT (SYS_CTRL_HSRBTOGGLE)
|
||
| 203 | #define SYS_CTRL_HRBT_OFFSET (3) |
||
| 204 | |||
| 205 | /****************************************************************************//** |
||
| 206 | * @brief Bit definitions for register SYS_MASK
|
||
| 207 | **/
|
||
| 208 | #define SYS_MASK_ID 0x0E /* System Event Mask Register */ |
||
| 209 | #define SYS_MASK_LEN (4) |
||
| 210 | /*masks */
|
||
| 211 | #define SYS_MASK_MASK_32 0x3FF7FFFEUL /* System Event Mask Register access mask (all unused fields should always be writen as zero) */ |
||
| 212 | /*offset 0 */
|
||
| 213 | #define SYS_MASK_MCPLOCK 0x00000002UL /* Mask clock PLL lock event */ |
||
| 214 | #define SYS_MASK_MESYNCR 0x00000004UL /* Mask clock PLL lock event */ |
||
| 215 | #define SYS_MASK_MAAT 0x00000008UL /* Mask automatic acknowledge trigger event */ |
||
| 216 | #define SYS_MASK_MTXFRB 0x00000010UL /* Mask transmit frame begins event */ |
||
| 217 | #define SYS_MASK_MTXPRS 0x00000020UL /* Mask transmit preamble sent event */ |
||
| 218 | #define SYS_MASK_MTXPHS 0x00000040UL /* Mask transmit PHY Header Sent event */ |
||
| 219 | #define SYS_MASK_MTXFRS 0x00000080UL /* Mask transmit frame sent event */ |
||
| 220 | /*offset 8 */
|
||
| 221 | #define SYS_MASK_MRXPRD 0x00000100UL /* Mask receiver preamble detected event */ |
||
| 222 | #define SYS_MASK_MRXSFDD 0x00000200UL /* Mask receiver SFD detected event */ |
||
| 223 | #define SYS_MASK_MLDEDONE 0x00000400UL /* Mask LDE processing done event */ |
||
| 224 | #define SYS_MASK_MRXPHD 0x00000800UL /* Mask receiver PHY header detect event */ |
||
| 225 | #define SYS_MASK_MRXPHE 0x00001000UL /* Mask receiver PHY header error event */ |
||
| 226 | #define SYS_MASK_MRXDFR 0x00002000UL /* Mask receiver data frame ready event */ |
||
| 227 | #define SYS_MASK_MRXFCG 0x00004000UL /* Mask receiver FCS good event */ |
||
| 228 | #define SYS_MASK_MRXFCE 0x00008000UL /* Mask receiver FCS error event */ |
||
| 229 | /*offset 16 */
|
||
| 230 | #define SYS_MASK_MRXRFSL 0x00010000UL /* Mask receiver Reed Solomon Frame Sync Loss event */ |
||
| 231 | #define SYS_MASK_MRXRFTO 0x00020000UL /* Mask Receive Frame Wait Timeout event */ |
||
| 232 | #define SYS_MASK_MLDEERR 0x00040000UL /* Mask leading edge detection processing error event */ |
||
| 233 | #define SYS_MASK_MRXOVRR 0x00100000UL /* Mask Receiver Overrun event */ |
||
| 234 | #define SYS_MASK_MRXPTO 0x00200000UL /* Mask Preamble detection timeout event */ |
||
| 235 | #define SYS_MASK_MGPIOIRQ 0x00400000UL /* Mask GPIO interrupt event */ |
||
| 236 | #define SYS_MASK_MSLP2INIT 0x00800000UL /* Mask SLEEP to INIT event */ |
||
| 237 | /*offset 24*/
|
||
| 238 | #define SYS_MASK_MRFPLLLL 0x01000000UL /* Mask RF PLL Loosing Lock warning event */ |
||
| 239 | #define SYS_MASK_MCPLLLL 0x02000000UL /* Mask Clock PLL Loosing Lock warning event */ |
||
| 240 | #define SYS_MASK_MRXSFDTO 0x04000000UL /* Mask Receive SFD timeout event */ |
||
| 241 | #define SYS_MASK_MHPDWARN 0x08000000UL /* Mask Half Period Delay Warning event */ |
||
| 242 | #define SYS_MASK_MTXBERR 0x10000000UL /* Mask Transmit Buffer Error event */ |
||
| 243 | #define SYS_MASK_MAFFREJ 0x20000000UL /* Mask Automatic Frame Filtering rejection event */ |
||
| 244 | |||
| 245 | /****************************************************************************//** |
||
| 246 | * @brief Bit definitions for register SYS_STATUS
|
||
| 247 | **/
|
||
| 248 | #define SYS_STATUS_ID 0x0F /* System event Status Register */ |
||
| 249 | #define SYS_STATUS_OFFSET 0x00 |
||
| 250 | #define SYS_STATUS_LEN (5) /* Note 40 bit register */ |
||
| 251 | /*masks */
|
||
| 252 | #define SYS_STATUS_MASK_32 0xFFF7FFFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */ |
||
| 253 | /*offset 0 */
|
||
| 254 | #define SYS_STATUS_IRQS 0x00000001UL /* Interrupt Request Status READ ONLY */ |
||
| 255 | #define SYS_STATUS_CPLOCK 0x00000002UL /* Clock PLL Lock */ |
||
| 256 | #define SYS_STATUS_ESYNCR 0x00000004UL /* External Sync Clock Reset */ |
||
| 257 | #define SYS_STATUS_AAT 0x00000008UL /* Automatic Acknowledge Trigger */ |
||
| 258 | #define SYS_STATUS_TXFRB 0x00000010UL /* Transmit Frame Begins */ |
||
| 259 | #define SYS_STATUS_TXPRS 0x00000020UL /* Transmit Preamble Sent */ |
||
| 260 | #define SYS_STATUS_TXPHS 0x00000040UL /* Transmit PHY Header Sent */ |
||
| 261 | #define SYS_STATUS_TXFRS 0x00000080UL /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */ |
||
| 262 | /*offset 8 */
|
||
| 263 | #define SYS_STATUS_RXPRD 0x00000100UL /* Receiver Preamble Detected status */ |
||
| 264 | #define SYS_STATUS_RXSFDD 0x00000200UL /* Receiver Start Frame Delimiter Detected. */ |
||
| 265 | #define SYS_STATUS_LDEDONE 0x00000400UL /* LDE processing done */ |
||
| 266 | #define SYS_STATUS_RXPHD 0x00000800UL /* Receiver PHY Header Detect */ |
||
| 267 | #define SYS_STATUS_RXPHE 0x00001000UL /* Receiver PHY Header Error */ |
||
| 268 | #define SYS_STATUS_RXDFR 0x00002000UL /* Receiver Data Frame Ready */ |
||
| 269 | #define SYS_STATUS_RXFCG 0x00004000UL /* Receiver FCS Good */ |
||
| 270 | #define SYS_STATUS_RXFCE 0x00008000UL /* Receiver FCS Error */ |
||
| 271 | /*offset 16 */
|
||
| 272 | #define SYS_STATUS_RXRFSL 0x00010000UL /* Receiver Reed Solomon Frame Sync Loss */ |
||
| 273 | #define SYS_STATUS_RXRFTO 0x00020000UL /* Receive Frame Wait Timeout */ |
||
| 274 | #define SYS_STATUS_LDEERR 0x00040000UL /* Leading edge detection processing error */ |
||
| 275 | #define SYS_STATUS_reserved 0x00080000UL /* bit19 reserved */ |
||
| 276 | #define SYS_STATUS_RXOVRR 0x00100000UL /* Receiver Overrun */ |
||
| 277 | #define SYS_STATUS_RXPTO 0x00200000UL /* Preamble detection timeout */ |
||
| 278 | #define SYS_STATUS_GPIOIRQ 0x00400000UL /* GPIO interrupt */ |
||
| 279 | #define SYS_STATUS_SLP2INIT 0x00800000UL /* SLEEP to INIT */ |
||
| 280 | /*offset 24 */
|
||
| 281 | #define SYS_STATUS_RFPLL_LL 0x01000000UL /* RF PLL Losing Lock */ |
||
| 282 | #define SYS_STATUS_CLKPLL_LL 0x02000000UL /* Clock PLL Losing Lock */ |
||
| 283 | #define SYS_STATUS_RXSFDTO 0x04000000UL /* Receive SFD timeout */ |
||
| 284 | #define SYS_STATUS_HPDWARN 0x08000000UL /* Half Period Delay Warning */ |
||
| 285 | #define SYS_STATUS_TXBERR 0x10000000UL /* Transmit Buffer Error */ |
||
| 286 | #define SYS_STATUS_AFFREJ 0x20000000UL /* Automatic Frame Filtering rejection */ |
||
| 287 | #define SYS_STATUS_HSRBP 0x40000000UL /* Host Side Receive Buffer Pointer */ |
||
| 288 | #define SYS_STATUS_ICRBP 0x80000000UL /* IC side Receive Buffer Pointer READ ONLY */ |
||
| 289 | /*offset 32 */
|
||
| 290 | #define SYS_STATUS_RXRSCS 0x0100000000ULL /* Receiver Reed-Solomon Correction Status */ |
||
| 291 | #define SYS_STATUS_RXPREJ 0x0200000000ULL /* Receiver Preamble Rejection */ |
||
| 292 | #define SYS_STATUS_TXPUTE 0x0400000000ULL /* Transmit power up time error */ |
||
| 293 | |||
| 294 | #define SYS_STATUS_TXERR (0x0408) /* These bits are the 16 high bits of status register TXPUTE and HPDWARN flags */ |
||
| 295 | |||
| 296 | /* All RX events after a correct packet reception mask. */
|
||
| 297 | #define SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG | SYS_STATUS_RXPRD | \
|
||
| 298 | SYS_STATUS_RXSFDD | SYS_STATUS_RXPHD | SYS_STATUS_LDEDONE) |
||
| 299 | |||
| 300 | /* All double buffer events mask. */
|
||
| 301 | #define SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG)
|
||
| 302 | |||
| 303 | /* All RX errors mask. */
|
||
| 304 | #define SYS_STATUS_ALL_RX_ERR (SYS_STATUS_RXPHE | SYS_STATUS_RXFCE | SYS_STATUS_RXRFSL | SYS_STATUS_RXSFDTO \
|
||
| 305 | | SYS_STATUS_AFFREJ | SYS_STATUS_LDEERR) |
||
| 306 | |||
| 307 | /* User defined RX timeouts (frame wait timeout and preamble detect timeout) mask. */
|
||
| 308 | #define SYS_STATUS_ALL_RX_TO (SYS_STATUS_RXRFTO | SYS_STATUS_RXPTO)
|
||
| 309 | |||
| 310 | /* All TX events mask. */
|
||
| 311 | #define SYS_STATUS_ALL_TX (SYS_STATUS_AAT | SYS_STATUS_TXFRB | SYS_STATUS_TXPRS | \
|
||
| 312 | SYS_STATUS_TXPHS | SYS_STATUS_TXFRS ) |
||
| 313 | |||
| 314 | |||
| 315 | /****************************************************************************//** |
||
| 316 | * @brief Bit definitions for register RX_FINFO
|
||
| 317 | **/
|
||
| 318 | #define RX_FINFO_ID 0x10 /* RX Frame Information (in double buffer set) */ |
||
| 319 | #define RX_FINFO_OFFSET 0x00 |
||
| 320 | #define RX_FINFO_LEN (4) |
||
| 321 | /*mask and shift */
|
||
| 322 | #define RX_FINFO_MASK_32 0xFFFFFBFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */ |
||
| 323 | #define RX_FINFO_RXFLEN_MASK 0x0000007FUL /* Receive Frame Length (0 to 127) */ |
||
| 324 | #define RX_FINFO_RXFLE_MASK 0x00000380UL /* Receive Frame Length Extension (0 to 7)<<7 */ |
||
| 325 | #define RX_FINFO_RXFL_MASK_1023 0x000003FFUL /* Receive Frame Length Extension (0 to 1023) */ |
||
| 326 | |||
| 327 | #define RX_FINFO_RXNSPL_MASK 0x00001800UL /* Receive Non-Standard Preamble Length */ |
||
| 328 | #define RX_FINFO_RXPSR_MASK 0x000C0000UL /* RX Preamble Repetition. 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols */ |
||
| 329 | |||
| 330 | #define RX_FINFO_RXPEL_MASK 0x000C1800UL /* Receive Preamble Length = RXPSR+RXNSPL */ |
||
| 331 | #define RX_FINFO_RXPEL_64 0x00040000UL /* Receive Preamble length = 64 */ |
||
| 332 | #define RX_FINFO_RXPEL_128 0x00040800UL /* Receive Preamble length = 128 */ |
||
| 333 | #define RX_FINFO_RXPEL_256 0x00041000UL /* Receive Preamble length = 256 */ |
||
| 334 | #define RX_FINFO_RXPEL_512 0x00041800UL /* Receive Preamble length = 512 */ |
||
| 335 | #define RX_FINFO_RXPEL_1024 0x00080000UL /* Receive Preamble length = 1024 */ |
||
| 336 | #define RX_FINFO_RXPEL_1536 0x00080800UL /* Receive Preamble length = 1536 */ |
||
| 337 | #define RX_FINFO_RXPEL_2048 0x00081000UL /* Receive Preamble length = 2048 */ |
||
| 338 | #define RX_FINFO_RXPEL_4096 0x000C0000UL /* Receive Preamble length = 4096 */ |
||
| 339 | |||
| 340 | #define RX_FINFO_RXBR_MASK 0x00006000UL /* Receive Bit Rate report. This field reports the received bit rate */ |
||
| 341 | #define RX_FINFO_RXBR_110k 0x00000000UL /* Received bit rate = 110 kbps */ |
||
| 342 | #define RX_FINFO_RXBR_850k 0x00002000UL /* Received bit rate = 850 kbps */ |
||
| 343 | #define RX_FINFO_RXBR_6M 0x00004000UL /* Received bit rate = 6.8 Mbps */ |
||
| 344 | #define RX_FINFO_RXBR_SHIFT (13) |
||
| 345 | |||
| 346 | #define RX_FINFO_RNG 0x00008000UL /* Receiver Ranging. Ranging bit in the received PHY header identifying the frame as a ranging packet. */ |
||
| 347 | #define RX_FINFO_RNG_SHIFT (15) |
||
| 348 | |||
| 349 | #define RX_FINFO_RXPRF_MASK 0x00030000UL /* RX Pulse Repetition Rate report */ |
||
| 350 | #define RX_FINFO_RXPRF_16M 0x00010000UL /* PRF being employed in the receiver = 16M */ |
||
| 351 | #define RX_FINFO_RXPRF_64M 0x00020000UL /* PRF being employed in the receiver = 64M */ |
||
| 352 | #define RX_FINFO_RXPRF_SHIFT (16) |
||
| 353 | |||
| 354 | #define RX_FINFO_RXPACC_MASK 0xFFF00000UL /* Preamble Accumulation Count */ |
||
| 355 | #define RX_FINFO_RXPACC_SHIFT (20) |
||
| 356 | |||
| 357 | |||
| 358 | /****************************************************************************//** |
||
| 359 | * @brief Bit definitions for register RX_BUFFER
|
||
| 360 | **/
|
||
| 361 | #define RX_BUFFER_ID 0x11 /* Receive Data Buffer (in double buffer set) */ |
||
| 362 | #define RX_BUFFER_LEN (1024) |
||
| 363 | |||
| 364 | |||
| 365 | /****************************************************************************//** |
||
| 366 | * @brief Bit definitions for register RX_FQUAL
|
||
| 367 | **/
|
||
| 368 | #define RX_FQUAL_ID 0x12 /* Rx Frame Quality information (in double buffer set) */ |
||
| 369 | #define RX_FQUAL_LEN (8) /* note 64 bit register*/ |
||
| 370 | /*mask and shift */
|
||
| 371 | /*offset 0 */
|
||
| 372 | #define RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL /* Standard Deviation of Noise */ |
||
| 373 | #define RX_EQUAL_STD_NOISE_SHIFT (0) |
||
| 374 | #define STD_NOISE_MASK RX_EQUAL_STD_NOISE_MASK
|
||
| 375 | #define STD_NOISE_SHIFT RX_EQUAL_STD_NOISE_SHIFT
|
||
| 376 | /*offset 16 */
|
||
| 377 | #define RX_EQUAL_FP_AMPL2_MASK 0xFFFF0000ULL /* First Path Amplitude point 2 */ |
||
| 378 | #define RX_EQUAL_FP_AMPL2_SHIFT (16) |
||
| 379 | #define FP_AMPL2_MASK RX_EQUAL_FP_AMPL2_MASK
|
||
| 380 | #define FP_AMPL2_SHIFT RX_EQUAL_FP_AMPL2_SHIFT
|
||
| 381 | /*offset 32*/
|
||
| 382 | #define RX_EQUAL_PP_AMPL3_MASK 0x0000FFFF00000000ULL /* First Path Amplitude point 3 */ |
||
| 383 | #define RX_EQUAL_PP_AMPL3_SHIFT (32) |
||
| 384 | #define PP_AMPL3_MASK RX_EQUAL_PP_AMPL3_MASK
|
||
| 385 | #define PP_AMPL3_SHIFT RX_EQUAL_PP_AMPL3_SHIFT
|
||
| 386 | /*offset 48*/
|
||
| 387 | #define RX_EQUAL_CIR_MXG_MASK 0xFFFF000000000000ULL /* Channel Impulse Response Max Growth */ |
||
| 388 | #define RX_EQUAL_CIR_MXG_SHIFT (48) |
||
| 389 | #define CIR_MXG_MASK RX_EQUAL_CIR_MXG_MASK
|
||
| 390 | #define CIR_MXG_SHIFT RX_EQUAL_CIR_MXG_SHIFT
|
||
| 391 | |||
| 392 | |||
| 393 | |||
| 394 | /****************************************************************************//** |
||
| 395 | * @brief Bit definitions for register RX_TTCKI
|
||
| 396 | * The value here is the interval over which the timing offset reported
|
||
| 397 | * in the RXTOFS field of Register file: 0x14 RX_TTCKO is measured.
|
||
| 398 | * The clock offset is calculated by dividing RXTTCKI by RXTOFS.
|
||
| 399 | * The value in RXTTCKI will take just one of two values depending on the PRF: 0x01F00000 @ 16 MHz PRF,
|
||
| 400 | * and 0x01FC0000 @ 64 MHz PRF.
|
||
| 401 | **/
|
||
| 402 | #define RX_TTCKI_ID 0x13 /* Receiver Time Tracking Interval (in double buffer set) */ |
||
| 403 | #define RX_TTCKI_LEN (4) |
||
| 404 | |||
| 405 | /****************************************************************************//** |
||
| 406 | * @brief Bit definitions for register RX_TTCKO
|
||
| 407 | **/
|
||
| 408 | #define RX_TTCKO_ID 0x14 /* Receiver Time Tracking Offset (in double buffer set) */ |
||
| 409 | #define RX_TTCKO_LEN (5) /* Note 40 bit register */ |
||
| 410 | /*mask and shift */
|
||
| 411 | #define RX_TTCKO_MASK_32 0xFF07FFFFUL /* Receiver Time Tracking Offset access mask (all unused fields should always be writen as zero) */ |
||
| 412 | /*offset 0 */
|
||
| 413 | #define RX_TTCKO_RXTOFS_MASK 0x0007FFFFUL /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity*/ |
||
| 414 | /*offset 24 */
|
||
| 415 | #define RX_TTCKO_RSMPDEL_MASK 0xFF000000UL /* This 8-bit field reports an internal re-sampler delay value */ |
||
| 416 | /*offset 32 */
|
||
| 417 | #define RX_TTCKO_RCPHASE_MASK 0x7F0000000000ULL /* This 7-bit field reports the receive carrier phase adjustment at time the ranging timestamp is made. */ |
||
| 418 | |||
| 419 | |||
| 420 | /****************************************************************************//** |
||
| 421 | * @brief Bit definitions for register RX_TIME
|
||
| 422 | **/
|
||
| 423 | #define RX_TIME_ID 0x15 /* Receive Message Time of Arrival (in double buffer set) */ |
||
| 424 | #define RX_TIME_LLEN (14) |
||
| 425 | #define RX_TIME_RX_STAMP_LEN (5) /* read only 5 bytes (the adjusted timestamp (40:0)) */ |
||
| 426 | #define RX_STAMP_LEN RX_TIME_RX_STAMP_LEN
|
||
| 427 | /*mask and shift */
|
||
| 428 | #define RX_TIME_RX_STAMP_OFFSET (0) /* byte 0..4 40 bit Reports the fully adjusted time of reception. */ |
||
| 429 | #define RX_TIME_FP_INDEX_OFFSET (5) /* byte 5..6 16 bit First path index. */ |
||
| 430 | #define RX_TIME_FP_AMPL1_OFFSET (7) /* byte 7..8 16 bit First Path Amplitude point 1 */ /* doc bug */ |
||
| 431 | #define RX_TIME_FP_RAWST_OFFSET (9) /* byte 9..13 40 bit Raw Timestamp for the frame */ |
||
| 432 | |||
| 433 | |||
| 434 | /****************************************************************************//** |
||
| 435 | * @brief Bit definitions for register
|
||
| 436 | **/
|
||
| 437 | #define REG_16_ID_RESERVED 0x16 |
||
| 438 | |||
| 439 | |||
| 440 | /****************************************************************************//** |
||
| 441 | * @brief Bit definitions for register
|
||
| 442 | **/
|
||
| 443 | #define TX_TIME_ID 0x17 /* Transmit Message Time of Sending */ |
||
| 444 | #define TX_TIME_LLEN (10) |
||
| 445 | #define TX_TIME_TX_STAMP_LEN (5) /* 40-bits = 5 bytes */ |
||
| 446 | #define TX_STAMP_LEN TX_TIME_TX_STAMP_LEN
|
||
| 447 | /*mask and shift */
|
||
| 448 | #define TX_TIME_TX_STAMP_OFFSET (0) /* byte 0..4 40 bit Reports the fully adjusted time of transmission */ |
||
| 449 | #define TX_TIME_TX_RAWST_OFFSET (5) /* byte 5..9 40 bit Raw Timestamp for the frame */ |
||
| 450 | |||
| 451 | |||
| 452 | |||
| 453 | |||
| 454 | /****************************************************************************//** |
||
| 455 | * @brief Bit definitions for register TX_ANTD
|
||
| 456 | **/
|
||
| 457 | #define TX_ANTD_ID 0x18 /* 16-bit Delay from Transmit to Antenna */ |
||
| 458 | #define TX_ANTD_OFFSET 0x00 |
||
| 459 | #define TX_ANTD_LEN (2) |
||
| 460 | |||
| 461 | |||
| 462 | |||
| 463 | |||
| 464 | /****************************************************************************//** |
||
| 465 | * @brief Bit definitions for register SYS_STATES
|
||
| 466 | * Register map register file 0x19 is reserved
|
||
| 467 | *
|
||
| 468 | **/
|
||
| 469 | #define SYS_STATE_ID 0x19 /* System State information READ ONLY */ |
||
| 470 | #define SYS_STATE_LEN (5) |
||
| 471 | |||
| 472 | /****************************************************************************//** |
||
| 473 | * @brief Bit definitions for register ACK_RESP_T
|
||
| 474 | **/
|
||
| 475 | /* Acknowledge (31:24 preamble symbol delay before auto ACK is sent) and respose (19:0 - unit 1us) timer */
|
||
| 476 | #define ACK_RESP_T_ID 0x1A /* Acknowledgement Time and Response Time */ |
||
| 477 | #define ACK_RESP_T_LEN (4) |
||
| 478 | /*mask and shift */
|
||
| 479 | #define ACK_RESP_T_MASK 0xFF0FFFFFUL /* Acknowledgement Time and Response access mask */ |
||
| 480 | #define ACK_RESP_T_W4R_TIM_OFFSET 0 /* In bytes */ |
||
| 481 | #define ACK_RESP_T_W4R_TIM_MASK 0x000FFFFFUL /* Wait-for-Response turn-around Time 20 bit field */ |
||
| 482 | #define W4R_TIM_MASK ACK_RESP_T_W4R_TIM_MASK
|
||
| 483 | #define ACK_RESP_T_ACK_TIM_OFFSET 3 /* In bytes */ |
||
| 484 | #define ACK_RESP_T_ACK_TIM_MASK 0xFF000000UL /* Auto-Acknowledgement turn-around Time */ |
||
| 485 | #define ACK_TIM_MASK ACK_RESP_T_ACK_TIM_MASK
|
||
| 486 | |||
| 487 | |||
| 488 | |||
| 489 | /****************************************************************************//** |
||
| 490 | * @brief Bit definitions for register 0x1B 0x1C
|
||
| 491 | **/
|
||
| 492 | #define REG_1B_ID_RESERVED 0x1B |
||
| 493 | #define REG_1C_ID_RESERVED 0x1C |
||
| 494 | |||
| 495 | /****************************************************************************//** |
||
| 496 | * @brief Bit definitions for register RX_SNIFF
|
||
| 497 | * Sniff Mode Configuration or Pulsed Preamble Reception Configuration
|
||
| 498 | **/
|
||
| 499 | #define RX_SNIFF_ID 0x1D /* Sniff Mode Configuration */ |
||
| 500 | #define RX_SNIFF_OFFSET 0x00 |
||
| 501 | #define RX_SNIFF_LEN (4) |
||
| 502 | /*mask and shift */
|
||
| 503 | #define RX_SNIFF_MASK 0x0000FF0FUL /* */ |
||
| 504 | #define RX_SNIFF_SNIFF_ONT_MASK 0x0000000FUL /* SNIFF Mode ON time. Specified in units of PAC */ |
||
| 505 | #define SNIFF_ONT_MASK RX_SNIFF_SNIFF_ONT_MASK
|
||
| 506 | #define RX_SNIFF_SNIFF_OFFT_MASK 0x0000FF00UL /* SNIFF Mode OFF time specified in units of approximately 1mkS, or 128 system clock cycles.*/ |
||
| 507 | #define SNIFF_OFFT_MASK RX_SNIFF_SNIFF_OFFT_MASK
|
||
| 508 | |||
| 509 | |||
| 510 | |||
| 511 | /****************************************************************************//** |
||
| 512 | * @brief Bit definitions for register TX_POWER
|
||
| 513 | **/
|
||
| 514 | #define TX_POWER_ID 0x1E /* TX Power Control */ |
||
| 515 | #define TX_POWER_LEN (4) |
||
| 516 | /*mask and shift definition for Smart Transmit Power Control*/
|
||
| 517 | #define TX_POWER_BOOSTNORM_MASK 0x00000000UL /* This is the normal power setting used for frames that do not fall */ |
||
| 518 | #define BOOSTNORM_MASK TX_POWER_BOOSTNORM_MASK
|
||
| 519 | #define TX_POWER_BOOSTNORM_SHIFT (0) |
||
| 520 | #define TX_POWER_BOOSTP500_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.5 ms duration */ |
||
| 521 | #define BOOSTP500_MASK TX_POWER_BOOSTP500_MASK
|
||
| 522 | #define TX_POWER_BOOSTP500_SHIFT (8) |
||
| 523 | #define TX_POWER_BOOSTP250_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.25 ms duration */ |
||
| 524 | #define BOOSTP250_MASK TX_POWER_BOOSTP250_MASK
|
||
| 525 | #define TX_POWER_BOOSTP250_SHIFT (16) |
||
| 526 | #define TX_POWER_BOOSTP125_MASK 0x00000000UL /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.125 ms */ |
||
| 527 | #define BOOSTP125_MASK TX_POWER_BOOSTP125_MASK
|
||
| 528 | #define TX_POWER_BOOSTP125_SHIFT (24) |
||
| 529 | /*mask and shift definition for Manual Transmit Power Control (DIS_STXP=1 in SYS_CFG)*/
|
||
| 530 | #define TX_POWER_MAN_DEFAULT 0x0E080222UL |
||
| 531 | #define TX_POWER_TXPOWPHR_MASK 0x0000FF00UL /* This power setting is applied during the transmission of the PHY header (PHR) portion of the frame. */ |
||
| 532 | #define TX_POWER_TXPOWSD_MASK 0x00FF0000UL /* This power setting is applied during the transmission of the synchronisation header (SHR) and data portions of the frame. */ |
||
| 533 | |||
| 534 | |||
| 535 | /****************************************************************************//** |
||
| 536 | * @brief Bit definitions for register CHAN_CTRL
|
||
| 537 | **/
|
||
| 538 | #define CHAN_CTRL_ID 0x1F /* Channel Control */ |
||
| 539 | #define CHAN_CTRL_LEN (4) |
||
| 540 | /*mask and shift */
|
||
| 541 | #define CHAN_CTRL_MASK 0xFFFF00FFUL /* Channel Control Register access mask */ |
||
| 542 | #define CHAN_CTRL_TX_CHAN_MASK 0x0000000FUL /* Supported channels are 1, 2, 3, 4, 5, and 7.*/ |
||
| 543 | #define CHAN_CTRL_TX_CHAN_SHIFT (0) /* Bits 0..3 TX channel number 0-15 selection */ |
||
| 544 | |||
| 545 | #define CHAN_CTRL_RX_CHAN_MASK 0x000000F0UL |
||
| 546 | #define CHAN_CTRL_RX_CHAN_SHIFT (4) /* Bits 4..7 RX channel number 0-15 selection */ |
||
| 547 | |||
| 548 | #define CHAN_CTRL_RXFPRF_MASK 0x000C0000UL /* Bits 18..19 Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */ |
||
| 549 | #define CHAN_CTRL_RXFPRF_SHIFT (18) |
||
| 550 | /* Specific RXFPRF configuration */
|
||
| 551 | #define CHAN_CTRL_RXFPRF_4 0x00000000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */ |
||
| 552 | #define CHAN_CTRL_RXFPRF_16 0x00040000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */ |
||
| 553 | #define CHAN_CTRL_RXFPRF_64 0x00080000UL /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */ |
||
| 554 | #define CHAN_CTRL_TX_PCOD_MASK 0x07C00000UL /* Bits 22..26 TX Preamble Code selection, 1 to 24. */ |
||
| 555 | #define CHAN_CTRL_TX_PCOD_SHIFT (22) |
||
| 556 | #define CHAN_CTRL_RX_PCOD_MASK 0xF8000000UL /* Bits 27..31 RX Preamble Code selection, 1 to 24. */ |
||
| 557 | #define CHAN_CTRL_RX_PCOD_SHIFT (27) |
||
| 558 | /*offset 16 */
|
||
| 559 | #define CHAN_CTRL_DWSFD 0x00020000UL /* Bit 17 This bit enables a non-standard DecaWave proprietary SFD sequence. */ |
||
| 560 | #define CHAN_CTRL_DWSFD_SHIFT (17) |
||
| 561 | #define CHAN_CTRL_TNSSFD 0x00100000UL /* Bit 20 Non-standard SFD in the transmitter */ |
||
| 562 | #define CHAN_CTRL_TNSSFD_SHIFT (20) |
||
| 563 | #define CHAN_CTRL_RNSSFD 0x00200000UL /* Bit 21 Non-standard SFD in the receiver */ |
||
| 564 | #define CHAN_CTRL_RNSSFD_SHIFT (21) |
||
| 565 | |||
| 566 | |||
| 567 | |||
| 568 | |||
| 569 | /****************************************************************************//** |
||
| 570 | * @brief Bit definitions for register 0x20
|
||
| 571 | **/
|
||
| 572 | #define REG_20_ID_RESERVED 0x20 |
||
| 573 | |||
| 574 | /****************************************************************************//** |
||
| 575 | * @brief Bit definitions for register USR_SFD
|
||
| 576 | * Please read User Manual : User defined SFD sequence
|
||
| 577 | **/
|
||
| 578 | #define USR_SFD_ID 0x21 /* User-specified short/long TX/RX SFD sequences */ |
||
| 579 | #define USR_SFD_LEN (41) |
||
| 580 | #define DW_NS_SFD_LEN_110K 64 /* Decawave non-standard SFD length for 110 kbps */ |
||
| 581 | #define DW_NS_SFD_LEN_850K 16 /* Decawave non-standard SFD length for 850 kbps */ |
||
| 582 | #define DW_NS_SFD_LEN_6M8 8 /* Decawave non-standard SFD length for 6.8 Mbps */ |
||
| 583 | |||
| 584 | |||
| 585 | /****************************************************************************//** |
||
| 586 | * @brief Bit definitions for register
|
||
| 587 | **/
|
||
| 588 | #define REG_22_ID_RESERVED 0x22 |
||
| 589 | |||
| 590 | /****************************************************************************//** |
||
| 591 | * @brief Bit definitions for register AGC_CTRL
|
||
| 592 | * Please take care to write to this register as doing so may cause the DW1000 to malfunction
|
||
| 593 | **/
|
||
| 594 | #define AGC_CTRL_ID 0x23 /* Automatic Gain Control configuration */ |
||
| 595 | #define AGC_CTRL_LEN (32) |
||
| 596 | #define AGC_CFG_STS_ID AGC_CTRL_ID
|
||
| 597 | /* offset from AGC_CTRL_ID in bytes */
|
||
| 598 | #define AGC_CTRL1_OFFSET (0x02) |
||
| 599 | #define AGC_CTRL1_LEN (2) |
||
| 600 | #define AGC_CTRL1_MASK 0x0001 /* access mask to AGC configuration and control register */ |
||
| 601 | #define AGC_CTRL1_DIS_AM 0x0001 /* Disable AGC Measurement. The DIS_AM bit is set by default. */ |
||
| 602 | /* offset from AGC_CTRL_ID in bytes */
|
||
| 603 | /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
|
||
| 604 | #define AGC_TUNE1_OFFSET (0x04) |
||
| 605 | #define AGC_TUNE1_LEN (2) |
||
| 606 | #define AGC_TUNE1_MASK 0xFFFF /* It is a 16-bit tuning register for the AGC. */ |
||
| 607 | #define AGC_TUNE1_16M 0x8870 |
||
| 608 | #define AGC_TUNE1_64M 0x889B |
||
| 609 | /* offset from AGC_CTRL_ID in bytes */
|
||
| 610 | /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
|
||
| 611 | #define AGC_TUNE2_OFFSET (0x0C) |
||
| 612 | #define AGC_TUNE2_LEN (4) |
||
| 613 | #define AGC_TUNE2_MASK 0xFFFFFFFFUL |
||
| 614 | #define AGC_TUNE2_VAL 0X2502A907UL |
||
| 615 | /* offset from AGC_CTRL_ID in bytes */
|
||
| 616 | /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
|
||
| 617 | #define AGC_TUNE3_OFFSET (0x12) |
||
| 618 | #define AGC_TUNE3_LEN (2) |
||
| 619 | #define AGC_TUNE3_MASK 0xFFFF |
||
| 620 | #define AGC_TUNE3_VAL 0X0055 |
||
| 621 | /* offset from AGC_CTRL_ID in bytes */
|
||
| 622 | #define AGC_STAT1_OFFSET (0x1E) |
||
| 623 | #define AGC_STAT1_LEN (3) |
||
| 624 | #define AGC_STAT1_MASK 0x0FFFFF |
||
| 625 | #define AGC_STAT1_EDG1_MASK 0x0007C0 /* This 5-bit gain value relates to input noise power measurement. */ |
||
| 626 | #define AGC_STAT1_EDG2_MASK 0x0FF800 /* This 9-bit value relates to the input noise power measurement. */ |
||
| 627 | |||
| 628 | /****************************************************************************//** |
||
| 629 | * @brief Bit definitions for register EXT_SYNC
|
||
| 630 | **/
|
||
| 631 | #define EXT_SYNC_ID 0x24 /* External synchronisation control */ |
||
| 632 | #define EXT_SYNC_LEN (12) |
||
| 633 | /* offset from EXT_SYNC_ID in bytes */
|
||
| 634 | #define EC_CTRL_OFFSET (0x00) |
||
| 635 | #define EC_CTRL_LEN (4) |
||
| 636 | #define EC_CTRL_MASK 0x00000FFBUL /* sub-register 0x00 is the External clock synchronisation counter configuration register */ |
||
| 637 | #define EC_CTRL_OSTSM 0x00000001UL /* External transmit synchronisation mode enable */ |
||
| 638 | #define EC_CTRL_OSRSM 0x00000002UL /* External receive synchronisation mode enable */ |
||
| 639 | #define EC_CTRL_PLLLCK 0x04 /* PLL lock detect enable */ |
||
| 640 | #define EC_CTRL_OSTRM 0x00000800UL /* External timebase reset mode enable */ |
||
| 641 | #define EC_CTRL_WAIT_MASK 0x000007F8UL /* Wait counter used for external transmit synchronisation and external timebase reset */ |
||
| 642 | /* offset from EXT_SYNC_ID in bytes */
|
||
| 643 | #define EC_RXTC_OFFSET (0x04) |
||
| 644 | #define EC_RXTC_LEN (4) |
||
| 645 | #define EC_RXTC_MASK 0xFFFFFFFFUL /* External clock synchronisation counter captured on RMARKER */ |
||
| 646 | /* offset from EXT_SYNC_ID in bytes */
|
||
| 647 | #define EC_GOLP (0x08) |
||
| 648 | #define EC_GOLP_LEN (4) |
||
| 649 | #define EC_GOLP_MASK 0x0000003FUL /* sub-register 0x08 is the External clock offset to first path 1 GHz counter, EC_GOLP */ |
||
| 650 | #define EC_GOLP_OFFSET_EXT_MASK 0x0000003FUL /* This register contains the 1 GHz count from the arrival of the RMARKER and the next edge of the external clock. */ |
||
| 651 | |||
| 652 | |||
| 653 | /****************************************************************************//** |
||
| 654 | * @brief Bit definitions for register ACC_MEM
|
||
| 655 | **/
|
||
| 656 | #define ACC_MEM_ID 0x25 /* Read access to accumulator data */ |
||
| 657 | #define ACC_MEM_LEN (4064) |
||
| 658 | |||
| 659 | |||
| 660 | /****************************************************************************//** |
||
| 661 | * @brief Bit definitions for register GPIO_CTRL
|
||
| 662 | **/
|
||
| 663 | #define GPIO_CTRL_ID 0x26 /* Peripheral register bus 1 access - GPIO control */ |
||
| 664 | #define GPIO_CTRL_LEN (44) |
||
| 665 | |||
| 666 | /* offset from GPIO_CTRL in bytes */
|
||
| 667 | #define GPIO_MODE_OFFSET 0x00 /* sub-register 0x00 is the GPIO Mode Control Register */ |
||
| 668 | #define GPIO_MODE_LEN (4) |
||
| 669 | #define GPIO_MODE_MASK 0x00FFFFC0UL |
||
| 670 | |||
| 671 | #define GPIO_MSGP0_MASK 0x000000C0UL /* Mode Selection for GPIO0/RXOKLED */ |
||
| 672 | #define GPIO_MSGP1_MASK 0x00000300UL /* Mode Selection for GPIO1/SFDLED */ |
||
| 673 | #define GPIO_MSGP2_MASK 0x00000C00UL /* Mode Selection for GPIO2/RXLED */ |
||
| 674 | #define GPIO_MSGP3_MASK 0x00003000UL /* Mode Selection for GPIO3/TXLED */ |
||
| 675 | #define GPIO_MSGP4_MASK 0x0000C000UL /* Mode Selection for GPIO4/EXTPA */ |
||
| 676 | #define GPIO_MSGP5_MASK 0x00030000UL /* Mode Selection for GPIO5/EXTTXE */ |
||
| 677 | #define GPIO_MSGP6_MASK 0x000C0000UL /* Mode Selection for GPIO6/EXTRXE */ |
||
| 678 | #define GPIO_MSGP7_MASK 0x00300000UL /* Mode Selection for SYNC/GPIO7 */ |
||
| 679 | #define GPIO_MSGP8_MASK 0x00C00000UL /* Mode Selection for IRQ/GPIO8 */ |
||
| 680 | |||
| 681 | #define GPIO_PIN2_RXLED 0x00000400UL /* The pin operates as the RXLED output */ |
||
| 682 | #define GPIO_PIN3_TXLED 0x00001000UL /* The pin operates as the TXLED output */ |
||
| 683 | #define GPIO_PIN4_EXTPA 0x00004000UL /* The pin operates as the EXTPA output */ |
||
| 684 | #define GPIO_PIN5_EXTTXE 0x00010000UL /* The pin operates as the EXTTXE output */ |
||
| 685 | #define GPIO_PIN6_EXTRXE 0x00040000UL /* The pin operates as the EXTRXE output */ |
||
| 686 | |||
| 687 | /* offset from GPIO_CTRL in bytes */
|
||
| 688 | #define GPIO_DIR_OFFSET 0x08 /* sub-register 0x08 is the GPIO Direction Control Register */ |
||
| 689 | #define GPIO_DIR_LEN (3) |
||
| 690 | #define GPIO_DIR_MASK 0x0011FFFFUL |
||
| 691 | |||
| 692 | #define GxP0 0x00000001UL /* GPIO0 Only changed if the GxM0 mask bit has a value of 1 for the write operation*/ |
||
| 693 | #define GxP1 0x00000002UL /* GPIO1. (See GDP0). */ |
||
| 694 | #define GxP2 0x00000004UL /* GPIO2. (See GDP0). */ |
||
| 695 | #define GxP3 0x00000008UL /* GPIO3. (See GDP0). */ |
||
| 696 | #define GxP4 0x00000100UL /* GPIO4. (See GDP0). */ |
||
| 697 | #define GxP5 0x00000200UL /* GPIO5. (See GDP0). */ |
||
| 698 | #define GxP6 0x00000400UL /* GPIO6. (See GDP0). */ |
||
| 699 | #define GxP7 0x00000800UL /* GPIO7. (See GDP0). */ |
||
| 700 | #define GxP8 0x00010000UL /* GPIO8 */ |
||
| 701 | |||
| 702 | #define GxM0 0x00000010UL /* Mask for GPIO0 */ |
||
| 703 | #define GxM1 0x00000020UL /* Mask for GPIO1. (See GDM0). */ |
||
| 704 | #define GxM2 0x00000040UL /* Mask for GPIO2. (See GDM0). */ |
||
| 705 | #define GxM3 0x00000080UL /* Mask for GPIO3. (See GDM0). */ |
||
| 706 | #define GxM4 0x00001000UL /* Mask for GPIO4. (See GDM0). */ |
||
| 707 | #define GxM5 0x00002000UL /* Mask for GPIO5. (See GDM0). */ |
||
| 708 | #define GxM6 0x00004000UL /* Mask for GPIO6. (See GDM0). */ |
||
| 709 | #define GxM7 0x00008000UL /* Mask for GPIO7. (See GDM0). */ |
||
| 710 | #define GxM8 0x00100000UL /* Mask for GPIO8. (See GDM0). */ |
||
| 711 | |||
| 712 | #define GDP0 GxP0 /* Direction Selection for GPIO0. 1 = input, 0 = output. Only changed if the GDM0 mask bit has a value of 1 for the write operation*/ |
||
| 713 | #define GDP1 GxP1 /* Direction Selection for GPIO1. (See GDP0). */ |
||
| 714 | #define GDP2 GxP2 /* Direction Selection for GPIO2. (See GDP0). */ |
||
| 715 | #define GDP3 GxP3 /* Direction Selection for GPIO3. (See GDP0). */ |
||
| 716 | #define GDP4 GxP4 /* Direction Selection for GPIO4. (See GDP0). */ |
||
| 717 | #define GDP5 GxP5 /* Direction Selection for GPIO5. (See GDP0). */ |
||
| 718 | #define GDP6 GxP6 /* Direction Selection for GPIO6. (See GDP0). */ |
||
| 719 | #define GDP7 GxP7 /* Direction Selection for GPIO7. (See GDP0). */ |
||
| 720 | #define GDP8 GxP8 /* Direction Selection for GPIO8 */ |
||
| 721 | |||
| 722 | #define GDM0 GxM0 /* Mask for setting the direction of GPIO0 */ |
||
| 723 | #define GDM1 GxM1 /* Mask for setting the direction of GPIO1. (See GDM0). */ |
||
| 724 | #define GDM2 GxM2 /* Mask for setting the direction of GPIO2. (See GDM0). */ |
||
| 725 | #define GDM3 GxM3 /* Mask for setting the direction of GPIO3. (See GDM0). */ |
||
| 726 | #define GDM4 GxM4 /* Mask for setting the direction of GPIO4. (See GDM0). */ |
||
| 727 | #define GDM5 GxM5 /* Mask for setting the direction of GPIO5. (See GDM0). */ |
||
| 728 | #define GDM6 GxM6 /* Mask for setting the direction of GPIO6. (See GDM0). */ |
||
| 729 | #define GDM7 GxM7 /* Mask for setting the direction of GPIO7. (See GDM0). */ |
||
| 730 | #define GDM8 GxM8 /* Mask for setting the direction of GPIO8. (See GDM0). */ |
||
| 731 | |||
| 732 | /* offset from GPIO_CTRL in bytes */
|
||
| 733 | #define GPIO_DOUT_OFFSET 0x0C /* sub-register 0x0C is the GPIO data output register. */ |
||
| 734 | #define GPIO_DOUT_LEN (3) |
||
| 735 | #define GPIO_DOUT_MASK GPIO_DIR_MASK
|
||
| 736 | |||
| 737 | /* offset from GPIO_CTRL in bytes */
|
||
| 738 | #define GPIO_IRQE_OFFSET 0x10 /* sub-register 0x10 is the GPIO interrupt enable register */ |
||
| 739 | #define GPIO_IRQE_LEN (4) |
||
| 740 | #define GPIO_IRQE_MASK 0x000001FFUL |
||
| 741 | #define GIRQx0 0x00000001UL /* IRQ bit0 */ |
||
| 742 | #define GIRQx1 0x00000002UL /* IRQ bit1 */ |
||
| 743 | #define GIRQx2 0x00000004UL /* IRQ bit2 */ |
||
| 744 | #define GIRQx3 0x00000008UL /* IRQ bit3 */ |
||
| 745 | #define GIRQx4 0x00000010UL /* IRQ bit4 */ |
||
| 746 | #define GIRQx5 0x00000020UL /* IRQ bit5 */ |
||
| 747 | #define GIRQx6 0x00000040UL /* IRQ bit6 */ |
||
| 748 | #define GIRQx7 0x00000080UL /* IRQ bit7 */ |
||
| 749 | #define GIRQx8 0x00000100UL /* IRQ bit8 */ |
||
| 750 | #define GIRQE0 GIRQx0 /* GPIO IRQ Enable for GPIO0 input. Value 1 = enable, 0 = disable*/ |
||
| 751 | #define GIRQE1 GIRQx1 /* */ |
||
| 752 | #define GIRQE2 GIRQx2 /* */ |
||
| 753 | #define GIRQE3 GIRQx3 /* */ |
||
| 754 | #define GIRQE4 GIRQx4 /* */ |
||
| 755 | #define GIRQE5 GIRQx5 /* */ |
||
| 756 | #define GIRQE6 GIRQx6 /* */ |
||
| 757 | #define GIRQE7 GIRQx7 /* */ |
||
| 758 | #define GIRQE8 GIRQx8 /* Value 1 = enable, 0 = disable */ |
||
| 759 | |||
| 760 | /* offset from GPIO_CTRL in bytes */
|
||
| 761 | #define GPIO_ISEN_OFFSET 0x14 /* sub-register 0x14 is the GPIO interrupt sense selection register */ |
||
| 762 | #define GPIO_ISEN_LEN (4) |
||
| 763 | #define GPIO_ISEN_MASK GPIO_IRQE_MASK
|
||
| 764 | #define GISEN0 GIRQx0 /* GPIO IRQ Sense selection GPIO0 input. Value 0 = High or Rising-Edge, 1 = Low or falling-edge.*/ |
||
| 765 | #define GISEN1 GIRQx1 /* */ |
||
| 766 | #define GISEN2 GIRQx2 /* */ |
||
| 767 | #define GISEN3 GIRQx3 /* */ |
||
| 768 | #define GISEN4 GIRQx4 /* */ |
||
| 769 | #define GISEN5 GIRQx5 /* */ |
||
| 770 | #define GISEN6 GIRQx6 /* */ |
||
| 771 | #define GISEN7 GIRQx7 /* */ |
||
| 772 | #define GISEN8 GIRQx8 /* Value 0 = High or Rising-Edge, 1 = Low or falling-edge */ |
||
| 773 | |||
| 774 | /* offset from GPIO_CTRL in bytes */
|
||
| 775 | #define GPIO_IMODE_OFFSET 0x18 /* sub-register 0x18 is the GPIO interrupt mode selection register */ |
||
| 776 | #define GPIO_IMODE_LEN (4) |
||
| 777 | #define GPIO_IMODE_MASK GPIO_IRQE_MASK
|
||
| 778 | #define GIMOD0 GIRQx0 /* GPIO IRQ Mode selection for GPIO0 input. Value 0 = Level sensitive interrupt. Value 1 = Edge triggered interrupt */ |
||
| 779 | #define GIMOD1 GIRQx1 /* */ |
||
| 780 | #define GIMOD2 GIRQx2 /* */ |
||
| 781 | #define GIMOD3 GIRQx3 /* */ |
||
| 782 | #define GIMOD4 GIRQx4 /* */ |
||
| 783 | #define GIMOD5 GIRQx5 /* */ |
||
| 784 | #define GIMOD6 GIRQx6 /* */ |
||
| 785 | #define GIMOD7 GIRQx7 /* */ |
||
| 786 | #define GIMOD8 GIRQx8 /* Value 0 = Level, 1 = Edge. */ |
||
| 787 | |||
| 788 | /* offset from EXT_SYNC_ID in bytes */
|
||
| 789 | #define GPIO_IBES_OFFSET 0x1C /* sub-register 0x1C is the GPIO interrupt Both Edge selection register */ |
||
| 790 | #define GPIO_IBES_LEN (4) |
||
| 791 | #define GPIO_IBES_MASK GPIO_IRQE_MASK /* */ |
||
| 792 | #define GIBES0 GIRQx0 /* GPIO IRQ Both Edge selection for GPIO0 input. Value 0 = GPIO_IMODE register selects the edge. Value 1 = Both edges trigger the interrupt. */ |
||
| 793 | #define GIBES1 GIRQx1 /* */ |
||
| 794 | #define GIBES2 GIRQx2 /* */ |
||
| 795 | #define GIBES3 GIRQx3 /* */ |
||
| 796 | #define GIBES4 GIRQx4 /* */ |
||
| 797 | #define GIBES5 GIRQx5 /* */ |
||
| 798 | #define GIBES6 GIRQx6 /* */ |
||
| 799 | #define GIBES7 GIRQx7 /* */ |
||
| 800 | #define GIBES8 GIRQx8 /* Value 0 = use GPIO_IMODE, 1 = Both Edges */ |
||
| 801 | |||
| 802 | /* offset from GPIO_CTRL in bytes */
|
||
| 803 | #define GPIO_ICLR_OFFSET 0x20 /* sub-register 0x20 is the GPIO interrupt clear register */ |
||
| 804 | #define GPIO_ICLR_LEN (4) |
||
| 805 | #define GPIO_ICLR_MASK GPIO_IRQE_MASK /* */ |
||
| 806 | #define GICLR0 GIRQx0 /* GPIO IRQ latch clear for GPIO0 input. Write 1 to clear the GPIO0 interrupt latch. Writing 0 has no effect. Reading returns zero */ |
||
| 807 | #define GICLR1 GIRQx1 /* */ |
||
| 808 | #define GICLR2 GIRQx2 /* */ |
||
| 809 | #define GICLR3 GIRQx3 /* */ |
||
| 810 | #define GICLR4 GIRQx4 /* */ |
||
| 811 | #define GICLR5 GIRQx5 /* */ |
||
| 812 | #define GICLR6 GIRQx6 /* */ |
||
| 813 | #define GICLR7 GIRQx7 /* */ |
||
| 814 | #define GICLR8 GIRQx8 /* Write 1 to clear the interrupt latch */ |
||
| 815 | |||
| 816 | /* offset from GPIO_CTRL in bytes */
|
||
| 817 | #define GPIO_IDBE_OFFSET 0x24 /* sub-register 0x24 is the GPIO interrupt de-bounce enable register */ |
||
| 818 | #define GPIO_IDBE_LEN (4) |
||
| 819 | #define GPIO_IDBE_MASK GPIO_IRQE_MASK
|
||
| 820 | #define GIDBE0 GIRQx0 /* GPIO IRQ de-bounce enable for GPIO0. Value 1 = de-bounce enabled. Value 0 = de-bounce disabled */ |
||
| 821 | #define GIDBE1 GIRQx1 /* */ |
||
| 822 | #define GIDBE2 GIRQx2 /* */ |
||
| 823 | #define GIDBE3 GIRQx3 /* */ |
||
| 824 | #define GIDBE4 GIRQx4 /* */ |
||
| 825 | #define GIDBE5 GIRQx5 /* */ |
||
| 826 | #define GIDBE6 GIRQx6 /* */ |
||
| 827 | #define GIDBE7 GIRQx7 /* */ |
||
| 828 | #define GIDBE8 GIRQx8 /* Value 1 = de-bounce enabled, 0 = de-bounce disabled */ |
||
| 829 | |||
| 830 | /* offset from GPIO_CTRL in bytes */
|
||
| 831 | #define GPIO_RAW_OFFSET 0x28 /* sub-register 0x28 allows the raw state of the GPIO pin to be read. */ |
||
| 832 | #define GPIO_RAW_LEN (4) |
||
| 833 | #define GPIO_RAW_MASK GPIO_IRQE_MASK
|
||
| 834 | #define GRAWP0 GIRQx0 /* This bit reflects the raw state of GPIO0 */ |
||
| 835 | #define GRAWP1 GIRQx1 /* */ |
||
| 836 | #define GRAWP2 GIRQx2 /* */ |
||
| 837 | #define GRAWP3 GIRQx3 /* */ |
||
| 838 | #define GRAWP4 GIRQx4 /* */ |
||
| 839 | #define GRAWP5 GIRQx5 /* */ |
||
| 840 | #define GRAWP6 GIRQx6 /* */ |
||
| 841 | #define GRAWP7 GIRQx7 /* */ |
||
| 842 | #define GRAWP8 GIRQx8 /* This bit reflects the raw state of GPIO8 */ |
||
| 843 | |||
| 844 | /****************************************************************************//** |
||
| 845 | * @brief Bit definitions for register DRX_CONF
|
||
| 846 | * Digital Receiver configuration block
|
||
| 847 | **/
|
||
| 848 | #define DRX_CONF_ID 0x27 /* Digital Receiver configuration */ |
||
| 849 | #define DRX_CONF_LEN (44) |
||
| 850 | /* offset from DRX_CONF_ID in bytes */
|
||
| 851 | #define DRX_TUNE0b_OFFSET (0x02) /* sub-register 0x02 is a 16-bit tuning register. */ |
||
| 852 | #define DRX_TUNE0b_LEN (2) |
||
| 853 | #define DRX_TUNE0b_MASK 0xFFFF /* 7.2.40.2 Sub-Register 0x27:02 DRX_TUNE0b */ |
||
| 854 | #define DRX_TUNE0b_110K_STD 0x000A |
||
| 855 | #define DRX_TUNE0b_110K_NSTD 0x0016 |
||
| 856 | #define DRX_TUNE0b_850K_STD 0x0001 |
||
| 857 | #define DRX_TUNE0b_850K_NSTD 0x0006 |
||
| 858 | #define DRX_TUNE0b_6M8_STD 0x0001 |
||
| 859 | #define DRX_TUNE0b_6M8_NSTD 0x0002 |
||
| 860 | |||
| 861 | /* offset from DRX_CONF_ID in bytes */
|
||
| 862 | #define DRX_TUNE1a_OFFSET 0x04 /* 7.2.40.3 Sub-Register 0x27:04 DRX_TUNE1a */ |
||
| 863 | #define DRX_TUNE1a_LEN (2) |
||
| 864 | #define DRX_TUNE1a_MASK 0xFFFF |
||
| 865 | #define DRX_TUNE1a_PRF16 0x0087 |
||
| 866 | #define DRX_TUNE1a_PRF64 0x008D |
||
| 867 | |||
| 868 | /* offset from DRX_CONF_ID in bytes */
|
||
| 869 | #define DRX_TUNE1b_OFFSET 0x06 /* 7.2.40.4 Sub-Register 0x27:06 DRX_TUNE1b */ |
||
| 870 | #define DRX_TUNE1b_LEN (2) |
||
| 871 | #define DRX_TUNE1b_MASK 0xFFFF |
||
| 872 | #define DRX_TUNE1b_110K 0x0064 |
||
| 873 | #define DRX_TUNE1b_850K_6M8 0x0020 |
||
| 874 | #define DRX_TUNE1b_6M8_PRE64 0x0010 |
||
| 875 | |||
| 876 | /* offset from DRX_CONF_ID in bytes */
|
||
| 877 | #define DRX_TUNE2_OFFSET 0x08 /* 7.2.40.5 Sub-Register 0x27:08 DRX_TUNE2 */ |
||
| 878 | #define DRX_TUNE2_LEN (4) |
||
| 879 | #define DRX_TUNE2_MASK 0xFFFFFFFFUL |
||
| 880 | #define DRX_TUNE2_PRF16_PAC8 0x311A002DUL |
||
| 881 | #define DRX_TUNE2_PRF16_PAC16 0x331A0052UL |
||
| 882 | #define DRX_TUNE2_PRF16_PAC32 0x351A009AUL |
||
| 883 | #define DRX_TUNE2_PRF16_PAC64 0x371A011DUL |
||
| 884 | #define DRX_TUNE2_PRF64_PAC8 0x313B006BUL |
||
| 885 | #define DRX_TUNE2_PRF64_PAC16 0x333B00BEUL |
||
| 886 | #define DRX_TUNE2_PRF64_PAC32 0x353B015EUL |
||
| 887 | #define DRX_TUNE2_PRF64_PAC64 0x373B0296UL |
||
| 888 | |||
| 889 | /* offset from DRX_CONF_ID in bytes */
|
||
| 890 | /* WARNING: Please do NOT set DRX_SFDTOC to zero (disabling SFD detection timeout)
|
||
| 891 | * since this risks IC malfunction due to prolonged receiver activity in the event of false preamble detection.
|
||
| 892 | */
|
||
| 893 | #define DRX_SFDTOC_OFFSET 0x20 /* 7.2.40.7 Sub-Register 0x27:20 DRX_SFDTOC */ |
||
| 894 | #define DRX_SFDTOC_LEN (2) |
||
| 895 | #define DRX_SFDTOC_MASK 0xFFFF |
||
| 896 | |||
| 897 | /* offset from DRX_CONF_ID in bytes */
|
||
| 898 | #define DRX_PRETOC_OFFSET 0x24 /* 7.2.40.9 Sub-Register 0x27:24 DRX_PRETOC */ |
||
| 899 | #define DRX_PRETOC_LEN (2) |
||
| 900 | #define DRX_PRETOC_MASK 0xFFFF |
||
| 901 | |||
| 902 | /* offset from DRX_CONF_ID in bytes */
|
||
| 903 | #define DRX_TUNE4H_OFFSET 0x26 /* 7.2.40.10 Sub-Register 0x27:26 DRX_TUNE4H */ |
||
| 904 | #define DRX_TUNE4H_LEN (2) |
||
| 905 | #define DRX_TUNE4H_MASK 0xFFFF |
||
| 906 | #define DRX_TUNE4H_PRE64 0x0010 |
||
| 907 | #define DRX_TUNE4H_PRE128PLUS 0x0028 |
||
| 908 | |||
| 909 | |||
| 910 | /****************************************************************************//** |
||
| 911 | * @brief Bit definitions for register RF_CONF
|
||
| 912 | * Analog RF Configuration block
|
||
| 913 | * Refer to section 7.2.41 Register file: 0x28 Analog RF configuration block
|
||
| 914 | **/
|
||
| 915 | #define RF_CONF_ID 0x28 /* Analog RF Configuration */ |
||
| 916 | #define RF_CONF_LEN (58) |
||
| 917 | #define RF_CONF_TXEN_MASK 0x00400000UL /* TX enable */ |
||
| 918 | #define RF_CONF_RXEN_MASK 0x00200000UL /* RX enable */ |
||
| 919 | #define RF_CONF_TXPOW_MASK 0x001F0000UL /* turn on power all LDOs */ |
||
| 920 | #define RF_CONF_PLLEN_MASK 0x0000E000UL /* enable PLLs */ |
||
| 921 | #define RF_CONF_PGMIXBIASEN_MASK 0x0000A700UL /* Enable TX mixer bias and pulse gen */ |
||
| 922 | #define RF_CONF_TXBLOCKSEN_MASK 0x00001F00UL /* enable TX blocks */ |
||
| 923 | #define RF_CONF_TXPLLPOWEN_MASK (RF_CONF_PLLEN_MASK | RF_CONF_TXPOW_MASK)
|
||
| 924 | #define RF_CONF_TXALLEN_MASK (RF_CONF_TXEN_MASK | RF_CONF_TXPOW_MASK | RF_CONF_PLLEN_MASK | RF_CONF_TXBLOCKSEN_MASK)
|
||
| 925 | /* offset from TX_CAL_ID in bytes */
|
||
| 926 | #define RF_RXCTRLH_OFFSET 0x0B /* Analog RX Control Register */ |
||
| 927 | #define RF_RXCTRLH_LEN (1) |
||
| 928 | #define RF_RXCTRLH_NBW 0xD8 /* RXCTRLH value for narrow bandwidth channels */ |
||
| 929 | #define RF_RXCTRLH_WBW 0xBC /* RXCTRLH value for wide bandwidth channels */ |
||
| 930 | /* offset from TX_CAL_ID in bytes */
|
||
| 931 | #define RF_TXCTRL_OFFSET 0x0C /* Analog TX Control Register */ |
||
| 932 | #define RF_TXCTRL_LEN (4) |
||
| 933 | #define RF_TXCTRL_TXMTUNE_MASK 0x000001E0UL /* Transmit mixer tuning register */ |
||
| 934 | #define RF_TXCTRL_TXTXMQ_MASK 0x00000E00UL /* Transmit mixer Q-factor tuning register */ |
||
| 935 | #define RF_TXCTRL_CH1 0x00005C40UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 936 | #define RF_TXCTRL_CH2 0x00045CA0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 937 | #define RF_TXCTRL_CH3 0x00086CC0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 938 | #define RF_TXCTRL_CH4 0x00045C80UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 939 | #define RF_TXCTRL_CH5 0x001E3FE0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 940 | #define RF_TXCTRL_CH7 0x001E7DE0UL /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ |
||
| 941 | |||
| 942 | /* offset from TX_CAL_ID in bytes */
|
||
| 943 | #define RF_STATUS_OFFSET 0x2C |
||
| 944 | |||
| 945 | /****************************************************************************//** |
||
| 946 | * @brief Bit definitions for register
|
||
| 947 | **/
|
||
| 948 | #define REG_29_ID_RESERVED 0x29 |
||
| 949 | |||
| 950 | /****************************************************************************//** |
||
| 951 | * @brief Bit definitions for register TX_CAL
|
||
| 952 | * Refer to section 7.2.43 Register file: 0x2A Transmitter Calibration block
|
||
| 953 | **/
|
||
| 954 | #define TX_CAL_ID 0x2A /* Transmitter calibration block */ |
||
| 955 | #define TX_CAL_LEN (52) |
||
| 956 | /* offset from TX_CAL_ID in bytes */
|
||
| 957 | #define TC_SARL_SAR_C (0) /* SAR control */ |
||
| 958 | /*cause bug in register block TX_CAL, we need to read 1 byte in a time*/
|
||
| 959 | #define TC_SARL_SAR_LVBAT_OFFSET (3) /* Latest SAR reading for Voltage level */ |
||
| 960 | #define TC_SARL_SAR_LTEMP_OFFSET (4) /* Latest SAR reading for Temperature level */ |
||
| 961 | #define TC_SARW_SAR_WTEMP_OFFSET 0x06 /* SAR reading of Temperature level taken at last wakeup event */ |
||
| 962 | #define TC_SARW_SAR_WVBAT_OFFSET 0x07 /* SAR reading of Voltage level taken at last wakeup event */ |
||
| 963 | |||
| 964 | #define TC_PGCCTRL_OFFSET 0x08 /* Pulse Generator Calibration control */ |
||
| 965 | #define TC_PGCCTRL_LEN (1) |
||
| 966 | #define TC_PGCCTRL_CALSTART 0x01 /* Start PG cal procedure */ |
||
| 967 | #define TC_PGCCTRL_AUTOCAL 0x02 /* Starts a PG autocalibration loop */ |
||
| 968 | #define TC_PGCCTRL_TMEAS_MASK 0x3C /* Mask to retrieve number of clock cycles over which to run PG cal counter */ |
||
| 969 | #define TC_PGCCTRL_ON_TX 0x40 /* Perform autocal on each TX enable */ |
||
| 970 | #define TC_PGCCTRL_DIR_CONV 0x80 /* Direction (converging) of autocal binary search */ |
||
| 971 | |||
| 972 | #define TC_PGCAL_STATUS_OFFSET 0x09 /* Status register from PG calibration block */ |
||
| 973 | #define TC_PGCAL_STATUS_LEN (1) |
||
| 974 | #define TC_PGCAL_STATUS_DELAY_MASK 0xFFF /* Mask to retrieve PG delay count from calibration */ |
||
| 975 | |||
| 976 | /* offset from TX_CAL_ID in bytes */
|
||
| 977 | #define TC_PGDELAY_OFFSET 0x0B /* Transmitter Calibration Pulse Generator Delay */ |
||
| 978 | #define TC_PGDELAY_LEN (1) |
||
| 979 | #define TC_PGDELAY_CH1 0xC9 /* Recommended value for channel 1 */ |
||
| 980 | #define TC_PGDELAY_CH2 0xC2 /* Recommended value for channel 2 */ |
||
| 981 | #define TC_PGDELAY_CH3 0xC5 /* Recommended value for channel 3 */ |
||
| 982 | #define TC_PGDELAY_CH4 0x95 /* Recommended value for channel 4 */ |
||
| 983 | #define TC_PGDELAY_CH5 0xC0 /* Recommended value for channel 5 */ |
||
| 984 | #define TC_PGDELAY_CH7 0x93 /* Recommended value for channel 7 */ |
||
| 985 | /* offset from TX_CAL_ID in bytes */
|
||
| 986 | #define TC_PGTEST_OFFSET 0x0C /* Transmitter Calibration Pulse Generator Test */ |
||
| 987 | #define TC_PGTEST_LEN (1) |
||
| 988 | #define TC_PGTEST_NORMAL 0x00 /* Normal operation */ |
||
| 989 | #define TC_PGTEST_CW 0x13 /* Continuous Wave (CW) Test Mode */ |
||
| 990 | |||
| 991 | /****************************************************************************//** |
||
| 992 | * @brief Bit definitions for register
|
||
| 993 | * Refer to section 7.2.44 Register file: 0x2B Frequency synthesiser control block
|
||
| 994 | **/
|
||
| 995 | #define FS_CTRL_ID 0x2B /* Frequency synthesiser control block */ |
||
| 996 | #define FS_CTRL_LEN (21) |
||
| 997 | /* offset from FS_CTRL_ID in bytes */
|
||
| 998 | #define FS_RES1_OFFSET 0x00 /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */ |
||
| 999 | #define FS_RES1_LEN (7) |
||
| 1000 | /* offset from FS_CTRL_ID in bytes */
|
||
| 1001 | #define FS_PLLCFG_OFFSET 0x07 /* Frequency synthesiser PLL configuration */ |
||
| 1002 | #define FS_PLLCFG_LEN (5) |
||
| 1003 | #define FS_PLLCFG_CH1 0x09000407UL /* Operating Channel 1 */ |
||
| 1004 | #define FS_PLLCFG_CH2 0x08400508UL /* Operating Channel 2 */ |
||
| 1005 | #define FS_PLLCFG_CH3 0x08401009UL /* Operating Channel 3 */ |
||
| 1006 | #define FS_PLLCFG_CH4 FS_PLLCFG_CH2 /* Operating Channel 4 (same as 2) */ |
||
| 1007 | #define FS_PLLCFG_CH5 0x0800041DUL /* Operating Channel 5 */ |
||
| 1008 | #define FS_PLLCFG_CH7 FS_PLLCFG_CH5 /* Operating Channel 7 (same as 5) */ |
||
| 1009 | /* offset from FS_CTRL_ID in bytes */
|
||
| 1010 | #define FS_PLLTUNE_OFFSET 0x0B /* Frequency synthesiser PLL Tuning */ |
||
| 1011 | #define FS_PLLTUNE_LEN (1) |
||
| 1012 | #define FS_PLLTUNE_CH1 0x1E /* Operating Channel 1 */ |
||
| 1013 | #define FS_PLLTUNE_CH2 0x26 /* Operating Channel 2 */ |
||
| 1014 | #define FS_PLLTUNE_CH3 0x56 /* Operating Channel 3 */ |
||
| 1015 | #define FS_PLLTUNE_CH4 FS_PLLTUNE_CH2 /* Operating Channel 4 (same as 2) */ |
||
| 1016 | #define FS_PLLTUNE_CH5 0xBE /* Operating Channel 5 */ |
||
| 1017 | #define FS_PLLTUNE_CH7 FS_PLLTUNE_CH5 /* Operating Channel 7 (same as 5) */ |
||
| 1018 | /* offset from FS_CTRL_ID in bytes */
|
||
| 1019 | #define FS_RES2_OFFSET 0x0C /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */ |
||
| 1020 | #define FS_RES2_LEN (2) |
||
| 1021 | /* offset from FS_CTRL_ID in bytes */
|
||
| 1022 | #define FS_XTALT_OFFSET 0x0E /* Frequency synthesiser Crystal trim */ |
||
| 1023 | #define FS_XTALT_LEN (1) |
||
| 1024 | #define FS_XTALT_MASK 0x1F /* Crystal Trim. Crystals may be trimmed using this register setting to tune out errors, see 8.1 IC Calibration Crystal Oscillator Trim. */ |
||
| 1025 | #define FS_XTALT_MIDRANGE 0x10 |
||
| 1026 | /* offset from FS_CTRL_ID in bytes */
|
||
| 1027 | #define FS_RES3_OFFSET 0x0F /* reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. */ |
||
| 1028 | #define FS_RES3_LEN (6) |
||
| 1029 | |||
| 1030 | /****************************************************************************//** |
||
| 1031 | * @brief Bit definitions for register
|
||
| 1032 | **/
|
||
| 1033 | #define AON_ID 0x2C /* Always-On register set */ |
||
| 1034 | #define AON_LEN (12) |
||
| 1035 | /* offset from AON_ID in bytes */
|
||
| 1036 | #define AON_WCFG_OFFSET 0x00 /* used to control what the DW1000 IC does as it wakes up from low-power SLEEP or DEEPSLEEPstates. */ |
||
| 1037 | #define AON_WCFG_LEN (2) |
||
| 1038 | #define AON_WCFG_MASK 0x09CB /* access mask to AON_WCFG register*/ |
||
| 1039 | #define AON_WCFG_ONW_RADC 0x0001 /* On Wake-up Run the (temperature and voltage) Analog-to-Digital Convertors */ |
||
| 1040 | #define AON_WCFG_ONW_RX 0x0002 /* On Wake-up turn on the Receiver */ |
||
| 1041 | #define AON_WCFG_ONW_LEUI 0x0008 /* On Wake-up load the EUI from OTP memory into Register file: 0x01 Extended Unique Identifier. */ |
||
| 1042 | #define AON_WCFG_ONW_LDC 0x0040 /* On Wake-up load configurations from the AON memory into the host interface register set */ |
||
| 1043 | #define AON_WCFG_ONW_L64P 0x0080 /* On Wake-up load the Length64 receiver operating parameter set */ |
||
| 1044 | #define AON_WCFG_PRES_SLEEP 0x0100 /* Preserve Sleep. This bit determines what the DW1000 does with respect to the ARXSLP and ATXSLP sleep controls */ |
||
| 1045 | #define AON_WCFG_ONW_LLDE 0x0800 /* On Wake-up load the LDE microcode. */ |
||
| 1046 | #define AON_WCFG_ONW_LLDO 0x1000 /* On Wake-up load the LDO tune value. */ |
||
| 1047 | /* offset from AON_ID in bytes */
|
||
| 1048 | #define AON_CTRL_OFFSET 0x02 /* The bits in this register in general cause direct activity within the AON block with respect to the stored AON memory */ |
||
| 1049 | #define AON_CTRL_LEN (1) |
||
| 1050 | #define AON_CTRL_MASK 0x8F /* access mask to AON_CTRL register */ |
||
| 1051 | #define AON_CTRL_RESTORE 0x01 /* When this bit is set the DW1000 will copy the user configurations from the AON memory to the host interface register set. */ |
||
| 1052 | #define AON_CTRL_SAVE 0x02 /* When this bit is set the DW1000 will copy the user configurations from the host interface register set into the AON memory */ |
||
| 1053 | #define AON_CTRL_UPL_CFG 0x04 /* Upload the AON block configurations to the AON */ |
||
| 1054 | #define AON_CTRL_DCA_READ 0x08 /* Direct AON memory access read */ |
||
| 1055 | #define AON_CTRL_DCA_ENAB 0x80 /* Direct AON memory access enable bit */ |
||
| 1056 | /* offset from AON_ID in bytes */
|
||
| 1057 | #define AON_RDAT_OFFSET 0x03 /* AON Direct Access Read Data Result */ |
||
| 1058 | #define AON_RDAT_LEN (1) |
||
| 1059 | /* offset from AON_ID in bytes */
|
||
| 1060 | #define AON_ADDR_OFFSET 0x04 /* AON Direct Access Address */ |
||
| 1061 | #define AON_ADDR_LEN (1) |
||
| 1062 | #define AON_ADDR_LPOSC_CAL_0 117 /* Address of low-power oscillator calibration value (lower byte) */ |
||
| 1063 | #define AON_ADDR_LPOSC_CAL_1 118 /* Address of low-power oscillator calibration value (lower byte) */ |
||
| 1064 | |||
| 1065 | /* offset from AON_ID in bytes */
|
||
| 1066 | #define AON_CFG0_OFFSET 0x06 /* 32-bit configuration register for the always on block. */ |
||
| 1067 | #define AON_CFG0_LEN (4) |
||
| 1068 | #define AON_CFG0_SLEEP_EN 0x00000001UL /* This is the sleep enable configuration bit */ |
||
| 1069 | #define AON_CFG0_WAKE_PIN 0x00000002UL /* Wake using WAKEUP pin */ |
||
| 1070 | #define AON_CFG0_WAKE_SPI 0x00000004UL /* Wake using SPI access SPICSn */ |
||
| 1071 | #define AON_CFG0_WAKE_CNT 0x00000008UL /* Wake when sleep counter elapses */ |
||
| 1072 | #define AON_CFG0_LPDIV_EN 0x00000010UL /* Low power divider enable configuration */ |
||
| 1073 | #define AON_CFG0_LPCLKDIVA_MASK 0x0000FFE0UL /* divider count for dividing the raw DW1000 XTAL oscillator frequency to set an LP clock frequency */ |
||
| 1074 | #define AON_CFG0_LPCLKDIVA_SHIFT (5) |
||
| 1075 | #define AON_CFG0_SLEEP_TIM 0xFFFF0000UL /* Sleep time. This field configures the sleep time count elapse value */ |
||
| 1076 | #define AON_CFG0_SLEEP_SHIFT (16) |
||
| 1077 | #define AON_CFG0_SLEEP_TIM_OFFSET 2 /* In bytes */ |
||
| 1078 | /* offset from AON_ID in bytes */
|
||
| 1079 | #define AON_CFG1_OFFSET 0x0A |
||
| 1080 | #define AON_CFG1_LEN (2) |
||
| 1081 | #define AON_CFG1_MASK 0x0007 /* aceess mask to AON_CFG1 */ |
||
| 1082 | #define AON_CFG1_SLEEP_CEN 0x0001 /* This bit enables the sleep counter */ |
||
| 1083 | #define AON_CFG1_SMXX 0x0002 /* This bit needs to be set to 0 for correct operation in the SLEEP state within the DW1000 */ |
||
| 1084 | #define AON_CFG1_LPOSC_CAL 0x0004 /* This bit enables the calibration function that measures the period of the IC\92s internal low powered oscillator */ |
||
| 1085 | |||
| 1086 | /****************************************************************************//** |
||
| 1087 | * @brief Bit definitions for register OTP_IF
|
||
| 1088 | * Refer to section 7.2.46 Register file: 0x2D OTP Memory Interface
|
||
| 1089 | **/
|
||
| 1090 | #define OTP_IF_ID 0x2D /* One Time Programmable Memory Interface */ |
||
| 1091 | #define OTP_IF_LEN (18) |
||
| 1092 | /* offset from OTP_IF_ID in bytes */
|
||
| 1093 | #define OTP_WDAT 0x00 /* 32-bit register. The data value to be programmed into an OTP location */ |
||
| 1094 | #define OTP_WDAT_LEN (4) |
||
| 1095 | /* offset from OTP_IF_ID in bytes */
|
||
| 1096 | #define OTP_ADDR 0x04 /* 16-bit register used to select the address within the OTP memory block */ |
||
| 1097 | #define OTP_ADDR_LEN (2) |
||
| 1098 | #define OTP_ADDR_MASK 0x07FF /* This 11-bit field specifies the address within OTP memory that will be accessed read or written. */ |
||
| 1099 | /* offset from OTP_IF_ID in bytes */
|
||
| 1100 | #define OTP_CTRL 0x06 /* used to control the operation of the OTP memory */ |
||
| 1101 | #define OTP_CTRL_LEN (2) |
||
| 1102 | #define OTP_CTRL_MASK 0x8002 |
||
| 1103 | #define OTP_CTRL_OTPRDEN 0x0001 /* This bit forces the OTP into manual read mode */ |
||
| 1104 | #define OTP_CTRL_OTPREAD 0x0002 /* This bit commands a read operation from the address specified in the OTP_ADDR register */ |
||
| 1105 | #define OTP_CTRL_LDELOAD 0x8000 /* This bit forces a load of LDE microcode */ |
||
| 1106 | #define OTP_CTRL_OTPPROG 0x0040 /* Setting this bit will cause the contents of OTP_WDAT to be written to OTP_ADDR. */ |
||
| 1107 | /* offset from OTP_IF_ID in bytes */
|
||
| 1108 | #define OTP_STAT 0x08 |
||
| 1109 | #define OTP_STAT_LEN (2) |
||
| 1110 | #define OTP_STAT_MASK 0x0003 |
||
| 1111 | #define OTP_STAT_OTPPRGD 0x0001 /* OTP Programming Done */ |
||
| 1112 | #define OTP_STAT_OTPVPOK 0x0002 /* OTP Programming Voltage OK */ |
||
| 1113 | /* offset from OTP_IF_ID in bytes */
|
||
| 1114 | #define OTP_RDAT 0x0A /* 32-bit register. The data value read from an OTP location will appear here */ |
||
| 1115 | #define OTP_RDAT_LEN (4) |
||
| 1116 | /* offset from OTP_IF_ID in bytes */
|
||
| 1117 | #define OTP_SRDAT 0x0E /* 32-bit register. The data value stored in the OTP SR (0x400) location will appear here after power up */ |
||
| 1118 | #define OTP_SRDAT_LEN (4) |
||
| 1119 | /* offset from OTP_IF_ID in bytes */
|
||
| 1120 | #define OTP_SF 0x12 /*8-bit special function register used to select and load special receiver operational parameter */ |
||
| 1121 | #define OTP_SF_LEN (1) |
||
| 1122 | #define OTP_SF_MASK 0x63 |
||
| 1123 | #define OTP_SF_OPS_KICK 0x01 /* This bit when set initiates a load of the operating parameter set selected by the OPS_SEL */ |
||
| 1124 | #define OTP_SF_LDO_KICK 0x02 /* This bit when set initiates a load of the LDO tune code */ |
||
| 1125 | #define OTP_SF_OPS_SEL_SHFT 5 |
||
| 1126 | #define OTP_SF_OPS_SEL_MASK 0x60 |
||
| 1127 | #define OTP_SF_OPS_SEL_L64 0x00 /* Operating parameter set selection: Length64 */ |
||
| 1128 | #define OTP_SF_OPS_SEL_TIGHT 0x40 /* Operating parameter set selection: Tight */ |
||
| 1129 | |||
| 1130 | /****************************************************************************//** |
||
| 1131 | * @brief Bit definitions for register LDE_IF
|
||
| 1132 | * Refer to section 7.2.47 Register file: 0x2E Leading Edge Detection Interface
|
||
| 1133 | * PLEASE NOTE: Other areas within the address space of Register file: 0x2E Leading Edge Detection Interface
|
||
| 1134 | * are reserved. To ensure proper operation of the LDE algorithm (i.e. to avoid loss of performance or a malfunction),
|
||
| 1135 | * care must be taken not to write to any byte locations other than those defined in the sub-sections below.
|
||
| 1136 | **/
|
||
| 1137 | #define LDE_IF_ID 0x2E /* Leading edge detection control block */ |
||
| 1138 | #define LDE_IF_LEN (0) |
||
| 1139 | /* offset from LDE_IF_ID in bytes */
|
||
| 1140 | #define LDE_THRESH_OFFSET 0x0000 /* 16-bit status register reporting the threshold that was used to find the first path */ |
||
| 1141 | #define LDE_THRESH_LEN (2) |
||
| 1142 | /* offset from LDE_IF_ID in bytes */
|
||
| 1143 | #define LDE_CFG1_OFFSET 0x0806 /*8-bit configuration register*/ |
||
| 1144 | #define LDE_CFG1_LEN (1) |
||
| 1145 | #define LDE_CFG1_NSTDEV_MASK 0x1F /* Number of Standard Deviations mask. */ |
||
| 1146 | #define LDE_CFG1_PMULT_MASK 0xE0 /* Peak Multiplier mask. */ |
||
| 1147 | /* offset from LDE_IF_ID in bytes */
|
||
| 1148 | #define LDE_PPINDX_OFFSET 0x1000 /* reporting the position within the accumulator that the LDE algorithm has determined to contain the maximum */ |
||
| 1149 | #define LDE_PPINDX_LEN (2) |
||
| 1150 | /* offset from LDE_IF_ID in bytes */
|
||
| 1151 | #define LDE_PPAMPL_OFFSET 0x1002 /* reporting the magnitude of the peak signal seen in the accumulator data memory */ |
||
| 1152 | #define LDE_PPAMPL_LEN (2) |
||
| 1153 | /* offset from LDE_IF_ID in bytes */
|
||
| 1154 | #define LDE_RXANTD_OFFSET 0x1804 /* 16-bit configuration register for setting the receive antenna delay */ |
||
| 1155 | #define LDE_RXANTD_LEN (2) |
||
| 1156 | /* offset from LDE_IF_ID in bytes */
|
||
| 1157 | #define LDE_CFG2_OFFSET 0x1806 /* 16-bit LDE configuration tuning register */ |
||
| 1158 | #define LDE_CFG2_LEN (2) |
||
| 1159 | /* offset from LDE_IF_ID in bytes */
|
||
| 1160 | #define LDE_REPC_OFFSET 0x2804 /* 16-bit configuration register for setting the replica avoidance coefficient */ |
||
| 1161 | #define LDE_REPC_LEN (2) |
||
| 1162 | #define LDE_REPC_PCODE_1 0x5998 |
||
| 1163 | #define LDE_REPC_PCODE_2 0x5998 |
||
| 1164 | #define LDE_REPC_PCODE_3 0x51EA |
||
| 1165 | #define LDE_REPC_PCODE_4 0x428E |
||
| 1166 | #define LDE_REPC_PCODE_5 0x451E |
||
| 1167 | #define LDE_REPC_PCODE_6 0x2E14 |
||
| 1168 | #define LDE_REPC_PCODE_7 0x8000 |
||
| 1169 | #define LDE_REPC_PCODE_8 0x51EA |
||
| 1170 | #define LDE_REPC_PCODE_9 0x28F4 |
||
| 1171 | #define LDE_REPC_PCODE_10 0x3332 |
||
| 1172 | #define LDE_REPC_PCODE_11 0x3AE0 |
||
| 1173 | #define LDE_REPC_PCODE_12 0x3D70 |
||
| 1174 | #define LDE_REPC_PCODE_13 0x3AE0 |
||
| 1175 | #define LDE_REPC_PCODE_14 0x35C2 |
||
| 1176 | #define LDE_REPC_PCODE_15 0x2B84 |
||
| 1177 | #define LDE_REPC_PCODE_16 0x35C2 |
||
| 1178 | #define LDE_REPC_PCODE_17 0x3332 |
||
| 1179 | #define LDE_REPC_PCODE_18 0x35C2 |
||
| 1180 | #define LDE_REPC_PCODE_19 0x35C2 |
||
| 1181 | #define LDE_REPC_PCODE_20 0x47AE |
||
| 1182 | #define LDE_REPC_PCODE_21 0x3AE0 |
||
| 1183 | #define LDE_REPC_PCODE_22 0x3850 |
||
| 1184 | #define LDE_REPC_PCODE_23 0x30A2 |
||
| 1185 | #define LDE_REPC_PCODE_24 0x3850 |
||
| 1186 | |||
| 1187 | /****************************************************************************//** |
||
| 1188 | * @brief Bit definitions for register DIG_DIAG
|
||
| 1189 | * Digital Diagnostics interface.
|
||
| 1190 | * It contains a number of sub-registers that give diagnostics information.
|
||
| 1191 | **/
|
||
| 1192 | #define DIG_DIAG_ID 0x2F /* Digital Diagnostics Interface */ |
||
| 1193 | #define DIG_DIAG_LEN (41) |
||
| 1194 | |||
| 1195 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1196 | #define EVC_CTRL_OFFSET 0x00 /* Event Counter Control */ |
||
| 1197 | #define EVC_CTRL_LEN (4) |
||
| 1198 | #define EVC_CTRL_MASK 0x00000003UL/* access mask to Register for bits should always be set to zero to avoid any malfunction of the device. */ |
||
| 1199 | #define EVC_EN 0x00000001UL/* Event Counters Enable bit */ |
||
| 1200 | #define EVC_CLR 0x00000002UL |
||
| 1201 | |||
| 1202 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1203 | #define EVC_PHE_OFFSET 0x04 /* PHR Error Event Counter */ |
||
| 1204 | #define EVC_PHE_LEN (2) |
||
| 1205 | #define EVC_PHE_MASK 0x0FFF |
||
| 1206 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1207 | #define EVC_RSE_OFFSET 0x06 /* Reed Solomon decoder (Frame Sync Loss) Error Event Counter */ |
||
| 1208 | #define EVC_RSE_LEN (2) |
||
| 1209 | #define EVC_RSE_MASK 0x0FFF |
||
| 1210 | |||
| 1211 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1212 | #define EVC_FCG_OFFSET 0x08 /* The EVC_FCG field is a 12-bit counter of the frames received with good CRC/FCS sequence. */ |
||
| 1213 | #define EVC_FCG_LEN (2) |
||
| 1214 | #define EVC_FCG_MASK 0x0FFF |
||
| 1215 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1216 | #define EVC_FCE_OFFSET 0x0A /* The EVC_FCE field is a 12-bit counter of the frames received with bad CRC/FCS sequence. */ |
||
| 1217 | #define EVC_FCE_LEN (2) |
||
| 1218 | #define EVC_FCE_MASK 0x0FFF |
||
| 1219 | |||
| 1220 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1221 | #define EVC_FFR_OFFSET 0x0C /* The EVC_FFR field is a 12-bit counter of the frames rejected by the receive frame filtering function. */ |
||
| 1222 | #define EVC_FFR_LEN (2) |
||
| 1223 | #define EVC_FFR_MASK 0x0FFF |
||
| 1224 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1225 | #define EVC_OVR_OFFSET 0x0E /* The EVC_OVR field is a 12-bit counter of receive overrun events */ |
||
| 1226 | #define EVC_OVR_LEN (2) |
||
| 1227 | #define EVC_OVR_MASK 0x0FFF |
||
| 1228 | |||
| 1229 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1230 | #define EVC_STO_OFFSET 0x10 /* The EVC_STO field is a 12-bit counter of SFD Timeout Error events */ |
||
| 1231 | #define EVC_OVR_LEN (2) |
||
| 1232 | #define EVC_OVR_MASK 0x0FFF |
||
| 1233 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1234 | #define EVC_PTO_OFFSET 0x12 /* The EVC_PTO field is a 12-bit counter of Preamble detection Timeout events */ |
||
| 1235 | #define EVC_PTO_LEN (2) |
||
| 1236 | #define EVC_PTO_MASK 0x0FFF |
||
| 1237 | |||
| 1238 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1239 | #define EVC_FWTO_OFFSET 0x14 /* The EVC_FWTO field is a 12-bit counter of receive frame wait timeout events */ |
||
| 1240 | #define EVC_FWTO_LEN (2) |
||
| 1241 | #define EVC_FWTO_MASK 0x0FFF |
||
| 1242 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1243 | #define EVC_TXFS_OFFSET 0x16 /* The EVC_TXFS field is a 12-bit counter of transmit frames sent. This is incremented every time a frame is sent */ |
||
| 1244 | #define EVC_TXFS_LEN (2) |
||
| 1245 | #define EVC_TXFS_MASK 0x0FFF |
||
| 1246 | |||
| 1247 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1248 | #define EVC_HPW_OFFSET 0x18 /* The EVC_HPW field is a 12-bit counter of Half Period Warnings\94. */ |
||
| 1249 | #define EVC_HPW_LEN (2) |
||
| 1250 | #define EVC_HPW_MASK 0x0FFF |
||
| 1251 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1252 | #define EVC_TPW_OFFSET 0x1A /* The EVC_TPW field is a 12-bit counter of Transmitter Power-Up Warnings\94. */ |
||
| 1253 | #define EVC_TPW_LEN (2) |
||
| 1254 | #define EVC_TPW_MASK 0x0FFF |
||
| 1255 | |||
| 1256 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1257 | #define EVC_RES1_OFFSET 0x1C /* Please take care not to write to this register as doing so may cause the DW1000 to malfunction. */ |
||
| 1258 | |||
| 1259 | /* offset from DIG_DIAG_ID in bytes */
|
||
| 1260 | #define DIAG_TMC_OFFSET 0x24 |
||
| 1261 | #define DIAG_TMC_LEN (2) |
||
| 1262 | #define DIAG_TMC_MASK 0x0010 |
||
| 1263 | #define DIAG_TMC_TX_PSTM 0x0010 /* This test mode is provided to help support regulatory approvals spectral testing. When the TX_PSTM bit is set it enables a repeating transmission of the data from the TX_BUFFER */ |
||
| 1264 | |||
| 1265 | |||
| 1266 | /****************************************************************************//** |
||
| 1267 | * @brief Bit definitions for register 0x30-0x35
|
||
| 1268 | * Please take care not to write to these registers as doing so may cause the DW1000 to malfunction.
|
||
| 1269 | **/
|
||
| 1270 | #define REG_30_ID_RESERVED 0x30 |
||
| 1271 | #define REG_31_ID_RESERVED 0x31 |
||
| 1272 | #define REG_32_ID_RESERVED 0x32 |
||
| 1273 | #define REG_33_ID_RESERVED 0x33 |
||
| 1274 | #define REG_34_ID_RESERVED 0x34 |
||
| 1275 | #define REG_35_ID_RESERVED 0x35 |
||
| 1276 | |||
| 1277 | /****************************************************************************//** |
||
| 1278 | * @brief Bit definitions for register PMSC
|
||
| 1279 | **/
|
||
| 1280 | #define PMSC_ID 0x36 /* Power Management System Control Block */ |
||
| 1281 | #define PMSC_LEN (48) |
||
| 1282 | /* offset from PMSC_ID in bytes */
|
||
| 1283 | #define PMSC_CTRL0_OFFSET 0x00 |
||
| 1284 | #define PMSC_CTRL0_LEN (4) |
||
| 1285 | #define PMSC_CTRL0_MASK 0xF18F847FUL /* access mask to register PMSC_CTRL0 */ |
||
| 1286 | #define PMSC_CTRL0_SYSCLKS_AUTO 0x00000000UL /* The system clock will run off the 19.2 MHz XTI clock until the PLL is calibrated and locked, then it will switch over the 125 MHz PLL clock */ |
||
| 1287 | #define PMSC_CTRL0_SYSCLKS_19M 0x00000001UL /* Force system clock to be the 19.2 MHz XTI clock. */ |
||
| 1288 | #define PMSC_CTRL0_SYSCLKS_125M 0x00000002UL /* Force system clock to the 125 MHz PLL clock. */ |
||
| 1289 | #define PMSC_CTRL0_RXCLKS_AUTO 0x00000000UL /* The RX clock will be disabled until it is required for an RX operation */ |
||
| 1290 | #define PMSC_CTRL0_RXCLKS_19M 0x00000004UL /* Force RX clock enable and sourced clock from the 19.2 MHz XTI clock */ |
||
| 1291 | #define PMSC_CTRL0_RXCLKS_125M 0x00000008UL /* Force RX clock enable and sourced from the 125 MHz PLL clock */ |
||
| 1292 | #define PMSC_CTRL0_RXCLKS_OFF 0x0000000CUL /* Force RX clock off. */ |
||
| 1293 | #define PMSC_CTRL0_TXCLKS_AUTO 0x00000000UL /* The TX clock will be disabled until it is required for a TX operation */ |
||
| 1294 | #define PMSC_CTRL0_TXCLKS_19M 0x00000010UL /* Force TX clock enable and sourced clock from the 19.2 MHz XTI clock */ |
||
| 1295 | #define PMSC_CTRL0_TXCLKS_125M 0x00000020UL /* Force TX clock enable and sourced from the 125 MHz PLL clock */ |
||
| 1296 | #define PMSC_CTRL0_TXCLKS_OFF 0x00000030UL /* Force TX clock off */ |
||
| 1297 | #define PMSC_CTRL0_FACE 0x00000040UL /* Force Accumulator Clock Enable */ |
||
| 1298 | #define PMSC_CTRL0_GPDCE 0x00040000UL /* GPIO De-bounce Clock Enable */ |
||
| 1299 | #define PMSC_CTRL0_KHZCLEN 0x00800000UL /* Kilohertz Clock Enable */ |
||
| 1300 | #define PMSC_CTRL0_PLL2_SEQ_EN 0x01000000UL /* Enable PLL2 on/off sequencing by SNIFF mode */ |
||
| 1301 | #define PMSC_CTRL0_SOFTRESET_OFFSET 3 /* In bytes */ |
||
| 1302 | #define PMSC_CTRL0_RESET_ALL 0x00 /* Assuming only 4th byte of the register is read */ |
||
| 1303 | #define PMSC_CTRL0_RESET_RX 0xE0 /* Assuming only 4th byte of the register is read */ |
||
| 1304 | #define PMSC_CTRL0_RESET_CLEAR 0xF0 /* Assuming only 4th byte of the register is read */ |
||
| 1305 | /* offset from PMSC_ID in bytes */
|
||
| 1306 | #define PMSC_CTRL1_OFFSET 0x04 |
||
| 1307 | #define PMSC_CTRL1_LEN (4) |
||
| 1308 | #define PMSC_CTRL1_MASK 0xFC02F802UL /* access mask to register PMSC_CTRL1 */ |
||
| 1309 | #define PMSC_CTRL1_ARX2INIT 0x00000002UL /* Automatic transition from receive mode into the INIT state */ |
||
| 1310 | #define PMSC_CTRL1_ATXSLP 0x00000800UL /* If this bit is set then the DW1000 will automatically transition into SLEEP or DEEPSLEEP mode after transmission of a frame */ |
||
| 1311 | #define PMSC_CTRL1_ARXSLP 0x00001000UL /* this bit is set then the DW1000 will automatically transition into SLEEP mode after a receive attempt */ |
||
| 1312 | #define PMSC_CTRL1_SNOZE 0x00002000UL /* Snooze Enable */ |
||
| 1313 | #define PMSC_CTRL1_SNOZR 0x00004000UL /* The SNOZR bit is set to allow the snooze timer to repeat twice */ |
||
| 1314 | #define PMSC_CTRL1_PLLSYN 0x00008000UL /* This enables a special 1 GHz clock used for some external SYNC modes */ |
||
| 1315 | #define PMSC_CTRL1_LDERUNE 0x00020000UL /* This bit enables the running of the LDE algorithm */ |
||
| 1316 | #define PMSC_CTRL1_KHZCLKDIV_MASK 0xFC000000UL /* Kilohertz clock divisor */ |
||
| 1317 | #define PMSC_CTRL1_PKTSEQ_DISABLE 0x00 /* writing this to PMSC CONTROL 1 register (bits 10-3) disables PMSC control of analog RF subsystems */ |
||
| 1318 | #define PMSC_CTRL1_PKTSEQ_ENABLE 0xE7 /* writing this to PMSC CONTROL 1 register (bits 10-3) enables PMSC control of analog RF subsystems */ |
||
| 1319 | /* offset from PMSC_ID in bytes */
|
||
| 1320 | #define PMSC_RES1_OFFSET 0x08 |
||
| 1321 | /* offset from PMSC_ID in bytes */
|
||
| 1322 | #define PMSC_SNOZT_OFFSET 0x0C /* PMSC Snooze Time Register */ |
||
| 1323 | #define PMSC_SNOZT_LEN (1) |
||
| 1324 | /* offset from PMSC_ID in bytes */
|
||
| 1325 | #define PMSC_RES2_OFFSET 0x10 |
||
| 1326 | /* offset from PMSC_ID in bytes */
|
||
| 1327 | #define PMSC_RES3_OFFSET 0x24 |
||
| 1328 | /* offset from PMSC_ID in bytes */
|
||
| 1329 | #define PMSC_TXFINESEQ_OFFSET 0x26 |
||
| 1330 | #define PMSC_TXFINESEQ_DISABLE 0x0 /* Writing this disables fine grain sequencing in the transmitter */ |
||
| 1331 | #define PMSC_TXFINESEQ_ENABLE 0x0B74 /* Writing this enables fine grain sequencing in the transmitter */ |
||
| 1332 | /* offset from PMSC_ID in bytes */
|
||
| 1333 | #define PMSC_LEDC_OFFSET 0x28 |
||
| 1334 | #define PMSC_LEDC_LEN (4) |
||
| 1335 | #define PMSC_LEDC_MASK 0x000001FFUL /* 32-bit LED control register. */ |
||
| 1336 | #define PMSC_LEDC_BLINK_TIM_MASK 0x000000FFUL /* This field determines how long the LEDs remain lit after an event that causes them to be set on. */ |
||
| 1337 | #define PMSC_LEDC_BLNKEN 0x00000100UL /* Blink Enable. When this bit is set to 1 the LED blink feature is enabled. */ |
||
| 1338 | /* Default blink time. Blink time is expressed in multiples of 14 ms. The value defined here is ~225 ms. */
|
||
| 1339 | #define PMSC_LEDC_BLINK_TIME_DEF 0x10 |
||
| 1340 | /* Command a blink of all LEDs */
|
||
| 1341 | #define PMSC_LEDC_BLINK_NOW_ALL 0x000F0000UL |
||
| 1342 | |||
| 1343 | /****************************************************************************//** |
||
| 1344 | * @brief Bit definitions for register 0x37-0x3F
|
||
| 1345 | * Please take care not to write to these registers as doing so may cause the DW1000 to malfunction.
|
||
| 1346 | **/
|
||
| 1347 | #define REG_37_ID_RESERVED 0x37 |
||
| 1348 | #define REG_38_ID_RESERVED 0x38 |
||
| 1349 | #define REG_39_ID_RESERVED 0x39 |
||
| 1350 | #define REG_3A_ID_RESERVED 0x3A |
||
| 1351 | #define REG_3B_ID_RESERVED 0x3B |
||
| 1352 | #define REG_3C_ID_RESERVED 0x3C |
||
| 1353 | #define REG_3D_ID_RESERVED 0x3D |
||
| 1354 | #define REG_3E_ID_RESERVED 0x3E |
||
| 1355 | #define REG_3F_ID_RESERVED 0x3F |
||
| 1356 | |||
| 1357 | /* END DW1000 REGISTER DEFINITION */
|
||
| 1358 | |||
| 1359 | #ifdef __cplusplus
|
||
| 1360 | } |
||
| 1361 | #endif
|
||
| 1362 | |||
| 1363 | #endif /* defined(AMIROLLD_CFG_USE_DW1000) */ |
||
| 1364 | #endif
|