/ - Diff - AMiRo-OS - Research for Cognitive Interaction

Revision 1d5bcc82

     AMIROLLD_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
     # include paths
     AMIROLLD_INC = $(AMIROLLD_DIR:/=) \
                    $(AMIROLLD_DIR)include
     AMIROLLD_SRCDIR = $(AMIROLLD_DIR)source
     AMIROLLD_INC = $(AMIROLLD_DIR) \
                    $(sort $(dir $(wildcard $(AMIROLLD_DIR)include/?*/)))
     # C sources
     AMIROLLD_CSRC = $(wildcard $(AMIROLLD_SRCDIR)/*.c)
     AMIROLLD_CSRC = $(wildcard $(AMIROLLD_DIR)source/*/*/*.c)

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_A3906.h
+     *
      * @addtogroup lld_motor
      * @{
      */
     #ifndef AMIROLLD_A3906_H
     #define AMIROLLD_A3906_H
     #include <amiro-lld.h>
     #if defined(AMIROLLD_CFG_A3906)
     #if (AMIROLLD_CFG_A3906 == 1)
       #include "v1/alld_A3906_v1.h"
     #else
       #error "invalid value assigned to AMIROLLD_CFG_A3906 in alldconf.h"
     #endif
     #endif /* defined(AMIROLLD_CFG_A3906) */
     #endif /* AMIROLLD_A3906_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_A3906_v1.h
      * @brief   Motor driver macros and structures.
+     *
      * @addtogroup lld_motor
      * @{
      */
     #ifndef AMIROLLD_A3906_V1_H
     #define AMIROLLD_A3906_V1_H
     #include <amiro-lld.h>
     #if (defined(AMIROLLD_CFG_A3906) && (AMIROLLD_CFG_A3906 == 1)) || defined(__DOXYGEN__)
     /******************************************************************************/
     /* CONSTANTS                                                                  */
     /******************************************************************************/
     /**
      * @brief Active state of power pin.
      */
     #define A3906_LLD_POWER_PIN_ACTIVE_STATE  APAL_GPIO_ACTIVE_HIGH
     /******************************************************************************/
     /* SETTINGS                                                                   */
     /******************************************************************************/
     /******************************************************************************/
     /* CHECKS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* DATA STRUCTURES AND TYPES                                                  */
     /******************************************************************************/
     /**
      * @brief A3906 driver struct.
      */
     typedef struct {
       const apalControlGpio_t* power_pin;   /**< @brief GPIO to enable/disable power of the A3906. */
     } A3906Driver;
     /**
      * @brief Power state of the A3906.
      */
     typedef enum {
       A3906_LLD_POWER_OFF = 0x00,   /**< 'power off' state  */
       A3906_LLD_POWER_ON  = 0x01,   /**< 'power on' state   */
     } a3906_lld_power_t;
     /******************************************************************************/
     /* MACROS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* EXTERN DECLARATIONS                                                        */
     /******************************************************************************/
     #ifdef __cplusplus
     extern "C" {
     #endif
       apalExitStatus_t a3906_lld_set_power(const A3906Driver* const a3906, const a3906_lld_power_t power_state);
       apalExitStatus_t a3906_lld_get_power(const A3906Driver* const a3906, a3906_lld_power_t* const power_state);
       apalExitStatus_t a3906_lld_set_pwm(apalPWMDriver_t* pwm, const apalPWMchannel_t channel, const apalPWMwidth_t width);
     #ifdef __cplusplus
+    }
     #endif
     /******************************************************************************/
     /* INLINE FUNCTIONS                                                           */
     /******************************************************************************/
     #endif /* defined(AMIROLLD_CFG_USE_A3906) && (AMIROLLD_CFG_USE_A3906 == 1) */
     #endif /* AMIROLLD_A3906_V1_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_AT24C01B.h
+     *
      * @addtogroup lld_eeprom
      * @{
      */
     #ifndef AMIROLLD_AT24C01B_H
     #define AMIROLLD_AT24C01B_H
     #include <amiro-lld.h>
     #if defined(AMIROLLD_CFG_AT24C01B)
     #if (AMIROLLD_CFG_AT24C01B == 1)
       #include "v1/alld_AT24C01B_v1.h"
     #else
       #error "invalid value assigned to AMIROLLD_CFG_AT24C01B in alldconf.h"
     #endif
     #endif /* defined(AMIROLLD_CFG_AT24C01B) */
     #endif /* AMIROLLD_AT24C01B_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_AT24C01B_v1.h
      * @brief   EEPROM macros and structures.
+     *
      * @addtogroup lld_eeprom
      * @{
      */
     #ifndef AMIROLLD_AT24C01B_V1_H
     #define AMIROLLD_AT24C01B_V1_H
     #include <amiro-lld.h>
     #if (defined(AMIROLLD_CFG_AT24C01B) && (AMIROLLD_CFG_AT24C01B == 1)) || defined(__DOXYGEN__)
     /******************************************************************************/
     /* CONSTANTS                                                                  */
     /******************************************************************************/
     /**
      * @brief Memory size of the EEPROM in bits.
      */
     #define AT24C01B_LLD_SIZE_BITS              1024
     /**
      * @brief Memory size of the EEPROM in bytes
      */
     #define AT24C01B_LLD_SIZE_BYTES             128
     /**
      * @brief Size of a page in bytes
      */
     #define AT24C01B_LLD_PAGE_SIZE_BYTES        8
     /**
      * @brief  Time in microseconds a write operation takes to complete (I2C will not respond).
      * @note   The system should wait slightly longer.
      */
     #define AT24C01B_LLD_WRITECYCLETIME_US      5000
     /**
      * @brief Maximum I2C frequency.
      */
     #define AT24C01B_LLD_I2C_MAXFREQUENCY       400000
     /**
      * @brief Maximum I2C frequency at 5V.
      */
     #define AT24C01B_LLD_I2C_MAXFREQUENCY_5V    1000000
     /******************************************************************************/
     /* SETTINGS                                                                   */
     /******************************************************************************/
     /******************************************************************************/
     /* CHECKS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* DATA STRUCTURES AND TYPES                                                  */
     /******************************************************************************/
     /**
      * @brief The AT24C01B driver struct
      */
     typedef struct {
       apalI2CDriver_t* i2cd;  /**< @brief The I2C Driver */
       apalI2Caddr_t addr;     /**< @brief The address of the AT24C01B for I2C communication, which is defined by the wiring of the A0, A1, A2 pins */
     } AT24C01BDriver;
     /**
      * @brief Bitmasks for the I2C address, including the wiring of the A0, A1, A2 pins.
      */
     enum {
       AT24C01B_LLD_I2C_ADDR_FIXED       = 0x0050u,
       AT24C01B_LLD_I2C_ADDR_A0          = 0x0001u,
       AT24C01B_LLD_I2C_ADDR_A1          = 0x0002u,
       AT24C01B_LLD_I2C_ADDR_A2          = 0x0004u,
     };
     /******************************************************************************/
     /* MACROS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* EXTERN DECLARATIONS                                                        */
     /******************************************************************************/
     #ifdef __cplusplus
     extern "C" {
     #endif
       apalExitStatus_t at24c01b_lld_poll_ack(const AT24C01BDriver* const at24c01b, const apalTime_t timeout);
       apalExitStatus_t at24c01b_lld_read_current_address(const AT24C01BDriver* const at24c01b, uint8_t* const data, const uint8_t num, const apalTime_t timeout);
       apalExitStatus_t at24c01b_lld_read(const AT24C01BDriver* const at24c01b, const uint8_t addr, uint8_t* const data, const uint8_t num, const apalTime_t timeout);
       apalExitStatus_t at24c01b_lld_write_byte(const AT24C01BDriver* const at24c01b, const uint8_t addr, const uint8_t data, const apalTime_t timeout);
       apalExitStatus_t at24c01b_lld_write_page(const AT24C01BDriver* const at24c01b, const uint8_t addr, const uint8_t* const data, const uint8_t num, const apalTime_t timeout);
     #ifdef __cplusplus
+    }
     #endif
     /******************************************************************************/
     /* INLINE FUNCTIONS                                                           */
     /******************************************************************************/
     #endif /* defined(AMIROLLD_CFG_AT24C01B) && (AMIROLLD_CFG_AT24C01B == 1) */
     #endif /* AMIROLLD_AT24C01BN_V1_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_AT42QT1050.h
+     *
      * @addtogroup lld_touch
      * @{
      */
     #ifndef AMIROLLD_AT42QT1050_H
     #define AMIROLLD_AT42QT1050_H
     #include <amiro-lld.h>
     #if defined(AMIROLLD_CFG_AT42QT1050)
     #if (AMIROLLD_CFG_AT42QT1050 == 1)
       #include "v1/alld_AT42QT1050_v1.h"
     #else
       #error "invalid value assigned to AMIROLLD_CFG_AT42QT1050 in alldconf.h"
     #endif
     #endif /* defined(AMIROLLD_CFG_AT42QT1050) */
     #endif /* AMIROLLD_AT42QT1050_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_AT42QT1050_v1.h
      * @brief   Touch sensor macros and structures.
+     *
      * @addtogroup lld_touch
      * @{
      */
     #ifndef AMIROLLD_AT42QT1050_V1_H
     #define AMIROLLD_AT42QT1050_V1_H
     #include <amiro-lld.h>
     #if (defined(AMIROLLD_CFG_AT42QT1050) && (AMIROLLD_CFG_AT42QT1050 == 1)) || defined(__DOXYGEN__)
     /******************************************************************************/
     /* CONSTANTS                                                                  */
     /******************************************************************************/
     /**
      * @brief   Maximum I2C frequency.
      */
     #define AT42QT1050_LLD_I2C_MAXFREQUENCY         400000
     /**
      * @brief   A falling edge indicats an interrupt.
      */
     #define AT42QT1050_LLD_INT_EDGE                 APAL_GPIO_EDGE_FALLING
     /**
      * @brief   Number of touch keys supported by AT42QT1050.
      */
     #define AT42QT1050_LLD_NUM_KEYS                 5
     /**
      * @brief   Maximum time (in microseconds) to acquire all key signals before the overflow bit of the detection status register is set.
      */
     #define AT42QT1050_LLD_MAX_KEY_ACQUIRATION_TIME 8000
     /**
      * @brief   The chip ID as can be read from the according register (constant).
      */
     #define AT42QT1050_LLD_CHIPID                   0x46
     /******************************************************************************/
     /* SETTINGS                                                                   */
     /******************************************************************************/
     /******************************************************************************/
     /* CHECKS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* DATA STRUCTURES AND TYPES                                                  */
     /******************************************************************************/
     /**
      * @brief   The AT42QT1050Driver sruct.
      */
     typedef struct {
       apalI2CDriver_t* i2cd;
       apalI2Caddr_t addr;
     } AT42QT1050Driver;
     /**
      * @brief   Possible I2C address configurations.
      */
     enum {
       AT42QT1050_LLD_I2C_ADDRSEL_LOW  = 0x0041u,  /**< ADDR_SEL pin is pulled low. */
       AT42QT1050_LLD_I2C_ADDRSEL_HIGH = 0x0046u,  /**< ADDR_SEL pin is pulled high. */
     };
     /**
      * @brief   Available register addresses of the AT42Q1050.
      */
     typedef enum {
       AT42QT1050_LLD_REG_CHIPID               = 0x00u,  /**<  read only */
       AT42QT1050_LLD_REG_FIRMWAREVERSION      = 0x01u,  /**<  read only */
       AT42QT1050_LLD_REG_DETECTIONSTATUS      = 0x02u,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSTATUS            = 0x03u,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSIGNAL_0          = 0x06u,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSIGNAL_1          = 0x08u,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSIGNAL_2          = 0x0Du,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSIGNAL_3          = 0x0Fu,  /**<  read only */
       AT42QT1050_LLD_REG_KEYSIGNAL_4          = 0x11u,  /**<  read only */
       AT42QT1050_LLD_REG_REFERENCEDATA_0      = 0x14u,  /**<  read only */
       AT42QT1050_LLD_REG_REFERENCEDATA_1      = 0x16u,  /**<  read only */
       AT42QT1050_LLD_REG_REFERENCEDATA_2      = 0x1Au,  /**<  read only */
       AT42QT1050_LLD_REG_REFERENCEDATA_3      = 0x1Cu,  /**<  read only */
       AT42QT1050_LLD_REG_REFERENCEDATA_4      = 0x1Eu,  /**<  read only */
       AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_0  = 0x21u,  /**< read/write */
       AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_1  = 0x22u,  /**< read/write */
       AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_2  = 0x24u,  /**< read/write */
       AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_3  = 0x25u,  /**< read/write */
       AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_4  = 0x26u,  /**< read/write */
       AT42QT1050_LLD_REG_PULSE_SCALE_0        = 0x28u,  /**< read/write */
       AT42QT1050_LLD_REG_PULSE_SCALE_1        = 0x29u,  /**< read/write */
       AT42QT1050_LLD_REG_PULSE_SCALE_2        = 0x2Bu,  /**< read/write */
       AT42QT1050_LLD_REG_PULSE_SCALE_3        = 0x2Cu,  /**< read/write */
       AT42QT1050_LLD_REG_PULSE_SCALE_4        = 0x2Du,  /**< read/write */
       AT42QT1050_LLD_REG_INTEGRATOR_AKS_0     = 0x2Fu,  /**< read/write */
       AT42QT1050_LLD_REG_INTEGRATOR_AKS_1     = 0x30u,  /**< read/write */
       AT42QT1050_LLD_REG_INTEGRATOR_AKS_2     = 0x32u,  /**< read/write */
       AT42QT1050_LLD_REG_INTEGRATOR_AKS_3     = 0x33u,  /**< read/write */
       AT42QT1050_LLD_REG_INTEGRATOR_AKS_4     = 0x34u,  /**< read/write */
       AT42QT1050_LLD_REG_CHARGESHAREDELAY_0   = 0x36u,  /**< read/write */
       AT42QT1050_LLD_REG_CHARGESHAREDELAY_1   = 0x37u,  /**< read/write */
       AT42QT1050_LLD_REG_CHARGESHAREDELAY_2   = 0x39u,  /**< read/write */
       AT42QT1050_LLD_REG_CHARGESHAREDELAY_3   = 0x3Au,  /**< read/write */
       AT42QT1050_LLD_REG_CHARGESHAREDELAY_4   = 0x3Bu,  /**< read/write */
       AT42QT1050_LLD_REG_FINFOUTMAXCALGUARD   = 0x3Cu,  /**< read/write */
       AT42QT1050_LLD_REG_LOWPOWERMODE         = 0x3Du,  /**< read/write */
       AT42QT1050_LLD_REG_MAXONDURATION        = 0x3Eu,  /**< read/write */
       AT42QT1050_LLD_REG_RESET_CALIBRATE      = 0x3Fu,  /**< read/write */
     } at42qt1050_lld_register_t;
     /**
      * @brief   Firmware version register structure.
      */
     typedef union {
       uint8_t raw;
       struct {
         uint8_t minor : 4;
         uint8_t major : 4;
       };
     } at42qt1050_lld_firmwarereg_t;
     /**
      * @brief   Relevant bits of the detection status register.
      */
     typedef enum {
       AT42QT1050_LLD_DETECTIONSTATUS_TOUCH      = 0x01u,  /**< Set if any keys are in detect.  */
       AT42QT1050_LLD_DETECTIONSTATUS_OVERFLOW   = 0x40u,  /**< Set if the time to acquire all key signals exceeds 8ms. */
       AT42QT1050_LLD_DETECTIONSTATUS_CALIBRATE  = 0x80u,  /**< Set during calibration sequence. */
     } at42q1050_lld_detectionstatusreg_t;
     /**
      * @brief   Key status register masks.
      */
     typedef enum {
       AT42QT1050_LLD_KEYSTATUS_KEY0 = 0x02u,
       AT42QT1050_LLD_KEYSTATUS_KEY1 = 0x04u,
       AT42QT1050_LLD_KEYSTATUS_KEY2 = 0x10u,
       AT42QT1050_LLD_KEYSTATUS_KEY3 = 0x20u,
       AT42QT1050_LLD_KEYSTATUS_KEY4 = 0x40u,
     } at42qt1050_lld_keystatusreg_t;
     /**
      * @brief   Pulse/Scale register structure.
      */
     typedef union {
       uint8_t raw;
       struct {
         uint8_t scale : 4;
         uint8_t pulse : 4;
       };
     } at42qt1050_lld_pulsescalereg_t;
     /**
      * @brief   Detection Integrator (DI) / AKS register structure.
      */
     typedef union {
       uint8_t raw;
       struct {
         uint8_t aks : 2;
         uint8_t detection_integrator : 6;
       };
     } at42qt1050_lld_detectionintegratoraksreg_t;
     /**
      * @brief   Charge share delay constant sclaing factor.
      * @details Values in the charge share delay registers are multiplied by this factor.
      *          Unit is microseconds (µs).
      */
     #define AT42QT1050_LLD_CHARGESHAREDELAY_FACTOR  2.5f
     /**
      * @brief   FastIn / FastOutDI / Max Cal / Guard Channel register masks.
      */
     typedef enum {
       AT42QT1050_LLD_FINFOUTMAXCALGUARD_GUARD   = 0x0Fu,
       AT42QT1050_LLD_FINFOUTMAXCALGUARD_MAXCAL  = 0x10u,
       AT42QT1050_LLD_FINFOUTMAXCALGUARD_FO      = 0x20u,
       AT42QT1050_LLD_FINFOUTMAXCALGUARD_FI      = 0x40u,
     } at42qt1050_lld_finfoutmaxcalguardreg_t;
     /**
      * @brief   Low power mode constant scaling factor.
      * @details The values in the low poer mode register is multiplied by this factor.
      *          Unit is microseconds (µs).
      * @note    Setting the power mode scaling register value to zero makes the AT42QT1050 enter deep-sleep mode.
      */
     #define AT42QT1050_LLD_LOWPOWER_FACTOR          8000
     /**
      * @brief   Man on duration constant scaling factor.
      * @details The value in the max on duration register is multiplied by this factor.
      *          Unit is microseconds (µs).
      */
     #define AT42QT1050_LLD_MAXONDURATION_FACTOR     160000
     /**
      * @brief   RESET / Calibrate register masks.
      */
     typedef enum {
       AT42QT1050_LLD_RESETCALIBRATE_CALIBRATE = 0x7Fu,
       AT42QT1050_LLD_RESETCALIBRATE_RESET     = 0x80u,
     } at42qt1050_lld_resetcalibratereg_t;
     /******************************************************************************/
     /* MACROS                                                                     */
     /******************************************************************************/
     /******************************************************************************/
     /* EXTERN DECLARATIONS                                                        */
     /******************************************************************************/
     #ifdef __cplusplus
     extern "C" {
     #endif
       apalExitStatus_t at42qt1050_lld_read_reg(const AT42QT1050Driver* at42qt1050d, const at42qt1050_lld_register_t reg, uint8_t* const data, const apalTime_t timeout);
       apalExitStatus_t at42qt1050_lld_write_reg(const AT42QT1050Driver* at42qt1050d, const at42qt1050_lld_register_t reg, const uint8_t data, const apalTime_t timeout);
       apalExitStatus_t at42qt1050_lld_read_keyssignal(const AT42QT1050Driver* at42qt1050d, const uint8_t key, uint16_t* signal, const apalTime_t timeout);
       apalExitStatus_t at42qt1050_lld_read_referencedata(const AT42QT1050Driver* at42qt1050d, const uint8_t key, uint16_t* refdata, const apalTime_t timeout);
       uint16_t at42qt1050_lld_pulse2samples(const uint8_t pulse);
       float at42qt1050_lld_samples2pulse(const uint16_t samples);
       uint16_t at42qt1050_lld_scale2scaling(const uint8_t scale);
       float at42qt1050_lld_scaling2scale(const uint16_t factor);
     #ifdef __cplusplus
+    }
     #endif
     /******************************************************************************/
     /* INLINE FUNCTIONS                                                           */
     /******************************************************************************/
     #endif /* defined(AMIROLLD_CFG_AT42QT1050) && (AMIROLLD_CFG_AT42QT1050 == 1) */
     #endif /* AMIROLLD_AT42QT1050_V1_H */
     /** @} */

     /*
     AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
     Copyright (C) 2016..2019  Thomas Schöpping et al.
     This program is free software: you can redistribute it and/or modify
     it under the terms of the GNU Lesser General Public License as published by
     the Free Software Foundation, either version 3 of the License, or
     (at your option) any later version.
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU Lesser General Public License for more details.
     You should have received a copy of the GNU Lesser General Public License
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
     */
     /**
      * @file    alld_DW1000.h
+     *
      * @addtogroup lld_uwb
      * @{
      */
     #ifndef AMIROLLD_DW1000_H
     #define AMIROLLD_DW1000_H
     #include <amiro-lld.h>
     #if defined(AMIROLLD_CFG_DW1000)
     #error "DW1000 LLD implementation is not ready yet."
     #endif /* defined(AMIROLLD_CFG_DW1000) */
     #endif /* AMIROLLD_DW1000_H */
     /** @} */

     /*! ------------------------------------------------------------------------------------------------------------------
      * @file    deca_regs.h
      * @brief   DW1000 Register Definitions
      *          This file supports assembler and C development for DW1000 enabled devices
+     *
      * @attention
+     *
      * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
+     *
      * All rights reserved.
+     *
      */
     #ifndef _DECA_REGS_H_
     #define _DECA_REGS_H_
     #ifdef __cplusplus
     extern "C" {
     #endif
     #include <amiro-lld.h>
     #if defined(AMIROLLD_CFG_USE_DW1000) || defined(__DOXYGEN__)
     /****************************************************************************//**
      * @brief Bit definitions for register DEV_ID
     **/
     #define DEV_ID_ID               0x00            /* Device ID register, includes revision info (0xDECA0130) */
     #define DEV_ID_LEN              (4)
     /* mask and shift */
     #define DEV_ID_REV_MASK         0x0000000FUL    /* Revision */
     #define DEV_ID_VER_MASK         0x000000F0UL    /* Version */
     #define DEV_ID_MODEL_MASK       0x0000FF00UL    /* The MODEL identifies the device. The DW1000 is device type 0x01 */
     #define DEV_ID_RIDTAG_MASK      0xFFFF0000UL    /* Register Identification Tag 0XDECA */
     /****************************************************************************//**
      * @brief Bit definitions for register EUI_64
     **/
     #define EUI_64_ID               0x01            /* IEEE Extended Unique Identifier (63:0) */
     #define EUI_64_OFFSET           0x00
     #define EUI_64_LEN              (8)
     /****************************************************************************//**
      * @brief Bit definitions for register PANADR
     **/
     #define PANADR_ID               0x03            /* PAN ID (31:16) and Short Address (15:0) */
     #define PANADR_LEN              (4)
     /*mask and shift */
     #define PANADR_SHORT_ADDR_OFFSET 0              /* In bytes */
     #define PANADR_SHORT_ADDR_MASK  0x0000FFFFUL    /* Short Address */
     #define PANADR_PAN_ID_OFFSET     2              /* In bytes */
     #define PANADR_PAN_ID_MASK      0xFFFF00F0UL    /* PAN Identifier */
     /****************************************************************************//**
      * @brief Bit definitions for register 0x05
     **/
     #define REG_05_ID_RESERVED      0x05
     /****************************************************************************//**
      * @brief Bit definitions for register SYS_CFG
     **/
     #define SYS_CFG_ID              0x04            /* System Configuration (31:0) */
     #define SYS_CFG_LEN             (4)
     /*mask and shift */
     #define SYS_CFG_MASK            0xF047FFFFUL    /* access mask to SYS_CFG_ID */
     #define SYS_CFG_FF_ALL_EN       0x000001FEUL    /* Frame filtering options all frames allowed */
     /*offset 0 */
     #define SYS_CFG_FFE             0x00000001UL    /* Frame Filtering Enable. This bit enables the frame filtering functionality */
     #define SYS_CFG_FFBC            0x00000002UL    /* Frame Filtering Behave as a Co-ordinator */
     #define SYS_CFG_FFAB            0x00000004UL    /* Frame Filtering Allow Beacon frame reception */
     #define SYS_CFG_FFAD            0x00000008UL    /* Frame Filtering Allow Data frame reception */
     #define SYS_CFG_FFAA            0x00000010UL    /* Frame Filtering Allow Acknowledgment frame reception */
     #define SYS_CFG_FFAM            0x00000020UL    /* Frame Filtering Allow MAC command frame reception */
     #define SYS_CFG_FFAR            0x00000040UL    /* Frame Filtering Allow Reserved frame types */
     #define SYS_CFG_FFA4            0x00000080UL    /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */
     /*offset 8 */
     #define SYS_CFG_FFA5            0x00000100UL    /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */
     #define SYS_CFG_HIRQ_POL        0x00000200UL    /* Host interrupt polarity */
     #define SYS_CFG_SPI_EDGE        0x00000400UL    /* SPI data launch edge */
     #define SYS_CFG_DIS_FCE         0x00000800UL    /* Disable frame check error handling */
     #define SYS_CFG_DIS_DRXB        0x00001000UL    /* Disable Double RX Buffer */
     #define SYS_CFG_DIS_PHE         0x00002000UL    /* Disable receiver abort on PHR error */
     #define SYS_CFG_DIS_RSDE        0x00004000UL    /* Disable Receiver Abort on RSD error */
     #define SYS_CFG_FCS_INIT2F      0x00008000UL    /* initial seed value for the FCS generation and checking function */
     /*offset 16 */
     #define SYS_CFG_PHR_MODE_SHFT   16
     #define SYS_CFG_PHR_MODE_00     0x00000000UL    /* Standard Frame mode */
     #define SYS_CFG_PHR_MODE_11     0x00030000UL    /* Long Frames mode */
     #define SYS_CFG_DIS_STXP        0x00040000UL    /* Disable Smart TX Power control */
     #define SYS_CFG_RXM110K         0x00400000UL    /* Receiver Mode 110 kbps data rate */
     /*offset 24 */
     #define SYS_CFG_RXWTOE          0x10000000UL    /* Receive Wait Timeout Enable. */
     #define SYS_CFG_RXAUTR          0x20000000UL    /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */
     #define SYS_CFG_AUTOACK         0x40000000UL    /* Automatic Acknowledgement Enable */
     #define SYS_CFG_AACKPEND        0x80000000UL    /* Automatic Acknowledgement Pending bit control */
     /****************************************************************************//**
      * @brief Bit definitions for register SYS_TIME
     **/
     #define SYS_TIME_ID             0x06            /* System Time Counter (40-bit) */
     #define SYS_TIME_OFFSET         0x00
     #define SYS_TIME_LEN            (5)             /* Note 40 bit register */
     /****************************************************************************//**
      * @brief Bit definitions for register  0x07
     **/
     #define REG_07_ID_RESERVED      0x07
     /****************************************************************************//**
      * @brief Bit definitions for register TX_FCTRL
     **/
     #define TX_FCTRL_ID             0x08            /* Transmit Frame Control */
     #define TX_FCTRL_LEN            (5)             /* Note 40 bit register */
     /*masks (low 32 bit) */
     #define TX_FCTRL_TFLEN_MASK     0x0000007FUL    /* bit mask to access Transmit Frame Length */
     #define TX_FCTRL_TFLE_MASK      0x00000380UL    /* bit mask to access Transmit Frame Length Extension */
     #define TX_FCTRL_FLE_MASK       0x000003FFUL    /* bit mask to access Frame Length field */
     #define TX_FCTRL_TXBR_MASK      0x00006000UL    /* bit mask to access Transmit Bit Rate */
     #define TX_FCTRL_TXPRF_MASK     0x00030000UL    /* bit mask to access Transmit Pulse Repetition Frequency */
     #define TX_FCTRL_TXPSR_MASK     0x000C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
     #define TX_FCTRL_PE_MASK        0x00300000UL    /* bit mask to access Preamble Extension */
     #define TX_FCTRL_TXPSR_PE_MASK  0x003C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
     #define TX_FCTRL_SAFE_MASK_32   0xFFFFE3FFUL    /* FSCTRL has fields which should always be writen zero */
     /*offset 0 */
     /*offset 8 */
     #define TX_FCTRL_TXBR_110k      0x00000000UL    /* Transmit Bit Rate = 110k */
     #define TX_FCTRL_TXBR_850k      0x00002000UL    /* Transmit Bit Rate = 850k */
     #define TX_FCTRL_TXBR_6M        0x00004000UL    /* Transmit Bit Rate = 6.8M */
     #define TX_FCTRL_TXBR_SHFT      (13)            /* shift to access Data Rate field */
     #define TX_FCTRL_TR             0x00008000UL    /* Transmit Ranging enable */
     #define TX_FCTRL_TR_SHFT        (15)            /* shift to access Ranging bit */
     /*offset 16 */
     #define TX_FCTRL_TXPRF_SHFT     (16)            /* shift to access Pulse Repetition Frequency field */
     #define TX_FCTRL_TXPRF_4M       0x00000000UL    /* Transmit Pulse Repetition Frequency = 4 Mhz */
     #define TX_FCTRL_TXPRF_16M      0x00010000UL    /* Transmit Pulse Repetition Frequency = 16 Mhz */
     #define TX_FCTRL_TXPRF_64M      0x00020000UL    /* Transmit Pulse Repetition Frequency = 64 Mhz */
     #define TX_FCTRL_TXPSR_SHFT     (18)            /* shift to access Preamble Symbol Repetitions field */
     #define TX_FCTRL_PE_SHFT        (20)            /* shift to access Preamble length Extension to allow specification of non-standard values */
     #define TX_FCTRL_TXPSR_PE_16    0x00000000UL    /* bit mask to access Preamble Extension = 16 */
     #define TX_FCTRL_TXPSR_PE_64    0x00040000UL    /* bit mask to access Preamble Extension = 64 */
     #define TX_FCTRL_TXPSR_PE_128   0x00140000UL    /* bit mask to access Preamble Extension = 128 */
     #define TX_FCTRL_TXPSR_PE_256   0x00240000UL    /* bit mask to access Preamble Extension = 256 */
     #define TX_FCTRL_TXPSR_PE_512   0x00340000UL    /* bit mask to access Preamble Extension = 512 */
     #define TX_FCTRL_TXPSR_PE_1024  0x00080000UL    /* bit mask to access Preamble Extension = 1024 */
     #define TX_FCTRL_TXPSR_PE_1536  0x00180000UL    /* bit mask to access Preamble Extension = 1536 */
     #define TX_FCTRL_TXPSR_PE_2048  0x00280000UL    /* bit mask to access Preamble Extension = 2048 */
     #define TX_FCTRL_TXPSR_PE_4096  0x000C0000UL    /* bit mask to access Preamble Extension = 4096 */
     /*offset 22 */
     #define TX_FCTRL_TXBOFFS_SHFT   (22)            /* Shift to access transmit buffer index offset */
     #define TX_FCTRL_TXBOFFS_MASK   0xFFC00000UL    /* bit mask to access Transmit buffer index offset 10-bit field */
     /*offset 32 */
     #define TX_FCTRL_IFSDELAY_MASK  0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */
     /****************************************************************************//**
      * @brief Bit definitions for register TX_BUFFER
     **/
     #define TX_BUFFER_ID            0x09            /* Transmit Data Buffer */
     #define TX_BUFFER_LEN           (1024)
     /****************************************************************************//**
      * @brief Bit definitions for register  DX_TIME
     **/
     #define DX_TIME_ID              0x0A            /* Delayed Send or Receive Time (40-bit) */
     #define DX_TIME_LEN             (5)
     /****************************************************************************//**
      * @brief Bit definitions for register 0x08
     **/
     #define REG_0B_ID_RESERVED      0x0B
     /****************************************************************************//**
      * @brief Bit definitions for register RX_FWTO
     **/
     #define RX_FWTO_ID              0x0C            /* Receive Frame Wait Timeout Period */
     #define RX_FWTO_OFFSET          0x00
     #define RX_FWTO_LEN             (2)             /* doc bug*/
     /*mask and shift */
     #define RX_FWTO_MASK            0xFFFF
     /****************************************************************************//**
      * @brief Bit definitions for register SYS_CTRL
     **/
     #define SYS_CTRL_ID             0x0D            /* System Control Register */
     #define SYS_CTRL_OFFSET         0x00
     #define SYS_CTRL_LEN            (4)
     /*masks */
     #define SYS_CTRL_MASK_32        0x010003CFUL    /* System Control Register access mask (all unused fields should always be writen as zero) */
     /*offset 0 */
     #define SYS_CTRL_SFCST          0x00000001UL    /* Suppress Auto-FCS Transmission (on this frame) */
     #define SYS_CTRL_TXSTRT         0x00000002UL    /* Start Transmitting Now */
     #define SYS_CTRL_TXDLYS         0x00000004UL    /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */
     #define SYS_CTRL_CANSFCS        0x00000008UL    /* Cancel Suppression of auto-FCS transmission (on the current frame) */
     #define SYS_CTRL_TRXOFF         0x00000040UL    /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */
     #define SYS_CTRL_WAIT4RESP      0x00000080UL    /* Wait for Response */
     /*offset 8 */
     #define SYS_CTRL_RXENAB         0x00000100UL    /* Enable Receiver Now */
     #define SYS_CTRL_RXDLYE         0x00000200UL    /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/
     /*offset 16 */
     /*offset 24 */
     #define SYS_CTRL_HSRBTOGGLE     0x01000000UL    /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */
     #define SYS_CTRL_HRBT           (SYS_CTRL_HSRBTOGGLE)
     #define SYS_CTRL_HRBT_OFFSET    (3)
     /****************************************************************************//**
      * @brief Bit definitions for register  SYS_MASK
     **/
     #define SYS_MASK_ID             0x0E            /* System Event Mask Register */
     #define SYS_MASK_LEN            (4)
     /*masks */
     #define SYS_MASK_MASK_32        0x3FF7FFFEUL    /* System Event Mask Register access mask (all unused fields should always be writen as zero) */
     /*offset 0 */
     #define SYS_MASK_MCPLOCK        0x00000002UL    /* Mask clock PLL lock event    */
     #define SYS_MASK_MESYNCR        0x00000004UL    /* Mask clock PLL lock event    */
     #define SYS_MASK_MAAT           0x00000008UL    /* Mask automatic acknowledge trigger event */
     #define SYS_MASK_MTXFRB         0x00000010UL    /* Mask transmit frame begins event */
     #define SYS_MASK_MTXPRS         0x00000020UL    /* Mask transmit preamble sent event    */
     #define SYS_MASK_MTXPHS         0x00000040UL    /* Mask transmit PHY Header Sent event  */
     #define SYS_MASK_MTXFRS         0x00000080UL    /* Mask transmit frame sent event   */
     /*offset 8 */
     #define SYS_MASK_MRXPRD         0x00000100UL    /* Mask receiver preamble detected event    */
     #define SYS_MASK_MRXSFDD        0x00000200UL    /* Mask receiver SFD detected event */
     #define SYS_MASK_MLDEDONE       0x00000400UL    /* Mask LDE processing done event   */
     #define SYS_MASK_MRXPHD         0x00000800UL    /* Mask receiver PHY header detect event    */
     #define SYS_MASK_MRXPHE         0x00001000UL    /* Mask receiver PHY header error event */
     #define SYS_MASK_MRXDFR         0x00002000UL    /* Mask receiver data frame ready event */
     #define SYS_MASK_MRXFCG         0x00004000UL    /* Mask receiver FCS good event */
     #define SYS_MASK_MRXFCE         0x00008000UL    /* Mask receiver FCS error event    */
     /*offset 16 */
     #define SYS_MASK_MRXRFSL        0x00010000UL    /* Mask receiver Reed Solomon Frame Sync Loss event */
     #define SYS_MASK_MRXRFTO        0x00020000UL    /* Mask Receive Frame Wait Timeout event    */
     #define SYS_MASK_MLDEERR        0x00040000UL    /* Mask leading edge detection processing error event   */
     #define SYS_MASK_MRXOVRR        0x00100000UL    /* Mask Receiver Overrun event  */
     #define SYS_MASK_MRXPTO         0x00200000UL    /* Mask Preamble detection timeout event    */
     #define SYS_MASK_MGPIOIRQ       0x00400000UL    /* Mask GPIO interrupt event    */
     #define SYS_MASK_MSLP2INIT      0x00800000UL    /* Mask SLEEP to INIT event */
     /*offset 24*/
     #define SYS_MASK_MRFPLLLL       0x01000000UL    /* Mask RF PLL Loosing Lock warning event   */
     #define SYS_MASK_MCPLLLL        0x02000000UL    /* Mask Clock PLL Loosing Lock warning event    */
     #define SYS_MASK_MRXSFDTO       0x04000000UL    /* Mask Receive SFD timeout event   */
     #define SYS_MASK_MHPDWARN       0x08000000UL    /* Mask Half Period Delay Warning event */
     #define SYS_MASK_MTXBERR        0x10000000UL    /* Mask Transmit Buffer Error event */
     #define SYS_MASK_MAFFREJ        0x20000000UL    /* Mask Automatic Frame Filtering rejection event   */
     /****************************************************************************//**
      * @brief Bit definitions for register SYS_STATUS
     **/
     #define SYS_STATUS_ID           0x0F            /* System event Status Register */
     #define SYS_STATUS_OFFSET       0x00
     #define SYS_STATUS_LEN          (5)             /* Note 40 bit register */
     /*masks */
     #define SYS_STATUS_MASK_32      0xFFF7FFFFUL    /* System event Status Register access mask (all unused fields should always be writen as zero) */
     /*offset 0 */
     #define SYS_STATUS_IRQS         0x00000001UL    /* Interrupt Request Status READ ONLY */
     #define SYS_STATUS_CPLOCK       0x00000002UL    /* Clock PLL Lock */
     #define SYS_STATUS_ESYNCR       0x00000004UL    /* External Sync Clock Reset */
     #define SYS_STATUS_AAT          0x00000008UL    /* Automatic Acknowledge Trigger */
     #define SYS_STATUS_TXFRB        0x00000010UL    /* Transmit Frame Begins */
     #define SYS_STATUS_TXPRS        0x00000020UL    /* Transmit Preamble Sent */
     #define SYS_STATUS_TXPHS        0x00000040UL    /* Transmit PHY Header Sent */
     #define SYS_STATUS_TXFRS        0x00000080UL    /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */
     /*offset 8 */
     #define SYS_STATUS_RXPRD        0x00000100UL    /* Receiver Preamble Detected status */
     #define SYS_STATUS_RXSFDD       0x00000200UL    /* Receiver Start Frame Delimiter Detected. */
     #define SYS_STATUS_LDEDONE      0x00000400UL    /* LDE processing done */
     #define SYS_STATUS_RXPHD        0x00000800UL    /* Receiver PHY Header Detect */
     #define SYS_STATUS_RXPHE        0x00001000UL    /* Receiver PHY Header Error */
     #define SYS_STATUS_RXDFR        0x00002000UL    /* Receiver Data Frame Ready */
     #define SYS_STATUS_RXFCG        0x00004000UL    /* Receiver FCS Good */
     #define SYS_STATUS_RXFCE        0x00008000UL    /* Receiver FCS Error */
     /*offset 16 */
     #define SYS_STATUS_RXRFSL       0x00010000UL    /* Receiver Reed Solomon Frame Sync Loss */
     #define SYS_STATUS_RXRFTO       0x00020000UL    /* Receive Frame Wait Timeout */
     #define SYS_STATUS_LDEERR       0x00040000UL    /* Leading edge detection processing error */
     #define SYS_STATUS_reserved     0x00080000UL    /* bit19 reserved */
     #define SYS_STATUS_RXOVRR       0x00100000UL    /* Receiver Overrun */
     #define SYS_STATUS_RXPTO        0x00200000UL    /* Preamble detection timeout */
     #define SYS_STATUS_GPIOIRQ      0x00400000UL    /* GPIO interrupt */
     #define SYS_STATUS_SLP2INIT     0x00800000UL    /* SLEEP to INIT */
     /*offset 24 */
     #define SYS_STATUS_RFPLL_LL     0x01000000UL    /* RF PLL Losing Lock */
     #define SYS_STATUS_CLKPLL_LL    0x02000000UL    /* Clock PLL Losing Lock */
     #define SYS_STATUS_RXSFDTO      0x04000000UL    /* Receive SFD timeout */
     #define SYS_STATUS_HPDWARN      0x08000000UL    /* Half Period Delay Warning */
     #define SYS_STATUS_TXBERR       0x10000000UL    /* Transmit Buffer Error */
     #define SYS_STATUS_AFFREJ       0x20000000UL    /* Automatic Frame Filtering rejection */
     #define SYS_STATUS_HSRBP        0x40000000UL    /* Host Side Receive Buffer Pointer */
     #define SYS_STATUS_ICRBP        0x80000000UL    /* IC side Receive Buffer Pointer READ ONLY */
     /*offset 32 */
     #define SYS_STATUS_RXRSCS       0x0100000000ULL /* Receiver Reed-Solomon Correction Status */
     #define SYS_STATUS_RXPREJ       0x0200000000ULL /* Receiver Preamble Rejection */
     #define SYS_STATUS_TXPUTE       0x0400000000ULL /* Transmit power up time error */
     #define SYS_STATUS_TXERR        (0x0408)        /* These bits are the 16 high bits of status register TXPUTE and HPDWARN flags */
     /* All RX events after a correct packet reception mask. */
     #define SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG | SYS_STATUS_RXPRD | \
                                     SYS_STATUS_RXSFDD | SYS_STATUS_RXPHD | SYS_STATUS_LDEDONE)
     /* All double buffer events mask. */
     #define SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG)
     /* All RX errors mask. */
     #define SYS_STATUS_ALL_RX_ERR  (SYS_STATUS_RXPHE | SYS_STATUS_RXFCE | SYS_STATUS_RXRFSL | SYS_STATUS_RXSFDTO \
                                     | SYS_STATUS_AFFREJ | SYS_STATUS_LDEERR)
     /* User defined RX timeouts (frame wait timeout and preamble detect timeout) mask. */
     #define SYS_STATUS_ALL_RX_TO   (SYS_STATUS_RXRFTO | SYS_STATUS_RXPTO)
     /* All TX events mask. */
     #define SYS_STATUS_ALL_TX      (SYS_STATUS_AAT | SYS_STATUS_TXFRB | SYS_STATUS_TXPRS | \
                                     SYS_STATUS_TXPHS | SYS_STATUS_TXFRS )
     /****************************************************************************//**
      * @brief Bit definitions for register RX_FINFO
     **/
     #define RX_FINFO_ID             0x10            /* RX Frame Information (in double buffer set) */
     #define RX_FINFO_OFFSET         0x00
     #define RX_FINFO_LEN            (4)
     /*mask and shift */
     #define RX_FINFO_MASK_32        0xFFFFFBFFUL    /* System event Status Register access mask (all unused fields should always be writen as zero) */
     #define RX_FINFO_RXFLEN_MASK    0x0000007FUL    /* Receive Frame Length (0 to 127) */
     #define RX_FINFO_RXFLE_MASK     0x00000380UL    /* Receive Frame Length Extension (0 to 7)<<7 */
     #define RX_FINFO_RXFL_MASK_1023 0x000003FFUL    /* Receive Frame Length Extension (0 to 1023) */
     #define RX_FINFO_RXNSPL_MASK    0x00001800UL    /* Receive Non-Standard Preamble Length */
     #define RX_FINFO_RXPSR_MASK     0x000C0000UL    /* RX Preamble Repetition. 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols */
     #define RX_FINFO_RXPEL_MASK     0x000C1800UL    /* Receive Preamble Length = RXPSR+RXNSPL */
     #define RX_FINFO_RXPEL_64       0x00040000UL    /* Receive Preamble length = 64 */
     #define RX_FINFO_RXPEL_128      0x00040800UL    /* Receive Preamble length = 128 */
     #define RX_FINFO_RXPEL_256      0x00041000UL    /* Receive Preamble length = 256 */
     #define RX_FINFO_RXPEL_512      0x00041800UL    /* Receive Preamble length = 512 */
     #define RX_FINFO_RXPEL_1024     0x00080000UL    /* Receive Preamble length = 1024 */
     #define RX_FINFO_RXPEL_1536     0x00080800UL    /* Receive Preamble length = 1536 */
     #define RX_FINFO_RXPEL_2048     0x00081000UL    /* Receive Preamble length = 2048 */
     #define RX_FINFO_RXPEL_4096     0x000C0000UL    /* Receive Preamble length = 4096 */
     #define RX_FINFO_RXBR_MASK      0x00006000UL    /* Receive Bit Rate report. This field reports the received bit rate */
     #define RX_FINFO_RXBR_110k      0x00000000UL    /* Received bit rate = 110 kbps */
     #define RX_FINFO_RXBR_850k      0x00002000UL    /* Received bit rate = 850 kbps */
     #define RX_FINFO_RXBR_6M        0x00004000UL    /* Received bit rate = 6.8 Mbps */
     #define RX_FINFO_RXBR_SHIFT     (13)
     #define RX_FINFO_RNG            0x00008000UL    /* Receiver Ranging. Ranging bit in the received PHY header identifying the frame as a ranging packet. */
     #define RX_FINFO_RNG_SHIFT      (15)
     #define RX_FINFO_RXPRF_MASK     0x00030000UL    /* RX Pulse Repetition Rate report */
     #define RX_FINFO_RXPRF_16M      0x00010000UL    /* PRF being employed in the receiver = 16M */
     #define RX_FINFO_RXPRF_64M      0x00020000UL    /* PRF being employed in the receiver = 64M */
     #define RX_FINFO_RXPRF_SHIFT    (16)
     #define RX_FINFO_RXPACC_MASK    0xFFF00000UL    /* Preamble Accumulation Count */
     #define RX_FINFO_RXPACC_SHIFT   (20)
     /****************************************************************************//**
      * @brief Bit definitions for register RX_BUFFER
     **/
     #define RX_BUFFER_ID            0x11            /* Receive Data Buffer (in double buffer set) */
     #define RX_BUFFER_LEN           (1024)
     /****************************************************************************//**
      * @brief Bit definitions for register RX_FQUAL
     **/
     #define RX_FQUAL_ID             0x12            /* Rx Frame Quality information (in double buffer set) */
     #define RX_FQUAL_LEN            (8)             /* note 64 bit register*/
     /*mask and shift */
     /*offset 0 */
     #define RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL   /* Standard Deviation of Noise */
     #define RX_EQUAL_STD_NOISE_SHIFT (0)
     #define STD_NOISE_MASK          RX_EQUAL_STD_NOISE_MASK
     #define STD_NOISE_SHIFT         RX_EQUAL_STD_NOISE_SHIFT
     /*offset 16 */
     #define RX_EQUAL_FP_AMPL2_MASK  0xFFFF0000ULL   /* First Path Amplitude point 2 */
     #define RX_EQUAL_FP_AMPL2_SHIFT (16)
     #define FP_AMPL2_MASK           RX_EQUAL_FP_AMPL2_MASK
     #define FP_AMPL2_SHIFT          RX_EQUAL_FP_AMPL2_SHIFT
     /*offset 32*/
     #define RX_EQUAL_PP_AMPL3_MASK  0x0000FFFF00000000ULL   /* First Path Amplitude point 3 */
     #define RX_EQUAL_PP_AMPL3_SHIFT (32)
     #define PP_AMPL3_MASK           RX_EQUAL_PP_AMPL3_MASK
     #define PP_AMPL3_SHIFT          RX_EQUAL_PP_AMPL3_SHIFT
     /*offset 48*/
     #define RX_EQUAL_CIR_MXG_MASK   0xFFFF000000000000ULL   /* Channel Impulse Response Max Growth */
     #define RX_EQUAL_CIR_MXG_SHIFT  (48)
     #define CIR_MXG_MASK            RX_EQUAL_CIR_MXG_MASK
     #define CIR_MXG_SHIFT           RX_EQUAL_CIR_MXG_SHIFT
     /****************************************************************************//**
      * @brief Bit definitions for register RX_TTCKI
      *      The value here is the interval over which the timing offset reported
      *      in the RXTOFS field of Register file: 0x14 RX_TTCKO is measured.
      *      The clock offset is calculated by dividing RXTTCKI by RXTOFS.
      *      The value in RXTTCKI will take just one of two values depending on the PRF: 0x01F00000 @ 16 MHz PRF,
      *      and 0x01FC0000 @ 64 MHz PRF.
     **/
     #define RX_TTCKI_ID             0x13            /* Receiver Time Tracking Interval (in double buffer set) */
     #define RX_TTCKI_LEN            (4)
     /****************************************************************************//**
      * @brief Bit definitions for register RX_TTCKO
     **/
     #define RX_TTCKO_ID             0x14            /* Receiver Time Tracking Offset (in double buffer set) */
     #define RX_TTCKO_LEN            (5)             /* Note 40 bit register */
     /*mask and shift */
     #define RX_TTCKO_MASK_32        0xFF07FFFFUL    /* Receiver Time Tracking Offset access mask (all unused fields should always be writen as zero) */
     /*offset 0 */
     #define RX_TTCKO_RXTOFS_MASK    0x0007FFFFUL    /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity*/
     /*offset 24 */
     #define RX_TTCKO_RSMPDEL_MASK   0xFF000000UL    /* This 8-bit field reports an internal re-sampler delay value */
     /*offset 32 */
     #define RX_TTCKO_RCPHASE_MASK   0x7F0000000000ULL   /* This 7-bit field reports the receive carrier phase adjustment at time the ranging timestamp is made. */
     /****************************************************************************//**
      * @brief Bit definitions for register RX_TIME
     **/
     #define RX_TIME_ID              0x15            /* Receive Message Time of Arrival (in double buffer set) */
     #define RX_TIME_LLEN            (14)
     #define RX_TIME_RX_STAMP_LEN    (5)             /* read only 5 bytes (the adjusted timestamp (40:0)) */
     #define RX_STAMP_LEN            RX_TIME_RX_STAMP_LEN
     /*mask and shift */
     #define RX_TIME_RX_STAMP_OFFSET  (0) /* byte 0..4 40 bit Reports the fully adjusted time of reception. */
     #define RX_TIME_FP_INDEX_OFFSET  (5)    /* byte 5..6 16 bit First path index. */
     #define RX_TIME_FP_AMPL1_OFFSET  (7)    /* byte 7..8 16 bit First Path Amplitude point 1 */   /* doc bug */
     #define RX_TIME_FP_RAWST_OFFSET  (9)    /* byte 9..13 40 bit Raw Timestamp for the frame */
     /****************************************************************************//**
      * @brief Bit definitions for register
     **/
     #define REG_16_ID_RESERVED      0x16
     /****************************************************************************//**
      * @brief Bit definitions for register
     **/
     #define TX_TIME_ID              0x17            /* Transmit Message Time of Sending */
     #define TX_TIME_LLEN            (10)
     #define TX_TIME_TX_STAMP_LEN    (5)             /* 40-bits = 5 bytes */
     #define TX_STAMP_LEN            TX_TIME_TX_STAMP_LEN
     /*mask and shift */
     #define TX_TIME_TX_STAMP_OFFSET  (0) /* byte 0..4 40 bit Reports the fully adjusted time of transmission */
     #define TX_TIME_TX_RAWST_OFFSET  (5) /* byte 5..9 40 bit Raw Timestamp for the frame */
     /****************************************************************************//**
      * @brief Bit definitions for register TX_ANTD
     **/
     #define TX_ANTD_ID              0x18            /* 16-bit Delay from Transmit to Antenna */
     #define TX_ANTD_OFFSET          0x00
     #define TX_ANTD_LEN             (2)
     /****************************************************************************//**
      * @brief Bit definitions for register SYS_STATES
      *        Register map register file 0x19 is reserved
+     *
     **/
     #define SYS_STATE_ID            0x19            /* System State information READ ONLY */
     #define SYS_STATE_LEN           (5)
     /****************************************************************************//**
      * @brief Bit definitions for register ACK_RESP_T
     **/
     /* Acknowledge (31:24 preamble symbol delay before auto ACK is sent) and respose (19:0 - unit 1us) timer */
     #define ACK_RESP_T_ID           0x1A            /* Acknowledgement Time and Response Time */
     #define ACK_RESP_T_LEN          (4)
     /*mask and shift */
     #define ACK_RESP_T_MASK         0xFF0FFFFFUL    /* Acknowledgement Time and Response access mask */
     #define ACK_RESP_T_W4R_TIM_OFFSET 0             /* In bytes */
     #define ACK_RESP_T_W4R_TIM_MASK 0x000FFFFFUL    /* Wait-for-Response turn-around Time 20 bit field */
     #define W4R_TIM_MASK            ACK_RESP_T_W4R_TIM_MASK
     #define ACK_RESP_T_ACK_TIM_OFFSET 3             /* In bytes */
     #define ACK_RESP_T_ACK_TIM_MASK 0xFF000000UL    /* Auto-Acknowledgement turn-around Time */
     #define ACK_TIM_MASK            ACK_RESP_T_ACK_TIM_MASK
     /****************************************************************************//**
      * @brief Bit definitions for register 0x1B 0x1C
     **/
     #define REG_1B_ID_RESERVED      0x1B
     #define REG_1C_ID_RESERVED      0x1C
     /****************************************************************************//**
      * @brief Bit definitions for register RX_SNIFF
      *        Sniff Mode Configuration or Pulsed Preamble Reception Configuration
     **/
     #define RX_SNIFF_ID             0x1D            /* Sniff Mode Configuration */
     #define RX_SNIFF_OFFSET         0x00
     #define RX_SNIFF_LEN            (4)
     /*mask and shift */
     #define RX_SNIFF_MASK           0x0000FF0FUL    /*  */
     #define RX_SNIFF_SNIFF_ONT_MASK 0x0000000FUL    /* SNIFF Mode ON time. Specified in units of PAC */
     #define SNIFF_ONT_MASK          RX_SNIFF_SNIFF_ONT_MASK
     #define RX_SNIFF_SNIFF_OFFT_MASK 0x0000FF00UL   /* SNIFF Mode OFF time specified in units of approximately 1mkS, or 128 system clock cycles.*/
     #define SNIFF_OFFT_MASK         RX_SNIFF_SNIFF_OFFT_MASK
     /****************************************************************************//**
      * @brief Bit definitions for register TX_POWER
     **/
     #define TX_POWER_ID             0x1E            /* TX Power Control */
     #define TX_POWER_LEN            (4)
     /*mask and shift definition for Smart Transmit Power Control*/
     #define TX_POWER_BOOSTNORM_MASK 0x00000000UL    /* This is the normal power setting used for frames that do not fall */
     #define BOOSTNORM_MASK          TX_POWER_BOOSTNORM_MASK
     #define TX_POWER_BOOSTNORM_SHIFT (0)
     #define TX_POWER_BOOSTP500_MASK 0x00000000UL    /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.5 ms duration */
     #define BOOSTP500_MASK          TX_POWER_BOOSTP500_MASK
     #define TX_POWER_BOOSTP500_SHIFT (8)
     #define TX_POWER_BOOSTP250_MASK 0x00000000UL    /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.25 ms duration */
     #define BOOSTP250_MASK          TX_POWER_BOOSTP250_MASK
     #define TX_POWER_BOOSTP250_SHIFT (16)
     #define TX_POWER_BOOSTP125_MASK 0x00000000UL    /* This value sets the power applied during transmission at the 6.8 Mbps data rate frames that are less than 0.125 ms */
     #define BOOSTP125_MASK          TX_POWER_BOOSTP125_MASK
     #define TX_POWER_BOOSTP125_SHIFT (24)
     /*mask and shift definition for Manual Transmit Power Control (DIS_STXP=1 in SYS_CFG)*/
     #define TX_POWER_MAN_DEFAULT    0x0E080222UL
     #define TX_POWER_TXPOWPHR_MASK  0x0000FF00UL    /* This power setting is applied during the transmission of the PHY header (PHR) portion of the frame. */
     #define TX_POWER_TXPOWSD_MASK   0x00FF0000UL    /* This power setting is applied during the transmission of the synchronisation header (SHR) and data portions of the frame. */
     /****************************************************************************//**
      * @brief Bit definitions for register CHAN_CTRL
     **/
     #define CHAN_CTRL_ID            0x1F            /* Channel Control */
     #define CHAN_CTRL_LEN           (4)
     /*mask and shift */
     #define CHAN_CTRL_MASK          0xFFFF00FFUL    /* Channel Control Register access mask */
     #define CHAN_CTRL_TX_CHAN_MASK  0x0000000FUL    /* Supported channels are 1, 2, 3, 4, 5, and 7.*/
     #define CHAN_CTRL_TX_CHAN_SHIFT (0)             /* Bits 0..3        TX channel number 0-15 selection */
     #define CHAN_CTRL_RX_CHAN_MASK  0x000000F0UL
     #define CHAN_CTRL_RX_CHAN_SHIFT (4)             /* Bits 4..7        RX channel number 0-15 selection */
     #define CHAN_CTRL_RXFPRF_MASK   0x000C0000UL    /* Bits 18..19      Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
     #define CHAN_CTRL_RXFPRF_SHIFT  (18)
     /* Specific RXFPRF configuration */
     #define CHAN_CTRL_RXFPRF_4      0x00000000UL    /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
     #define CHAN_CTRL_RXFPRF_16     0x00040000UL    /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
     #define CHAN_CTRL_RXFPRF_64     0x00080000UL    /* Specify (Force) RX Pulse Repetition Rate: 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. */
     #define CHAN_CTRL_TX_PCOD_MASK  0x07C00000UL    /* Bits 22..26      TX Preamble Code selection, 1 to 24. */
     #define CHAN_CTRL_TX_PCOD_SHIFT (22)
     #define CHAN_CTRL_RX_PCOD_MASK  0xF8000000UL    /* Bits 27..31      RX Preamble Code selection, 1 to 24. */
     #define CHAN_CTRL_RX_PCOD_SHIFT (27)
     /*offset 16 */
     #define CHAN_CTRL_DWSFD         0x00020000UL    /* Bit 17 This bit enables a non-standard DecaWave proprietary SFD sequence. */
     #define CHAN_CTRL_DWSFD_SHIFT   (17)
     #define CHAN_CTRL_TNSSFD        0x00100000UL    /* Bit 20 Non-standard SFD in the transmitter */
     #define CHAN_CTRL_TNSSFD_SHIFT  (20)
     #define CHAN_CTRL_RNSSFD        0x00200000UL    /* Bit 21 Non-standard SFD in the receiver */
     #define CHAN_CTRL_RNSSFD_SHIFT  (21)
     /****************************************************************************//**
      * @brief Bit definitions for register 0x20
     **/
     #define REG_20_ID_RESERVED      0x20
     /****************************************************************************//**
      * @brief Bit definitions for register USR_SFD
      *        Please read User Manual : User defined SFD sequence
     **/
     #define USR_SFD_ID              0x21            /* User-specified short/long TX/RX SFD sequences */
     #define USR_SFD_LEN             (41)
     #define DW_NS_SFD_LEN_110K      64              /* Decawave non-standard SFD length for 110 kbps */
     #define DW_NS_SFD_LEN_850K      16              /* Decawave non-standard SFD length for 850 kbps */
     #define DW_NS_SFD_LEN_6M8       8               /* Decawave non-standard SFD length for 6.8 Mbps */
     /****************************************************************************//**
      * @brief Bit definitions for register
     **/
     #define REG_22_ID_RESERVED      0x22
     /****************************************************************************//**
      * @brief Bit definitions for register AGC_CTRL
      * Please take care to write to this register as doing so may cause the DW1000 to malfunction
     **/
     #define AGC_CTRL_ID             0x23            /* Automatic Gain Control configuration */
     #define AGC_CTRL_LEN            (32)
     #define AGC_CFG_STS_ID          AGC_CTRL_ID
     /* offset from AGC_CTRL_ID in bytes */
     #define AGC_CTRL1_OFFSET        (0x02)
     #define AGC_CTRL1_LEN           (2)
     #define AGC_CTRL1_MASK          0x0001          /* access mask to AGC configuration and control register */
     #define AGC_CTRL1_DIS_AM        0x0001          /* Disable AGC Measurement. The DIS_AM bit is set by default. */
     /* offset from AGC_CTRL_ID in bytes */
     /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
     #define AGC_TUNE1_OFFSET        (0x04)
     #define AGC_TUNE1_LEN           (2)
     #define AGC_TUNE1_MASK          0xFFFF          /* It is a 16-bit tuning register for the AGC. */
     #define AGC_TUNE1_16M           0x8870
     #define AGC_TUNE1_64M           0x889B
     /* offset from AGC_CTRL_ID in bytes */
     /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
     #define AGC_TUNE2_OFFSET        (0x0C)
     #define AGC_TUNE2_LEN           (4)
     #define AGC_TUNE2_MASK          0xFFFFFFFFUL
     #define AGC_TUNE2_VAL           0X2502A907UL
     /* offset from AGC_CTRL_ID in bytes */
     /* Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction */
     #define AGC_TUNE3_OFFSET        (0x12)
     #define AGC_TUNE3_LEN           (2)
     #define AGC_TUNE3_MASK          0xFFFF
     #define AGC_TUNE3_VAL           0X0055
     /* offset from AGC_CTRL_ID in bytes */
     #define AGC_STAT1_OFFSET        (0x1E)
     #define AGC_STAT1_LEN           (3)
     #define AGC_STAT1_MASK          0x0FFFFF
     #define AGC_STAT1_EDG1_MASK     0x0007C0        /* This 5-bit gain value relates to input noise power measurement. */
     #define AGC_STAT1_EDG2_MASK     0x0FF800        /* This 9-bit value relates to the input noise power measurement. */
     /****************************************************************************//**
      * @brief Bit definitions for register EXT_SYNC
     **/
     #define EXT_SYNC_ID             0x24            /* External synchronisation control */
     #define EXT_SYNC_LEN            (12)
     /* offset from EXT_SYNC_ID in bytes */
     #define EC_CTRL_OFFSET          (0x00)
     #define EC_CTRL_LEN             (4)
     #define EC_CTRL_MASK            0x00000FFBUL    /* sub-register 0x00 is the External clock synchronisation counter configuration register */
     #define EC_CTRL_OSTSM           0x00000001UL    /* External transmit synchronisation mode enable */
     #define EC_CTRL_OSRSM           0x00000002UL    /* External receive synchronisation mode enable */
     #define EC_CTRL_PLLLCK          0x04            /* PLL lock detect enable */
     #define EC_CTRL_OSTRM           0x00000800UL    /* External timebase reset mode enable */
     #define EC_CTRL_WAIT_MASK       0x000007F8UL    /* Wait counter used for external transmit synchronisation and external timebase reset */
     /* offset from EXT_SYNC_ID in bytes */
     #define EC_RXTC_OFFSET          (0x04)
     #define EC_RXTC_LEN             (4)
     #define EC_RXTC_MASK            0xFFFFFFFFUL    /* External clock synchronisation counter captured on RMARKER */
     /* offset from EXT_SYNC_ID in bytes */
     #define EC_GOLP                 (0x08)
     #define EC_GOLP_LEN             (4)
     #define EC_GOLP_MASK            0x0000003FUL    /* sub-register 0x08 is the External clock offset to first path 1 GHz counter, EC_GOLP */
     #define EC_GOLP_OFFSET_EXT_MASK 0x0000003FUL    /* This register contains the 1 GHz count from the arrival of the RMARKER and the next edge of the external clock. */
     /****************************************************************************//**
      * @brief Bit definitions for register ACC_MEM
     **/
     #define ACC_MEM_ID              0x25            /* Read access to accumulator data */
     #define ACC_MEM_LEN             (4064)
     /****************************************************************************//**
      * @brief Bit definitions for register GPIO_CTRL
     **/
     #define GPIO_CTRL_ID            0x26            /* Peripheral register bus 1 access - GPIO control */
     #define GPIO_CTRL_LEN           (44)
     /* offset from GPIO_CTRL in bytes */
     #define GPIO_MODE_OFFSET        0x00            /* sub-register 0x00 is the GPIO Mode Control Register */
     #define GPIO_MODE_LEN           (4)
     #define GPIO_MODE_MASK          0x00FFFFC0UL
     #define GPIO_MSGP0_MASK         0x000000C0UL    /* Mode Selection for GPIO0/RXOKLED */
     #define GPIO_MSGP1_MASK         0x00000300UL    /* Mode Selection for GPIO1/SFDLED */
     #define GPIO_MSGP2_MASK         0x00000C00UL    /* Mode Selection for GPIO2/RXLED */
     #define GPIO_MSGP3_MASK         0x00003000UL    /* Mode Selection for GPIO3/TXLED */
     #define GPIO_MSGP4_MASK         0x0000C000UL    /* Mode Selection for GPIO4/EXTPA */
     #define GPIO_MSGP5_MASK         0x00030000UL    /* Mode Selection for GPIO5/EXTTXE */
     #define GPIO_MSGP6_MASK         0x000C0000UL    /* Mode Selection for GPIO6/EXTRXE */
     #define GPIO_MSGP7_MASK         0x00300000UL    /* Mode Selection for SYNC/GPIO7 */
     #define GPIO_MSGP8_MASK         0x00C00000UL    /* Mode Selection for IRQ/GPIO8 */
     #define GPIO_PIN2_RXLED         0x00000400UL    /* The pin operates as the RXLED output */
     #define GPIO_PIN3_TXLED         0x00001000UL    /* The pin operates as the TXLED output */
     #define GPIO_PIN4_EXTPA         0x00004000UL    /* The pin operates as the EXTPA output */
     #define GPIO_PIN5_EXTTXE        0x00010000UL    /* The pin operates as the EXTTXE output */
     #define GPIO_PIN6_EXTRXE        0x00040000UL    /* The pin operates as the EXTRXE output */
     /* offset from GPIO_CTRL in bytes */
     #define GPIO_DIR_OFFSET         0x08            /* sub-register 0x08 is the GPIO Direction Control Register */
     #define GPIO_DIR_LEN            (3)
     #define GPIO_DIR_MASK           0x0011FFFFUL
     #define GxP0                    0x00000001UL    /* GPIO0 Only changed if the GxM0 mask bit has a value of 1 for the write operation*/
     #define GxP1                    0x00000002UL    /* GPIO1. (See GDP0). */
     #define GxP2                    0x00000004UL    /* GPIO2. (See GDP0). */
     #define GxP3                    0x00000008UL    /* GPIO3. (See GDP0). */
     #define GxP4                    0x00000100UL    /* GPIO4. (See GDP0). */
     #define GxP5                    0x00000200UL    /* GPIO5. (See GDP0). */
     #define GxP6                    0x00000400UL    /* GPIO6. (See GDP0). */
     #define GxP7                    0x00000800UL    /* GPIO7. (See GDP0). */
     #define GxP8                    0x00010000UL    /* GPIO8 */
     #define GxM0                    0x00000010UL    /* Mask for GPIO0 */
     #define GxM1                    0x00000020UL    /* Mask for GPIO1. (See GDM0). */
     #define GxM2                    0x00000040UL    /* Mask for GPIO2. (See GDM0). */
     #define GxM3                    0x00000080UL    /* Mask for GPIO3. (See GDM0). */
     #define GxM4                    0x00001000UL    /* Mask for GPIO4. (See GDM0). */
     #define GxM5                    0x00002000UL    /* Mask for GPIO5. (See GDM0). */
     #define GxM6                    0x00004000UL    /* Mask for GPIO6. (See GDM0). */
     #define GxM7                    0x00008000UL    /* Mask for GPIO7. (See GDM0). */
     #define GxM8                    0x00100000UL    /* Mask for GPIO8. (See GDM0). */
     #define GDP0    GxP0    /* Direction Selection for GPIO0. 1 = input, 0 = output. Only changed if the GDM0 mask bit has a value of 1 for the write operation*/
     #define GDP1    GxP1    /* Direction Selection for GPIO1. (See GDP0). */
     #define GDP2    GxP2    /* Direction Selection for GPIO2. (See GDP0). */
     #define GDP3    GxP3    /* Direction Selection for GPIO3. (See GDP0). */
     #define GDP4    GxP4    /* Direction Selection for GPIO4. (See GDP0). */
     #define GDP5    GxP5    /* Direction Selection for GPIO5. (See GDP0). */
     #define GDP6    GxP6    /* Direction Selection for GPIO6. (See GDP0). */
     #define GDP7    GxP7    /* Direction Selection for GPIO7. (See GDP0). */
     #define GDP8    GxP8    /* Direction Selection for GPIO8 */
     #define GDM0    GxM0    /* Mask for setting the direction of GPIO0 */
     #define GDM1    GxM1    /* Mask for setting the direction of GPIO1. (See GDM0). */
     #define GDM2    GxM2    /* Mask for setting the direction of GPIO2. (See GDM0). */
     #define GDM3    GxM3    /* Mask for setting the direction of GPIO3. (See GDM0). */
     #define GDM4    GxM4    /* Mask for setting the direction of GPIO4. (See GDM0). */
     #define GDM5    GxM5    /* Mask for setting the direction of GPIO5. (See GDM0). */
     #define GDM6    GxM6    /* Mask for setting the direction of GPIO6. (See GDM0). */
     #define GDM7    GxM7    /* Mask for setting the direction of GPIO7. (See GDM0). */
     #define GDM8    GxM8    /* Mask for setting the direction of GPIO8. (See GDM0). */
     /* offset from GPIO_CTRL in bytes */
     #define GPIO_DOUT_OFFSET        0x0C            /* sub-register 0x0C is the GPIO data output register. */
     #define GPIO_DOUT_LEN           (3)
     #define GPIO_DOUT_MASK          GPIO_DIR_MASK
     /* offset from GPIO_CTRL in bytes */
     #define GPIO_IRQE_OFFSET        0x10            /* sub-register 0x10 is the GPIO interrupt enable register */
     #define GPIO_IRQE_LEN           (4)
     #define GPIO_IRQE_MASK          0x000001FFUL
     #define GIRQx0                  0x00000001UL    /* IRQ bit0 */
     #define GIRQx1                  0x00000002UL    /* IRQ bit1 */
     #define GIRQx2                  0x00000004UL    /* IRQ bit2 */
     #define GIRQx3                  0x00000008UL    /* IRQ bit3 */
     #define GIRQx4                  0x00000010UL    /* IRQ bit4 */
     #define GIRQx5                  0x00000020UL    /* IRQ bit5 */
     #define GIRQx6                  0x00000040UL    /* IRQ bit6 */
     #define GIRQx7                  0x00000080UL    /* IRQ bit7 */
     #define GIRQx8                  0x00000100UL    /* IRQ bit8 */
     #define GIRQE0  GIRQx0  /* GPIO IRQ Enable for GPIO0 input. Value 1 = enable, 0 = disable*/
     #define GIRQE1  GIRQx1  /*  */
     #define GIRQE2  GIRQx2  /*  */
     #define GIRQE3  GIRQx3  /*  */
     #define GIRQE4  GIRQx4  /*  */
     #define GIRQE5  GIRQx5  /*  */
     #define GIRQE6  GIRQx6  /*  */
     #define GIRQE7  GIRQx7  /*  */
     #define GIRQE8  GIRQx8  /* Value 1 = enable, 0 = disable */
     /* offset from GPIO_CTRL in bytes */
     #define GPIO_ISEN_OFFSET        0x14    /* sub-register 0x14 is the GPIO interrupt sense selection register */
     #define GPIO_ISEN_LEN           (4)
     #define GPIO_ISEN_MASK          GPIO_IRQE_MASK
     #define GISEN0  GIRQx0  /* GPIO IRQ Sense selection GPIO0 input. Value 0 = High or Rising-Edge, 1 = Low or falling-edge.*/
     #define GISEN1  GIRQx1  /*  */
     #define GISEN2  GIRQx2  /*  */
     #define GISEN3  GIRQx3  /*  */
     #define GISEN4  GIRQx4  /*  */
     #define GISEN5  GIRQx5  /*  */
     #define GISEN6  GIRQx6  /*  */
     #define GISEN7  GIRQx7  /*  */

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