amiro-lld / drivers / DW1000 / v2 / decadriver / deca_params_init.c @ 22401187
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/*! ----------------------------------------------------------------------------
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* @file deca_params_init.c
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* @brief DW1000 configuration parameters
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*
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* @attention
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*
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* Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
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*
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* All rights reserved.
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*
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*
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* -------------------------------------------------------------------------------------------------------------------
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**/
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#include <stdio.h> |
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#include <stdlib.h> |
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#include "deca_regs.h" |
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#include "deca_device_api.h" |
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#include "deca_param_types.h" |
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//-----------------------------------------
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// map the channel number to the index in the configuration arrays below
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// 0th element is chan 1, 1st is chan 2, 2nd is chan 3, 3rd is chan 4, 4th is chan 5, 5th is chan 7
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const uint8 chan_idx[NUM_CH_SUPPORTED] = {0, 0, 1, 2, 3, 4, 0, 5}; |
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//-----------------------------------------
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const uint32 tx_config[NUM_CH] =
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{ |
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RF_TXCTRL_CH1, |
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RF_TXCTRL_CH2, |
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RF_TXCTRL_CH3, |
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RF_TXCTRL_CH4, |
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RF_TXCTRL_CH5, |
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RF_TXCTRL_CH7, |
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}; |
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//Frequency Synthesiser - PLL configuration
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const uint32 fs_pll_cfg[NUM_CH] =
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{ |
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FS_PLLCFG_CH1, |
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FS_PLLCFG_CH2, |
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FS_PLLCFG_CH3, |
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FS_PLLCFG_CH4, |
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FS_PLLCFG_CH5, |
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FS_PLLCFG_CH7 |
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}; |
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//Frequency Synthesiser - PLL tuning
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const uint8 fs_pll_tune[NUM_CH] =
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{ |
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FS_PLLTUNE_CH1, |
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FS_PLLTUNE_CH2, |
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FS_PLLTUNE_CH3, |
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FS_PLLTUNE_CH4, |
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FS_PLLTUNE_CH5, |
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FS_PLLTUNE_CH7 |
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}; |
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//bandwidth configuration
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const uint8 rx_config[NUM_BW] =
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{ |
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RF_RXCTRLH_NBW, |
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RF_RXCTRLH_WBW |
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}; |
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const agc_cfg_struct agc_config =
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{ |
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AGC_TUNE2_VAL, |
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{ AGC_TUNE1_16M , AGC_TUNE1_64M } //adc target
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}; |
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//DW non-standard SFD length for 110k, 850k and 6.81M
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const uint8 dwnsSFDlen[NUM_BR] =
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{ |
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DW_NS_SFD_LEN_110K, |
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DW_NS_SFD_LEN_850K, |
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DW_NS_SFD_LEN_6M8 |
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}; |
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// SFD Threshold
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const uint16 sftsh[NUM_BR][NUM_SFD] =
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{ |
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{ |
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DRX_TUNE0b_110K_STD, |
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DRX_TUNE0b_110K_NSTD |
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}, |
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{ |
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DRX_TUNE0b_850K_STD, |
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DRX_TUNE0b_850K_NSTD |
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}, |
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{ |
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DRX_TUNE0b_6M8_STD, |
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DRX_TUNE0b_6M8_NSTD |
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} |
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}; |
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const uint16 dtune1[NUM_PRF] =
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{ |
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DRX_TUNE1a_PRF16, |
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DRX_TUNE1a_PRF64 |
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}; |
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const uint32 digital_bb_config[NUM_PRF][NUM_PACS] =
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{ |
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{ |
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DRX_TUNE2_PRF16_PAC8, |
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DRX_TUNE2_PRF16_PAC16, |
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DRX_TUNE2_PRF16_PAC32, |
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DRX_TUNE2_PRF16_PAC64 |
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}, |
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{ |
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DRX_TUNE2_PRF64_PAC8, |
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DRX_TUNE2_PRF64_PAC16, |
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DRX_TUNE2_PRF64_PAC32, |
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DRX_TUNE2_PRF64_PAC64 |
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} |
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}; |
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const uint16 lde_replicaCoeff[PCODES] =
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{ |
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0, // No preamble code 0 |
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LDE_REPC_PCODE_1, |
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LDE_REPC_PCODE_2, |
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LDE_REPC_PCODE_3, |
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LDE_REPC_PCODE_4, |
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LDE_REPC_PCODE_5, |
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LDE_REPC_PCODE_6, |
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LDE_REPC_PCODE_7, |
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LDE_REPC_PCODE_8, |
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LDE_REPC_PCODE_9, |
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LDE_REPC_PCODE_10, |
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LDE_REPC_PCODE_11, |
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LDE_REPC_PCODE_12, |
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LDE_REPC_PCODE_13, |
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LDE_REPC_PCODE_14, |
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LDE_REPC_PCODE_15, |
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LDE_REPC_PCODE_16, |
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LDE_REPC_PCODE_17, |
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LDE_REPC_PCODE_18, |
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LDE_REPC_PCODE_19, |
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LDE_REPC_PCODE_20, |
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LDE_REPC_PCODE_21, |
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LDE_REPC_PCODE_22, |
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LDE_REPC_PCODE_23, |
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LDE_REPC_PCODE_24 |
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}; |
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