amiro-lld / drivers / DW1000 / v2 / decadriver / deca_regs.h @ 22401187
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/*! ------------------------------------------------------------------------------------------------------------------
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* @file deca_regs.h
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* @brief DW1000 Register Definitions
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* This file supports assembler and C development for DW1000 enabled devices
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*
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* @attention
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*
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* Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
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*
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* All rights reserved.
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*
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*/
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#ifndef _DECA_REGS_H_
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#define _DECA_REGS_H_
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#ifdef __cplusplus
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extern "C" { |
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#endif
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#include "deca_version.h" |
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/****************************************************************************//** |
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* @brief Bit definitions for register DEV_ID
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**/
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#define DEV_ID_ID 0x00 /* Device ID register, includes revision info (0xDECA0130) */ |
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#define DEV_ID_LEN (4) |
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/* mask and shift */
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#define DEV_ID_REV_MASK 0x0000000FUL /* Revision */ |
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#define DEV_ID_VER_MASK 0x000000F0UL /* Version */ |
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#define DEV_ID_MODEL_MASK 0x0000FF00UL /* The MODEL identifies the device. The DW1000 is device type 0x01 */ |
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#define DEV_ID_RIDTAG_MASK 0xFFFF0000UL /* Register Identification Tag 0XDECA */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register EUI_64
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**/
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#define EUI_64_ID 0x01 /* IEEE Extended Unique Identifier (63:0) */ |
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#define EUI_64_OFFSET 0x00 |
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#define EUI_64_LEN (8) |
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/****************************************************************************//** |
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* @brief Bit definitions for register PANADR
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**/
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#define PANADR_ID 0x03 /* PAN ID (31:16) and Short Address (15:0) */ |
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#define PANADR_LEN (4) |
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/*mask and shift */
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#define PANADR_SHORT_ADDR_OFFSET 0 /* In bytes */ |
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#define PANADR_SHORT_ADDR_MASK 0x0000FFFFUL /* Short Address */ |
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#define PANADR_PAN_ID_OFFSET 2 /* In bytes */ |
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#define PANADR_PAN_ID_MASK 0xFFFF0000UL /* PAN Identifier */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register 0x05
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**/
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#define REG_05_ID_RESERVED 0x05 |
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/****************************************************************************//** |
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* @brief Bit definitions for register SYS_CFG
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**/
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#define SYS_CFG_ID 0x04 /* System Configuration (31:0) */ |
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#define SYS_CFG_LEN (4) |
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/*mask and shift */
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#define SYS_CFG_MASK 0xF047FFFFUL /* access mask to SYS_CFG_ID */ |
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#define SYS_CFG_FF_ALL_EN 0x000001FEUL /* Frame filtering options all frames allowed */ |
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/*offset 0 */
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#define SYS_CFG_FFE 0x00000001UL /* Frame Filtering Enable. This bit enables the frame filtering functionality */ |
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#define SYS_CFG_FFBC 0x00000002UL /* Frame Filtering Behave as a Co-ordinator */ |
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#define SYS_CFG_FFAB 0x00000004UL /* Frame Filtering Allow Beacon frame reception */ |
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#define SYS_CFG_FFAD 0x00000008UL /* Frame Filtering Allow Data frame reception */ |
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#define SYS_CFG_FFAA 0x00000010UL /* Frame Filtering Allow Acknowledgment frame reception */ |
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#define SYS_CFG_FFAM 0x00000020UL /* Frame Filtering Allow MAC command frame reception */ |
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#define SYS_CFG_FFAR 0x00000040UL /* Frame Filtering Allow Reserved frame types */ |
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#define SYS_CFG_FFA4 0x00000080UL /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */ |
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/*offset 8 */
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#define SYS_CFG_FFA5 0x00000100UL /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */ |
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#define SYS_CFG_HIRQ_POL 0x00000200UL /* Host interrupt polarity */ |
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#define SYS_CFG_SPI_EDGE 0x00000400UL /* SPI data launch edge */ |
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#define SYS_CFG_DIS_FCE 0x00000800UL /* Disable frame check error handling */ |
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#define SYS_CFG_DIS_DRXB 0x00001000UL /* Disable Double RX Buffer */ |
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#define SYS_CFG_DIS_PHE 0x00002000UL /* Disable receiver abort on PHR error */ |
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#define SYS_CFG_DIS_RSDE 0x00004000UL /* Disable Receiver Abort on RSD error */ |
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#define SYS_CFG_FCS_INIT2F 0x00008000UL /* initial seed value for the FCS generation and checking function */ |
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/*offset 16 */
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#define SYS_CFG_PHR_MODE_SHFT 16 |
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#define SYS_CFG_PHR_MODE_00 0x00000000UL /* Standard Frame mode */ |
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#define SYS_CFG_PHR_MODE_11 0x00030000UL /* Long Frames mode */ |
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#define SYS_CFG_DIS_STXP 0x00040000UL /* Disable Smart TX Power control */ |
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#define SYS_CFG_RXM110K 0x00400000UL /* Receiver Mode 110 kbps data rate */ |
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/*offset 24 */
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#define SYS_CFG_RXWTOE 0x10000000UL /* Receive Wait Timeout Enable. */ |
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#define SYS_CFG_RXAUTR 0x20000000UL /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */ |
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#define SYS_CFG_AUTOACK 0x40000000UL /* Automatic Acknowledgement Enable */ |
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#define SYS_CFG_AACKPEND 0x80000000UL /* Automatic Acknowledgement Pending bit control */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register SYS_TIME
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**/
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#define SYS_TIME_ID 0x06 /* System Time Counter (40-bit) */ |
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#define SYS_TIME_OFFSET 0x00 |
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#define SYS_TIME_LEN (5) /* Note 40 bit register */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register 0x07
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**/
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#define REG_07_ID_RESERVED 0x07 |
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/****************************************************************************//** |
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* @brief Bit definitions for register TX_FCTRL
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**/
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#define TX_FCTRL_ID 0x08 /* Transmit Frame Control */ |
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#define TX_FCTRL_LEN (5) /* Note 40 bit register */ |
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/*masks (low 32 bit) */
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#define TX_FCTRL_TFLEN_MASK 0x0000007FUL /* bit mask to access Transmit Frame Length */ |
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#define TX_FCTRL_TFLE_MASK 0x00000380UL /* bit mask to access Transmit Frame Length Extension */ |
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#define TX_FCTRL_FLE_MASK 0x000003FFUL /* bit mask to access Frame Length field */ |
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#define TX_FCTRL_TXBR_MASK 0x00006000UL /* bit mask to access Transmit Bit Rate */ |
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#define TX_FCTRL_TXPRF_MASK 0x00030000UL /* bit mask to access Transmit Pulse Repetition Frequency */ |
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#define TX_FCTRL_TXPSR_MASK 0x000C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ |
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#define TX_FCTRL_PE_MASK 0x00300000UL /* bit mask to access Preamble Extension */ |
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#define TX_FCTRL_TXPSR_PE_MASK 0x003C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ |
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#define TX_FCTRL_SAFE_MASK_32 0xFFFFE3FFUL /* FSCTRL has fields which should always be writen zero */ |
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/*offset 0 */
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/*offset 8 */
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#define TX_FCTRL_TXBR_110k 0x00000000UL /* Transmit Bit Rate = 110k */ |
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#define TX_FCTRL_TXBR_850k 0x00002000UL /* Transmit Bit Rate = 850k */ |
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#define TX_FCTRL_TXBR_6M 0x00004000UL /* Transmit Bit Rate = 6.8M */ |
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#define TX_FCTRL_TXBR_SHFT (13) /* shift to access Data Rate field */ |
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#define TX_FCTRL_TR 0x00008000UL /* Transmit Ranging enable */ |
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#define TX_FCTRL_TR_SHFT (15) /* shift to access Ranging bit */ |
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/*offset 16 */
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#define TX_FCTRL_TXPRF_SHFT (16) /* shift to access Pulse Repetition Frequency field */ |
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#define TX_FCTRL_TXPRF_4M 0x00000000UL /* Transmit Pulse Repetition Frequency = 4 Mhz */ |
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#define TX_FCTRL_TXPRF_16M 0x00010000UL /* Transmit Pulse Repetition Frequency = 16 Mhz */ |
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#define TX_FCTRL_TXPRF_64M 0x00020000UL /* Transmit Pulse Repetition Frequency = 64 Mhz */ |
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#define TX_FCTRL_TXPSR_SHFT (18) /* shift to access Preamble Symbol Repetitions field */ |
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#define TX_FCTRL_PE_SHFT (20) /* shift to access Preamble length Extension to allow specification of non-standard values */ |
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#define TX_FCTRL_TXPSR_PE_16 0x00000000UL /* bit mask to access Preamble Extension = 16 */ |
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#define TX_FCTRL_TXPSR_PE_64 0x00040000UL /* bit mask to access Preamble Extension = 64 */ |
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#define TX_FCTRL_TXPSR_PE_128 0x00140000UL /* bit mask to access Preamble Extension = 128 */ |
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#define TX_FCTRL_TXPSR_PE_256 0x00240000UL /* bit mask to access Preamble Extension = 256 */ |
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#define TX_FCTRL_TXPSR_PE_512 0x00340000UL /* bit mask to access Preamble Extension = 512 */ |
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#define TX_FCTRL_TXPSR_PE_1024 0x00080000UL /* bit mask to access Preamble Extension = 1024 */ |
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#define TX_FCTRL_TXPSR_PE_1536 0x00180000UL /* bit mask to access Preamble Extension = 1536 */ |
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#define TX_FCTRL_TXPSR_PE_2048 0x00280000UL /* bit mask to access Preamble Extension = 2048 */ |
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#define TX_FCTRL_TXPSR_PE_4096 0x000C0000UL /* bit mask to access Preamble Extension = 4096 */ |
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/*offset 22 */
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#define TX_FCTRL_TXBOFFS_SHFT (22) /* Shift to access transmit buffer index offset */ |
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#define TX_FCTRL_TXBOFFS_MASK 0xFFC00000UL /* bit mask to access Transmit buffer index offset 10-bit field */ |
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/*offset 32 */
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#define TX_FCTRL_IFSDELAY_MASK 0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register TX_BUFFER
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**/
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#define TX_BUFFER_ID 0x09 /* Transmit Data Buffer */ |
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#define TX_BUFFER_LEN (1024) |
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/****************************************************************************//** |
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* @brief Bit definitions for register DX_TIME
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**/
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#define DX_TIME_ID 0x0A /* Delayed Send or Receive Time (40-bit) */ |
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#define DX_TIME_LEN (5) |
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/****************************************************************************//** |
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* @brief Bit definitions for register 0x08
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**/
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#define REG_0B_ID_RESERVED 0x0B |
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/****************************************************************************//** |
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* @brief Bit definitions for register RX_FWTO
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**/
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#define RX_FWTO_ID 0x0C /* Receive Frame Wait Timeout Period */ |
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#define RX_FWTO_OFFSET 0x00 |
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#define RX_FWTO_LEN (2) |
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/*mask and shift */
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#define RX_FWTO_MASK 0xFFFF |
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/****************************************************************************//** |
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* @brief Bit definitions for register SYS_CTRL
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**/
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#define SYS_CTRL_ID 0x0D /* System Control Register */ |
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#define SYS_CTRL_OFFSET 0x00 |
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#define SYS_CTRL_LEN (4) |
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/*masks */
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#define SYS_CTRL_MASK_32 0x010003CFUL /* System Control Register access mask (all unused fields should always be writen as zero) */ |
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/*offset 0 */
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#define SYS_CTRL_SFCST 0x00000001UL /* Suppress Auto-FCS Transmission (on this frame) */ |
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#define SYS_CTRL_TXSTRT 0x00000002UL /* Start Transmitting Now */ |
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#define SYS_CTRL_TXDLYS 0x00000004UL /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */ |
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#define SYS_CTRL_CANSFCS 0x00000008UL /* Cancel Suppression of auto-FCS transmission (on the current frame) */ |
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#define SYS_CTRL_TRXOFF 0x00000040UL /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */ |
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#define SYS_CTRL_WAIT4RESP 0x00000080UL /* Wait for Response */ |
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/*offset 8 */
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#define SYS_CTRL_RXENAB 0x00000100UL /* Enable Receiver Now */ |
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#define SYS_CTRL_RXDLYE 0x00000200UL /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/ |
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/*offset 16 */
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/*offset 24 */
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#define SYS_CTRL_HSRBTOGGLE 0x01000000UL /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */ |
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#define SYS_CTRL_HRBT (SYS_CTRL_HSRBTOGGLE)
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#define SYS_CTRL_HRBT_OFFSET (3) |
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/****************************************************************************//** |
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* @brief Bit definitions for register SYS_MASK
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**/
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#define SYS_MASK_ID 0x0E /* System Event Mask Register */ |
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#define SYS_MASK_LEN (4) |
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/*masks */
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#define SYS_MASK_MASK_32 0x3FF7FFFEUL /* System Event Mask Register access mask (all unused fields should always be writen as zero) */ |
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/*offset 0 */
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#define SYS_MASK_MCPLOCK 0x00000002UL /* Mask clock PLL lock event */ |
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#define SYS_MASK_MESYNCR 0x00000004UL /* Mask clock PLL lock event */ |
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#define SYS_MASK_MAAT 0x00000008UL /* Mask automatic acknowledge trigger event */ |
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#define SYS_MASK_MTXFRB 0x00000010UL /* Mask transmit frame begins event */ |
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#define SYS_MASK_MTXPRS 0x00000020UL /* Mask transmit preamble sent event */ |
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#define SYS_MASK_MTXPHS 0x00000040UL /* Mask transmit PHY Header Sent event */ |
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#define SYS_MASK_MTXFRS 0x00000080UL /* Mask transmit frame sent event */ |
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/*offset 8 */
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#define SYS_MASK_MRXPRD 0x00000100UL /* Mask receiver preamble detected event */ |
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#define SYS_MASK_MRXSFDD 0x00000200UL /* Mask receiver SFD detected event */ |
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#define SYS_MASK_MLDEDONE 0x00000400UL /* Mask LDE processing done event */ |
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#define SYS_MASK_MRXPHD 0x00000800UL /* Mask receiver PHY header detect event */ |
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#define SYS_MASK_MRXPHE 0x00001000UL /* Mask receiver PHY header error event */ |
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#define SYS_MASK_MRXDFR 0x00002000UL /* Mask receiver data frame ready event */ |
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#define SYS_MASK_MRXFCG 0x00004000UL /* Mask receiver FCS good event */ |
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#define SYS_MASK_MRXFCE 0x00008000UL /* Mask receiver FCS error event */ |
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/*offset 16 */
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#define SYS_MASK_MRXRFSL 0x00010000UL /* Mask receiver Reed Solomon Frame Sync Loss event */ |
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#define SYS_MASK_MRXRFTO 0x00020000UL /* Mask Receive Frame Wait Timeout event */ |
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#define SYS_MASK_MLDEERR 0x00040000UL /* Mask leading edge detection processing error event */ |
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#define SYS_MASK_MRXOVRR 0x00100000UL /* Mask Receiver Overrun event */ |
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#define SYS_MASK_MRXPTO 0x00200000UL /* Mask Preamble detection timeout event */ |
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#define SYS_MASK_MGPIOIRQ 0x00400000UL /* Mask GPIO interrupt event */ |
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#define SYS_MASK_MSLP2INIT 0x00800000UL /* Mask SLEEP to INIT event */ |
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/*offset 24*/
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#define SYS_MASK_MRFPLLLL 0x01000000UL /* Mask RF PLL Loosing Lock warning event */ |
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#define SYS_MASK_MCPLLLL 0x02000000UL /* Mask Clock PLL Loosing Lock warning event */ |
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#define SYS_MASK_MRXSFDTO 0x04000000UL /* Mask Receive SFD timeout event */ |
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#define SYS_MASK_MHPDWARN 0x08000000UL /* Mask Half Period Delay Warning event */ |
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#define SYS_MASK_MTXBERR 0x10000000UL /* Mask Transmit Buffer Error event */ |
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#define SYS_MASK_MAFFREJ 0x20000000UL /* Mask Automatic Frame Filtering rejection event */ |
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/****************************************************************************//** |
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* @brief Bit definitions for register SYS_STATUS
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**/
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#define SYS_STATUS_ID 0x0F /* System event Status Register */ |
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#define SYS_STATUS_OFFSET 0x00 |
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#define SYS_STATUS_LEN (5) /* Note 40 bit register */ |
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/*masks */
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#define SYS_STATUS_MASK_32 0xFFF7FFFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */ |
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/*offset 0 */
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#define SYS_STATUS_IRQS 0x00000001UL /* Interrupt Request Status READ ONLY */ |
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#define SYS_STATUS_CPLOCK 0x00000002UL /* Clock PLL Lock */ |
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#define SYS_STATUS_ESYNCR 0x00000004UL /* External Sync Clock Reset */ |
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#define SYS_STATUS_AAT 0x00000008UL /* Automatic Acknowledge Trigger */ |
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#define SYS_STATUS_TXFRB 0x00000010UL /* Transmit Frame Begins */ |
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#define SYS_STATUS_TXPRS 0x00000020UL /* Transmit Preamble Sent */ |
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#define SYS_STATUS_TXPHS 0x00000040UL /* Transmit PHY Header Sent */ |
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#define SYS_STATUS_TXFRS 0x00000080UL /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */ |
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/*offset 8 */
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#define SYS_STATUS_RXPRD 0x00000100UL /* Receiver Preamble Detected status */ |
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#define SYS_STATUS_RXSFDD 0x00000200UL /* Receiver Start Frame Delimiter Detected. */ |
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#define SYS_STATUS_LDEDONE 0x00000400UL /* LDE processing done */ |
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#define SYS_STATUS_RXPHD 0x00000800UL /* Receiver PHY Header Detect */ |
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#define SYS_STATUS_RXPHE 0x00001000UL /* Receiver PHY Header Error */ |
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#define SYS_STATUS_RXDFR 0x00002000UL /* Receiver Data Frame Ready */ |
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#define SYS_STATUS_RXFCG 0x00004000UL /* Receiver FCS Good */ |
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#define SYS_STATUS_RXFCE 0x00008000UL /* Receiver FCS Error */ |
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/*offset 16 */
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#define SYS_STATUS_RXRFSL 0x00010000UL /* Receiver Reed Solomon Frame Sync Loss */ |
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#define SYS_STATUS_RXRFTO 0x00020000UL /* Receive Frame Wait Timeout */ |
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#define SYS_STATUS_LDEERR 0x00040000UL /* Leading edge detection processing error */ |
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#define SYS_STATUS_reserved 0x00080000UL /* bit19 reserved */ |
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#define SYS_STATUS_RXOVRR 0x00100000UL /* Receiver Overrun */ |
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#define SYS_STATUS_RXPTO 0x00200000UL /* Preamble detection timeout */ |
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#define SYS_STATUS_GPIOIRQ 0x00400000UL /* GPIO interrupt */ |