amiro-lld / include / alld_l3g4200d.h @ 616f3584
History | View | Annotate | Download (9.198 KB)
| 1 |
/*
|
|---|---|
| 2 |
AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
|
| 3 |
Copyright (C) 2016..2018 Thomas Schöpping et al.
|
| 4 |
|
| 5 |
This program is free software: you can redistribute it and/or modify
|
| 6 |
it under the terms of the GNU Lesser General Public License as published by
|
| 7 |
the Free Software Foundation, either version 3 of the License, or
|
| 8 |
(at your option) any later version.
|
| 9 |
|
| 10 |
This program is distributed in the hope that it will be useful,
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 13 |
GNU Lesser General Public License for more details.
|
| 14 |
|
| 15 |
You should have received a copy of the GNU Lesser General Public License
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 17 |
*/
|
| 18 |
|
| 19 |
#ifndef _AMIROLLD_L3G4200D_H_
|
| 20 |
#define _AMIROLLD_L3G4200D_H_
|
| 21 |
|
| 22 |
#include <amiro-lld.h> |
| 23 |
|
| 24 |
#if defined(AMIROLLD_CFG_USE_L3G4200D) || defined(__DOXYGEN__)
|
| 25 |
|
| 26 |
/**
|
| 27 |
* @brief A rising edge indicates an interrupt.
|
| 28 |
*/
|
| 29 |
#define L3G4200D_LLD_INT_EDGE APAL_GPIO_EDGE_RISING
|
| 30 |
|
| 31 |
/**
|
| 32 |
* @brief The L3G4200D driver struct
|
| 33 |
*/
|
| 34 |
typedef struct { |
| 35 |
apalSPIDriver_t* spid; /**< @brief The SPI Driver */
|
| 36 |
} L3G4200DDriver; |
| 37 |
|
| 38 |
/**
|
| 39 |
* @brief SPI access modes.
|
| 40 |
*/
|
| 41 |
typedef enum { |
| 42 |
L3G4200D_LLD_SPI_MULT = 0x40u,
|
| 43 |
L3G4200D_LLD_SPI_READ = 0x80u,
|
| 44 |
L3G4200D_LLD_SPI_WRITE = 0x00u,
|
| 45 |
} l3g4200d_lld_SPI_mode_t; |
| 46 |
|
| 47 |
/**
|
| 48 |
* @brief Registers.
|
| 49 |
*/
|
| 50 |
typedef enum { |
| 51 |
L3G4200D_LLD_REGISTER_WHO_AM_I = 0x0F,
|
| 52 |
L3G4200D_LLD_REGISTER_CTRL_REG1 = 0x20,
|
| 53 |
L3G4200D_LLD_REGISTER_CTRL_REG2 = 0x21,
|
| 54 |
L3G4200D_LLD_REGISTER_CTRL_REG3 = 0x22,
|
| 55 |
L3G4200D_LLD_REGISTER_CTRL_REG4 = 0x23,
|
| 56 |
L3G4200D_LLD_REGISTER_CTRL_REG5 = 0x24,
|
| 57 |
L3G4200D_LLD_REGISTER_REFERECE = 0x25,
|
| 58 |
L3G4200D_LLD_REGISTER_OUT_TEMP = 0x26,
|
| 59 |
L3G4200D_LLD_REGISTER_STATUS_REG = 0x27,
|
| 60 |
L3G4200D_LLD_REGISTER_OUT_X_L = 0x28,
|
| 61 |
L3G4200D_LLD_REGISTER_OUT_X_H = 0x29,
|
| 62 |
L3G4200D_LLD_REGISTER_OUT_Y_L = 0x2A,
|
| 63 |
L3G4200D_LLD_REGISTER_OUT_Y_H = 0x2B,
|
| 64 |
L3G4200D_LLD_REGISTER_OUT_Z_L = 0x2C,
|
| 65 |
L3G4200D_LLD_REGISTER_OUT_Z_H = 0x2D,
|
| 66 |
L3G4200D_LLD_REGISTER_FIFO_CTRL_REG = 0x2E,
|
| 67 |
L3G4200D_LLD_REGISTER_FIFO_SRC_REG = 0x2F,
|
| 68 |
L3G4200D_LLD_REGISTER_INT1_CFG = 0x30,
|
| 69 |
L3G4200D_LLD_REGISTER_INT1_SRC = 0x31,
|
| 70 |
L3G4200D_LLD_REGISTER_INT1_TSH_XH = 0x32,
|
| 71 |
L3G4200D_LLD_REGISTER_INT1_TSH_XL = 0x33,
|
| 72 |
L3G4200D_LLD_REGISTER_INT1_TSH_YH = 0x34,
|
| 73 |
L3G4200D_LLD_REGISTER_INT1_TSH_YL = 0x35,
|
| 74 |
L3G4200D_LLD_REGISTER_INT1_TSH_ZH = 0x36,
|
| 75 |
L3G4200D_LLD_REGISTER_INT1_TSH_ZL = 0x37,
|
| 76 |
L3G4200D_LLD_REGISTER_INT1_DURATION = 0x38,
|
| 77 |
} l3g4200d_lld_register_t; |
| 78 |
|
| 79 |
/**
|
| 80 |
* @brief WHO_AM_I register constant content.
|
| 81 |
*/
|
| 82 |
typedef enum { |
| 83 |
L3G4200D_LLD_WHO_AM_I = 0xD3,
|
| 84 |
} l3g4200d_lld_whoami_t; |
| 85 |
|
| 86 |
/**
|
| 87 |
* @brief Control register 1 flags.
|
| 88 |
*/
|
| 89 |
typedef enum { |
| 90 |
L3G4200D_LLD_DR_100_HZ = 0x00,
|
| 91 |
L3G4200D_LLD_DR_200_HZ = 0x40,
|
| 92 |
L3G4200D_LLD_DR_400_HZ = 0x80,
|
| 93 |
L3G4200D_LLD_DR_800_HZ = 0xC0,
|
| 94 |
L3G4200D_LLD_BW_12_5 = 0x00,
|
| 95 |
L3G4200D_LLD_BW_20 = 0x00,
|
| 96 |
L3G4200D_LLD_BW_25 = 0x10,
|
| 97 |
L3G4200D_LLD_BW_30 = 0x00,
|
| 98 |
L3G4200D_LLD_BW_35 = 0x10,
|
| 99 |
L3G4200D_LLD_BW_50 = 0x20,
|
| 100 |
L3G4200D_LLD_BW_70 = 0x30,
|
| 101 |
L3G4200D_LLD_BW_110 = 0x30,
|
| 102 |
L3G4200D_LLD_PD = 0x08,
|
| 103 |
L3G4200D_LLD_ZEN = 0x04,
|
| 104 |
L3G4200D_LLD_YEN = 0x02,
|
| 105 |
L3G4200D_LLD_XEN = 0x01,
|
| 106 |
} l3g4200d_lld_ctrl_reg1_t; |
| 107 |
|
| 108 |
/**
|
| 109 |
* @brief Control register 2 flags.
|
| 110 |
*/
|
| 111 |
typedef enum { |
| 112 |
L3G4200D_LLD_HPM_NORMAL_RST = 0x00,
|
| 113 |
L3G4200D_LLD_HPM_REFERENCE = 0x10,
|
| 114 |
L3G4200D_LLD_HPM_NORMAL = 0x20,
|
| 115 |
L3G4200D_LLD_HPM_AUTO_RST = 0x30,
|
| 116 |
L3G4200D_LLD_HPCF_2 = 0x00,
|
| 117 |
L3G4200D_LLD_HPCF_4 = 0x01,
|
| 118 |
L3G4200D_LLD_HPCF_8 = 0x02,
|
| 119 |
L3G4200D_LLD_HPCF_16 = 0x03,
|
| 120 |
L3G4200D_LLD_HPCF_32 = 0x04,
|
| 121 |
L3G4200D_LLD_HPCF_64 = 0x05,
|
| 122 |
L3G4200D_LLD_HPCF_128 = 0x06,
|
| 123 |
L3G4200D_LLD_HPCF_256 = 0x07,
|
| 124 |
L3G4200D_LLD_HPCF_512 = 0x08,
|
| 125 |
L3G4200D_LLD_HPCF_1024 = 0x09,
|
| 126 |
} l3g4200d_lld_ctrl_reg2_t; |
| 127 |
|
| 128 |
/**
|
| 129 |
* @brief Control register 3 flags.
|
| 130 |
*/
|
| 131 |
typedef enum { |
| 132 |
L3G4200D_LLD_I1_INT1 = 0x80,
|
| 133 |
L3G4200D_LLD_I1_BOOT = 0x40,
|
| 134 |
L3G4200D_LLD_H_IACTIVE = 0x20,
|
| 135 |
L3G4200D_LLD_PP_OD = 0x10,
|
| 136 |
L3G4200D_LLD_I2_DRDY = 0x08,
|
| 137 |
L3G4200D_LLD_I2_WTM = 0x04,
|
| 138 |
L3G4200D_LLD_I2_ORUN = 0x02,
|
| 139 |
L3G4200D_LLD_I2_EMPTY = 0x01,
|
| 140 |
} l3g4200d_lld_ctrl_reg3_t; |
| 141 |
|
| 142 |
/**
|
| 143 |
* @brief Control register 4 flags.
|
| 144 |
*/
|
| 145 |
typedef enum { |
| 146 |
L3G4200D_LLD_BDU_CONT = 0x00,
|
| 147 |
L3G4200D_LLD_BDU_SINGLE = 0x80,
|
| 148 |
L3G4200D_LLD_BLE_MSB = 0x40,
|
| 149 |
L3G4200D_LLD_BLE_LSB = 0x00,
|
| 150 |
L3G4200D_LLD_FS_250_DPS = 0x00,
|
| 151 |
L3G4200D_LLD_FS_500_DPS = 0x10,
|
| 152 |
L3G4200D_LLD_FS_2000_DPS = 0x20,
|
| 153 |
L3G4200D_LLD_ST_SIGN_M = 0x04,
|
| 154 |
L3G4200D_LLD_ST_SIGN_P = 0x00,
|
| 155 |
L3G4200D_LLD_ST_EN = 0x02,
|
| 156 |
L3G4200D_LLD_SIM_3W = 0x01,
|
| 157 |
L3G4200D_LLD_SIM_4W = 0x00,
|
| 158 |
} l3g4200d_lld_ctrl_reg4_t; |
| 159 |
|
| 160 |
/**
|
| 161 |
* @brief Control register 5 flags.
|
| 162 |
*/
|
| 163 |
typedef enum { |
| 164 |
L3G4200D_LLD_BOOT = 0x80,
|
| 165 |
L3G4200D_LLD_FIFO_EN = 0x40,
|
| 166 |
L3G4200D_LLD_HP_EN = 0x10,
|
| 167 |
L3G4200D_LLD_INT1_SEL_NOHP = 0x00,
|
| 168 |
L3G4200D_LLD_INT1_SEL_HP = 0x04,
|
| 169 |
L3G4200D_LLD_INT1_SEL_LP = 0x08,
|
| 170 |
L3G4200D_LLD_OUT_SEL_NOHP = 0x00,
|
| 171 |
L3G4200D_LLD_OUT_SEL_HP = 0x01,
|
| 172 |
L3G4200D_LLD_OUT_SEL_LP = 0x02,
|
| 173 |
} l3g4200d_lld_ctrl_reg5_t; |
| 174 |
|
| 175 |
/**
|
| 176 |
* @brief Status register flags.
|
| 177 |
*/
|
| 178 |
typedef enum { |
| 179 |
L3G4200D_LLD_ZYXOR = 0x80,
|
| 180 |
L3G4200D_LLD_ZOR = 0x40,
|
| 181 |
L3G4200D_LLD_YOR = 0x20,
|
| 182 |
L3G4200D_LLD_XOR = 0x10,
|
| 183 |
L3G4200D_LLD_ZYXDA = 0x08,
|
| 184 |
L3G4200D_LLD_ZDA = 0x04,
|
| 185 |
L3G4200D_LLD_YDA = 0x02,
|
| 186 |
L3G4200D_LLD_XDA = 0x01,
|
| 187 |
} l3g4200d_lld_status_reg_t; |
| 188 |
|
| 189 |
/**
|
| 190 |
* @brief Fifo control register masks.
|
| 191 |
*/
|
| 192 |
typedef enum { |
| 193 |
L3G4200D_LLD_FM_BYPASS = 0x00,
|
| 194 |
L3G4200D_LLD_FM_FMMODE = 0x20,
|
| 195 |
L3G4200D_LLD_FM_STREAM = 0x40,
|
| 196 |
L3G4200D_LLD_FM_STREAM2FIFO = 0x60,
|
| 197 |
L3G4200D_LLD_FM_BYPASS2STREAM = 0x80,
|
| 198 |
L3G4200D_LLD_WTM_MASK = 0x1F,
|
| 199 |
} l3g4200d_lld_fifo_ctrl_reg_t; |
| 200 |
|
| 201 |
/**
|
| 202 |
* @brief FIFO source register masks.
|
| 203 |
*/
|
| 204 |
typedef enum { |
| 205 |
L3G4200D_LLD_WTM = 0x80,
|
| 206 |
L3G4200D_LLD_OVRN = 0x40,
|
| 207 |
L3G4200D_LLD_EMPTY = 0x20,
|
| 208 |
L3G4200D_LLD_FSS_MASK = 0x1F,
|
| 209 |
} l3g4200d_lld_fifo_src_reg_t; |
| 210 |
|
| 211 |
/**
|
| 212 |
* @brief Interrupt 1 config register flags.
|
| 213 |
*/
|
| 214 |
typedef enum { |
| 215 |
L3G4200D_LLD_ANDOR = 0x80,
|
| 216 |
L3G4200D_LLD_LIR = 0x40,
|
| 217 |
L3G4200D_LLD_ZHIE = 0x20,
|
| 218 |
L3G4200D_LLD_ZLIE = 0x10,
|
| 219 |
L3G4200D_LLD_YHIE = 0x08,
|
| 220 |
L3G4200D_LLD_YLIE = 0x04,
|
| 221 |
L3G4200D_LLD_XHIE = 0x02,
|
| 222 |
L3G4200D_LLD_XLIE = 0x01,
|
| 223 |
} l3g4200d_lld_int1_cfg_reg_t; |
| 224 |
|
| 225 |
/**
|
| 226 |
* @brief Interrupt 1 source register flags.
|
| 227 |
*/
|
| 228 |
typedef enum { |
| 229 |
L3G4200D_LLD_IA = 0x40,
|
| 230 |
L3G4200D_LLD_ZH = 0x20,
|
| 231 |
L3G4200D_LLD_ZL = 0x10,
|
| 232 |
L3G4200D_LLD_YH = 0x08,
|
| 233 |
L3G4200D_LLD_YL = 0x04,
|
| 234 |
L3G4200D_LLD_XH = 0x02,
|
| 235 |
L3G4200D_LLD_XL = 0x01,
|
| 236 |
} l3g4200d_lld_int1_src_t; |
| 237 |
|
| 238 |
/**
|
| 239 |
* @brief Threshold mask.
|
| 240 |
*/
|
| 241 |
enum {
|
| 242 |
L3G4200D_LLD_THS_L_MASK = 0x7F
|
| 243 |
}; |
| 244 |
|
| 245 |
/**
|
| 246 |
* @brief Interrupt duration register masks.
|
| 247 |
*/
|
| 248 |
typedef enum { |
| 249 |
L3G4200D_LLD_INT1_WAIT = 0x80,
|
| 250 |
L3G4200D_LLD_INT1_DURATION_MASK = 0x7F,
|
| 251 |
} l3g4200d_lld_int1_duration_reg_t; |
| 252 |
|
| 253 |
/**
|
| 254 |
* @brief Axis enum.
|
| 255 |
*/
|
| 256 |
typedef enum { |
| 257 |
L3G4200D_LLD_X_AXIS = 0x00,
|
| 258 |
L3G4200D_LLD_Y_AXIS = 0x01,
|
| 259 |
L3G4200D_LLD_Z_AXIS = 0x02,
|
| 260 |
} l3g4200d_lld_axis_t; |
| 261 |
|
| 262 |
/**
|
| 263 |
* @brief Config register struct.
|
| 264 |
*/
|
| 265 |
typedef union { |
| 266 |
uint8_t data[5];
|
| 267 |
struct {
|
| 268 |
uint8_t ctrl_reg1; |
| 269 |
uint8_t ctrl_reg2; |
| 270 |
uint8_t ctrl_reg3; |
| 271 |
uint8_t ctrl_reg4; |
| 272 |
uint8_t ctrl_reg5; |
| 273 |
} registers; |
| 274 |
} l3g4200d_lld_cfg_t; |
| 275 |
|
| 276 |
/**
|
| 277 |
* @brief Interrupt config struct.
|
| 278 |
*/
|
| 279 |
typedef union { |
| 280 |
uint8_t data[9];
|
| 281 |
struct {
|
| 282 |
uint8_t int1_cfg; |
| 283 |
uint8_t int1_src; |
| 284 |
uint8_t int1_tsh_xh; |
| 285 |
uint8_t int1_tsh_xl; |
| 286 |
uint8_t int1_tsh_yh; |
| 287 |
uint8_t int1_tsh_yl; |
| 288 |
uint8_t int1_tsh_zh; |
| 289 |
uint8_t int1_tsh_zl; |
| 290 |
uint8_t int1_duration; |
| 291 |
} registers; |
| 292 |
} l3g4200d_lld_int_cfg_t; |
| 293 |
|
| 294 |
#ifdef __cplusplus
|
| 295 |
extern "C" { |
| 296 |
#endif
|
| 297 |
apalExitStatus_t l3g4200d_lld_read_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, uint8_t* const data, const uint8_t length); |
| 298 |
apalExitStatus_t l3g4200d_lld_write_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, const uint8_t* const data, const uint8_t length); |
| 299 |
apalExitStatus_t l3g4200d_lld_read_all_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_cfg_t* const cfg); |
| 300 |
apalExitStatus_t l3g4200d_lld_read_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_axis_t axis, const l3g4200d_lld_cfg_t* const cfg); |
| 301 |
apalExitStatus_t l3g4200d_lld_read_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_cfg_t* const cfg); |
| 302 |
apalExitStatus_t l3g4200d_lld_write_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_cfg_t cfg); |
| 303 |
apalExitStatus_t l3g4200d_lld_read_int_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_int_cfg_t* const cfg); |
| 304 |
apalExitStatus_t l3g4200d_lld_write_int_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_int_cfg_t cfg); |
| 305 |
apalExitStatus_t l3g4200d_lld_read_int_src(const L3G4200DDriver* const l3gd, uint8_t* const cfg); |
| 306 |
apalExitStatus_t l3g4200d_lld_read_status_register(const L3G4200DDriver* const l3gd, uint8_t* const status); |
| 307 |
apalExitStatus_t l3g4200d_lld_read_fifo_ctrl_register(const L3G4200DDriver* const l3gd, uint8_t* const fifo); |
| 308 |
apalExitStatus_t l3g4200d_lld_write_fifo_ctrl_register(const L3G4200DDriver* const l3gd, const uint8_t fifo); |
| 309 |
apalExitStatus_t l3g4200d_lld_read_fifo_src_register(const L3G4200DDriver* const l3gdd, uint8_t* const fifo); |
| 310 |
#ifdef __cplusplus
|
| 311 |
} |
| 312 |
#endif
|
| 313 |
|
| 314 |
#endif /* defined(AMIROLLD_CFG_USE_L3G4200D) */ |
| 315 |
|
| 316 |
#endif /* _AMIROLLD_L3G4200D_H_ */ |