AMiRo-OS

#if (AMIROLLD_CFG_DW1000 == 1)

    #include "v1/alld_dw1000_v1.h"

    #include "v1/alld_dw1000_regs_v1.h"

    #include "v1/deca_instance_v1.h"

#elif (AMIROLLD_CFG_DW1000 == 0)

    #error "DW1000 LLD implementation for v0 is not ready yet."

#else

    #error "invalid value assigned to AMIROLLD_CFG_DW1000 in alldconf.h"

#endif /* defined(AMIROLLD_CFG_DW1000) == 1 */

/*! ------------------------------------------------------------------------------------------------------------------

 * @file    deca_regs.h

 * @brief   DW1000 Register Definitions

 *          This file supports assembler and C development for DW1000 enabled devices

 *

 * @attention

 *

 * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.

 *

 * All rights reserved.

 *

 */

#ifndef __DECA_REGS_V1_H

#define DECA_REGS_V1_H

#ifdef __cplusplus

extern "C" {

#endif

#include <amiro-lld.h>

#if (defined(AMIROLLD_CFG_DW1000) && (AMIROLLD_CFG_DW1000 == 1)) || defined(__DOXYGEN__)

/****************************************************************************//**

 * @brief Bit definitions for register DEV_ID

**/

#define DEV_ID_ID               0x00            /* Device ID register, includes revision info (0xDECA0130) */

#define DEV_ID_LEN              (4)

/* mask and shift */

#define DEV_ID_REV_MASK         0x0000000FUL    /* Revision */

#define DEV_ID_VER_MASK         0x000000F0UL    /* Version */

#define DEV_ID_MODEL_MASK       0x0000FF00UL    /* The MODEL identifies the device. The DW1000 is device type 0x01 */

#define DEV_ID_RIDTAG_MASK      0xFFFF0000UL    /* Register Identification Tag 0XDECA */

/****************************************************************************//**

 * @brief Bit definitions for register EUI_64

**/

#define EUI_64_ID               0x01            /* IEEE Extended Unique Identifier (63:0) */

#define EUI_64_OFFSET           0x00

#define EUI_64_LEN              (8)

/****************************************************************************//**

 * @brief Bit definitions for register PANADR

**/

#define PANADR_ID               0x03            /* PAN ID (31:16) and Short Address (15:0) */

#define PANADR_LEN              (4)

/*mask and shift */

#define PANADR_SHORT_ADDR_OFFSET 0              /* In bytes */

#define PANADR_SHORT_ADDR_MASK  0x0000FFFFUL    /* Short Address */

#define PANADR_PAN_ID_OFFSET     2              /* In bytes */

#define PANADR_PAN_ID_MASK      0xFFFF00F0UL    /* PAN Identifier */

/****************************************************************************//**

 * @brief Bit definitions for register 0x05

**/

#define REG_05_ID_RESERVED      0x05

/****************************************************************************//**

 * @brief Bit definitions for register SYS_CFG

**/

#define SYS_CFG_ID              0x04            /* System Configuration (31:0) */

#define SYS_CFG_LEN             (4)

/*mask and shift */

#define SYS_CFG_MASK            0xF047FFFFUL    /* access mask to SYS_CFG_ID */

#define SYS_CFG_FF_ALL_EN       0x000001FEUL    /* Frame filtering options all frames allowed */

/*offset 0 */

#define SYS_CFG_FFE             0x00000001UL    /* Frame Filtering Enable. This bit enables the frame filtering functionality */

#define SYS_CFG_FFBC            0x00000002UL    /* Frame Filtering Behave as a Co-ordinator */

#define SYS_CFG_FFAB            0x00000004UL    /* Frame Filtering Allow Beacon frame reception */

#define SYS_CFG_FFAD            0x00000008UL    /* Frame Filtering Allow Data frame reception */

#define SYS_CFG_FFAA            0x00000010UL    /* Frame Filtering Allow Acknowledgment frame reception */

#define SYS_CFG_FFAM            0x00000020UL    /* Frame Filtering Allow MAC command frame reception */

#define SYS_CFG_FFAR            0x00000040UL    /* Frame Filtering Allow Reserved frame types */

#define SYS_CFG_FFA4            0x00000080UL    /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */

/*offset 8 */

#define SYS_CFG_FFA5            0x00000100UL    /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */

#define SYS_CFG_HIRQ_POL        0x00000200UL    /* Host interrupt polarity */

#define SYS_CFG_SPI_EDGE        0x00000400UL    /* SPI data launch edge */

#define SYS_CFG_DIS_FCE         0x00000800UL    /* Disable frame check error handling */

#define SYS_CFG_DIS_DRXB        0x00001000UL    /* Disable Double RX Buffer */

#define SYS_CFG_DIS_PHE         0x00002000UL    /* Disable receiver abort on PHR error */

#define SYS_CFG_DIS_RSDE        0x00004000UL    /* Disable Receiver Abort on RSD error */

#define SYS_CFG_FCS_INIT2F      0x00008000UL    /* initial seed value for the FCS generation and checking function */

/*offset 16 */

#define SYS_CFG_PHR_MODE_SHFT   16

#define SYS_CFG_PHR_MODE_00     0x00000000UL    /* Standard Frame mode */

#define SYS_CFG_PHR_MODE_11     0x00030000UL    /* Long Frames mode */

#define SYS_CFG_DIS_STXP        0x00040000UL    /* Disable Smart TX Power control */

#define SYS_CFG_RXM110K         0x00400000UL    /* Receiver Mode 110 kbps data rate */

/*offset 24 */

#define SYS_CFG_RXWTOE          0x10000000UL    /* Receive Wait Timeout Enable. */

#define SYS_CFG_RXAUTR          0x20000000UL    /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */

#define SYS_CFG_AUTOACK         0x40000000UL    /* Automatic Acknowledgement Enable */

#define SYS_CFG_AACKPEND        0x80000000UL    /* Automatic Acknowledgement Pending bit control */

/****************************************************************************//**

 * @brief Bit definitions for register SYS_TIME

**/

#define SYS_TIME_ID             0x06            /* System Time Counter (40-bit) */

#define SYS_TIME_OFFSET         0x00

#define SYS_TIME_LEN            (5)             /* Note 40 bit register */

/****************************************************************************//**

 * @brief Bit definitions for register  0x07

**/

#define REG_07_ID_RESERVED      0x07

/****************************************************************************//**

 * @brief Bit definitions for register TX_FCTRL

**/

#define TX_FCTRL_ID             0x08            /* Transmit Frame Control */

#define TX_FCTRL_LEN            (5)             /* Note 40 bit register */

/*masks (low 32 bit) */

#define TX_FCTRL_TFLEN_MASK     0x0000007FUL    /* bit mask to access Transmit Frame Length */

#define TX_FCTRL_TFLE_MASK      0x00000380UL    /* bit mask to access Transmit Frame Length Extension */

#define TX_FCTRL_FLE_MASK       0x000003FFUL    /* bit mask to access Frame Length field */

#define TX_FCTRL_TXBR_MASK      0x00006000UL    /* bit mask to access Transmit Bit Rate */

#define TX_FCTRL_TXPRF_MASK     0x00030000UL    /* bit mask to access Transmit Pulse Repetition Frequency */

#define TX_FCTRL_TXPSR_MASK     0x000C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */

#define TX_FCTRL_PE_MASK        0x00300000UL    /* bit mask to access Preamble Extension */

#define TX_FCTRL_TXPSR_PE_MASK  0x003C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */

#define TX_FCTRL_SAFE_MASK_32   0xFFFFE3FFUL    /* FSCTRL has fields which should always be writen zero */

/*offset 0 */

/*offset 8 */

#define TX_FCTRL_TXBR_110k      0x00000000UL    /* Transmit Bit Rate = 110k */

#define TX_FCTRL_TXBR_850k      0x00002000UL    /* Transmit Bit Rate = 850k */

#define TX_FCTRL_TXBR_6M        0x00004000UL    /* Transmit Bit Rate = 6.8M */

#define TX_FCTRL_TXBR_SHFT      (13)            /* shift to access Data Rate field */

#define TX_FCTRL_TR             0x00008000UL    /* Transmit Ranging enable */

#define TX_FCTRL_TR_SHFT        (15)            /* shift to access Ranging bit */

/*offset 16 */

#define TX_FCTRL_TXPRF_SHFT     (16)            /* shift to access Pulse Repetition Frequency field */

#define TX_FCTRL_TXPRF_4M       0x00000000UL    /* Transmit Pulse Repetition Frequency = 4 Mhz */

#define TX_FCTRL_TXPRF_16M      0x00010000UL    /* Transmit Pulse Repetition Frequency = 16 Mhz */

#define TX_FCTRL_TXPRF_64M      0x00020000UL    /* Transmit Pulse Repetition Frequency = 64 Mhz */

#define TX_FCTRL_TXPSR_SHFT     (18)            /* shift to access Preamble Symbol Repetitions field */

#define TX_FCTRL_PE_SHFT        (20)            /* shift to access Preamble length Extension to allow specification of non-standard values */

#define TX_FCTRL_TXPSR_PE_16    0x00000000UL    /* bit mask to access Preamble Extension = 16 */

#define TX_FCTRL_TXPSR_PE_64    0x00040000UL    /* bit mask to access Preamble Extension = 64 */

#define TX_FCTRL_TXPSR_PE_128   0x00140000UL    /* bit mask to access Preamble Extension = 128 */

#define TX_FCTRL_TXPSR_PE_256   0x00240000UL    /* bit mask to access Preamble Extension = 256 */

#define TX_FCTRL_TXPSR_PE_512   0x00340000UL    /* bit mask to access Preamble Extension = 512 */

#define TX_FCTRL_TXPSR_PE_1024  0x00080000UL    /* bit mask to access Preamble Extension = 1024 */

#define TX_FCTRL_TXPSR_PE_1536  0x00180000UL    /* bit mask to access Preamble Extension = 1536 */

#define TX_FCTRL_TXPSR_PE_2048  0x00280000UL    /* bit mask to access Preamble Extension = 2048 */

#define TX_FCTRL_TXPSR_PE_4096  0x000C0000UL    /* bit mask to access Preamble Extension = 4096 */

/*offset 22 */

#define TX_FCTRL_TXBOFFS_SHFT   (22)            /* Shift to access transmit buffer index offset */

#define TX_FCTRL_TXBOFFS_MASK   0xFFC00000UL    /* bit mask to access Transmit buffer index offset 10-bit field */

/*offset 32 */

#define TX_FCTRL_IFSDELAY_MASK  0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */

/****************************************************************************//**

 * @brief Bit definitions for register TX_BUFFER

**/

#define TX_BUFFER_ID            0x09            /* Transmit Data Buffer */

#define TX_BUFFER_LEN           (1024)

/****************************************************************************//**

 * @brief Bit definitions for register  DX_TIME

**/

#define DX_TIME_ID              0x0A            /* Delayed Send or Receive Time (40-bit) */

#define DX_TIME_LEN             (5)

/****************************************************************************//**

 * @brief Bit definitions for register 0x08

**/

#define REG_0B_ID_RESERVED      0x0B

/****************************************************************************//**

 * @brief Bit definitions for register RX_FWTO

**/

#define RX_FWTO_ID              0x0C            /* Receive Frame Wait Timeout Period */

#define RX_FWTO_OFFSET          0x00

#define RX_FWTO_LEN             (2)             /* doc bug*/

/*mask and shift */

#define RX_FWTO_MASK            0xFFFF

/****************************************************************************//**

 * @brief Bit definitions for register SYS_CTRL

**/

#define SYS_CTRL_ID             0x0D            /* System Control Register */

#define SYS_CTRL_OFFSET         0x00

#define SYS_CTRL_LEN            (4)

/*masks */

#define SYS_CTRL_MASK_32        0x010003CFUL    /* System Control Register access mask (all unused fields should always be writen as zero) */

/*offset 0 */

#define SYS_CTRL_SFCST          0x00000001UL    /* Suppress Auto-FCS Transmission (on this frame) */

#define SYS_CTRL_TXSTRT         0x00000002UL    /* Start Transmitting Now */

#define SYS_CTRL_TXDLYS         0x00000004UL    /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */

#define SYS_CTRL_CANSFCS        0x00000008UL    /* Cancel Suppression of auto-FCS transmission (on the current frame) */

#define SYS_CTRL_TRXOFF         0x00000040UL    /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */

#define SYS_CTRL_WAIT4RESP      0x00000080UL    /* Wait for Response */

/*offset 8 */

#define SYS_CTRL_RXENAB         0x00000100UL    /* Enable Receiver Now */

#define SYS_CTRL_RXDLYE         0x00000200UL    /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/

/*offset 16 */

/*offset 24 */

#define SYS_CTRL_HSRBTOGGLE     0x01000000UL    /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */

#define SYS_CTRL_HRBT           (SYS_CTRL_HSRBTOGGLE)

#define SYS_CTRL_HRBT_OFFSET    (3)

/****************************************************************************//**

 * @brief Bit definitions for register  SYS_MASK

**/

#define SYS_MASK_ID             0x0E            /* System Event Mask Register */

#define SYS_MASK_LEN            (4)

/*masks */

#define SYS_MASK_MASK_32        0x3FF7FFFEUL    /* System Event Mask Register access mask (all unused fields should always be writen as zero) */

/*offset 0 */

#define SYS_MASK_MCPLOCK        0x00000002UL    /* Mask clock PLL lock event    */

#define SYS_MASK_MESYNCR        0x00000004UL    /* Mask clock PLL lock event    */

#define SYS_MASK_MAAT           0x00000008UL    /* Mask automatic acknowledge trigger event */

#define SYS_MASK_MTXFRB         0x00000010UL    /* Mask transmit frame begins event */

#define SYS_MASK_MTXPRS         0x00000020UL    /* Mask transmit preamble sent event    */

#define SYS_MASK_MTXPHS         0x00000040UL    /* Mask transmit PHY Header Sent event  */

#define SYS_MASK_MTXFRS         0x00000080UL    /* Mask transmit frame sent event   */

/*offset 8 */

#define SYS_MASK_MRXPRD         0x00000100UL    /* Mask receiver preamble detected event    */

#define SYS_MASK_MRXSFDD        0x00000200UL    /* Mask receiver SFD detected event */

#define SYS_MASK_MLDEDONE       0x00000400UL    /* Mask LDE processing done event   */

#define SYS_MASK_MRXPHD         0x00000800UL    /* Mask receiver PHY header detect event    */

#define SYS_MASK_MRXPHE         0x00001000UL    /* Mask receiver PHY header error event */

#define SYS_MASK_MRXDFR         0x00002000UL    /* Mask receiver data frame ready event */

#define SYS_MASK_MRXFCG         0x00004000UL    /* Mask receiver FCS good event */

#define SYS_MASK_MRXFCE         0x00008000UL    /* Mask receiver FCS error event    */

/*offset 16 */

#define SYS_MASK_MRXRFSL        0x00010000UL    /* Mask receiver Reed Solomon Frame Sync Loss event */

#define SYS_MASK_MRXRFTO        0x00020000UL    /* Mask Receive Frame Wait Timeout event    */

#define SYS_MASK_MLDEERR        0x00040000UL    /* Mask leading edge detection processing error event   */

#define SYS_MASK_MRXOVRR        0x00100000UL    /* Mask Receiver Overrun event  */

#define SYS_MASK_MRXPTO         0x00200000UL    /* Mask Preamble detection timeout event    */

#define SYS_MASK_MGPIOIRQ       0x00400000UL    /* Mask GPIO interrupt event    */

#define SYS_MASK_MSLP2INIT      0x00800000UL    /* Mask SLEEP to INIT event */

/*offset 24*/

#define SYS_MASK_MRFPLLLL       0x01000000UL    /* Mask RF PLL Loosing Lock warning event   */

#define SYS_MASK_MCPLLLL        0x02000000UL    /* Mask Clock PLL Loosing Lock warning event    */

#define SYS_MASK_MRXSFDTO       0x04000000UL    /* Mask Receive SFD timeout event   */

#define SYS_MASK_MHPDWARN       0x08000000UL    /* Mask Half Period Delay Warning event */

#define SYS_MASK_MTXBERR        0x10000000UL    /* Mask Transmit Buffer Error event */

#define SYS_MASK_MAFFREJ        0x20000000UL    /* Mask Automatic Frame Filtering rejection event   */

/****************************************************************************//**

 * @brief Bit definitions for register SYS_STATUS

**/

#define SYS_STATUS_ID           0x0F            /* System event Status Register */

#define SYS_STATUS_OFFSET       0x00

#define SYS_STATUS_LEN          (5)             /* Note 40 bit register */

/*masks */

#define SYS_STATUS_MASK_32      0xFFF7FFFFUL    /* System event Status Register access mask (all unused fields should always be writen as zero) */

/*offset 0 */

#define SYS_STATUS_IRQS         0x00000001UL    /* Interrupt Request Status READ ONLY */

#define SYS_STATUS_CPLOCK       0x00000002UL    /* Clock PLL Lock */

#define SYS_STATUS_ESYNCR       0x00000004UL    /* External Sync Clock Reset */

#define SYS_STATUS_AAT          0x00000008UL    /* Automatic Acknowledge Trigger */

#define SYS_STATUS_TXFRB        0x00000010UL    /* Transmit Frame Begins */

#define SYS_STATUS_TXPRS        0x00000020UL    /* Transmit Preamble Sent */

#define SYS_STATUS_TXPHS        0x00000040UL    /* Transmit PHY Header Sent */

#define SYS_STATUS_TXFRS        0x00000080UL    /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */

/*offset 8 */

#define SYS_STATUS_RXPRD        0x00000100UL    /* Receiver Preamble Detected status */

#define SYS_STATUS_RXSFDD       0x00000200UL    /* Receiver Start Frame Delimiter Detected. */

#define SYS_STATUS_LDEDONE      0x00000400UL    /* LDE processing done */

#define SYS_STATUS_RXPHD        0x00000800UL    /* Receiver PHY Header Detect */

#define SYS_STATUS_RXPHE        0x00001000UL    /* Receiver PHY Header Error */

#define SYS_STATUS_RXDFR        0x00002000UL    /* Receiver Data Frame Ready */

#define SYS_STATUS_RXFCG        0x00004000UL    /* Receiver FCS Good */

#define SYS_STATUS_RXFCE        0x00008000UL    /* Receiver FCS Error */

/*offset 16 */

#define SYS_STATUS_RXRFSL       0x00010000UL    /* Receiver Reed Solomon Frame Sync Loss */

#define SYS_STATUS_RXRFTO       0x00020000UL    /* Receive Frame Wait Timeout */

#define SYS_STATUS_LDEERR       0x00040000UL    /* Leading edge detection processing error */

#define SYS_STATUS_reserved     0x00080000UL    /* bit19 reserved */

#define SYS_STATUS_RXOVRR       0x00100000UL    /* Receiver Overrun */

#define SYS_STATUS_RXPTO        0x00200000UL    /* Preamble detection timeout */

#define SYS_STATUS_GPIOIRQ      0x00400000UL    /* GPIO interrupt */

#define SYS_STATUS_SLP2INIT     0x00800000UL    /* SLEEP to INIT */

/*offset 24 */

#define SYS_STATUS_RFPLL_LL     0x01000000UL    /* RF PLL Losing Lock */

#define SYS_STATUS_CLKPLL_LL    0x02000000UL    /* Clock PLL Losing Lock */

#define SYS_STATUS_RXSFDTO      0x04000000UL    /* Receive SFD timeout */

#define SYS_STATUS_HPDWARN      0x08000000UL    /* Half Period Delay Warning */

#define SYS_STATUS_TXBERR       0x10000000UL    /* Transmit Buffer Error */

#define SYS_STATUS_AFFREJ       0x20000000UL    /* Automatic Frame Filtering rejection */

#define SYS_STATUS_HSRBP        0x40000000UL    /* Host Side Receive Buffer Pointer */

#define SYS_STATUS_ICRBP        0x80000000UL    /* IC side Receive Buffer Pointer READ ONLY */

/*offset 32 */

#define SYS_STATUS_RXRSCS       0x0100000000ULL /* Receiver Reed-Solomon Correction Status */

#define SYS_STATUS_RXPREJ       0x0200000000ULL /* Receiver Preamble Rejection */

#define SYS_STATUS_TXPUTE       0x0400000000ULL /* Transmit power up time error */

#define SYS_STATUS_TXERR        (0x0408)        /* These bits are the 16 high bits of status register TXPUTE and HPDWARN flags */

/* All RX events after a correct packet reception mask. */

#define SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG | SYS_STATUS_RXPRD | \

                                SYS_STATUS_RXSFDD | SYS_STATUS_RXPHD | SYS_STATUS_LDEDONE)

/* All double buffer events mask. */

#define SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG)

/* All RX errors mask. */

#define SYS_STATUS_ALL_RX_ERR  (SYS_STATUS_RXPHE | SYS_STATUS_RXFCE | SYS_STATUS_RXRFSL | SYS_STATUS_RXSFDTO \

                                | SYS_STATUS_AFFREJ | SYS_STATUS_LDEERR)

/* User defined RX timeouts (frame wait timeout and preamble detect timeout) mask. */

#define SYS_STATUS_ALL_RX_TO   (SYS_STATUS_RXRFTO | SYS_STATUS_RXPTO)

/* All TX events mask. */

#define SYS_STATUS_ALL_TX      (SYS_STATUS_AAT | SYS_STATUS_TXFRB | SYS_STATUS_TXPRS | \

                                SYS_STATUS_TXPHS | SYS_STATUS_TXFRS )

/****************************************************************************//**

 * @brief Bit definitions for register RX_FINFO

**/

#define RX_FINFO_ID             0x10            /* RX Frame Information (in double buffer set) */

#define RX_FINFO_OFFSET         0x00

#define RX_FINFO_LEN            (4)

/*mask and shift */

#define RX_FINFO_MASK_32        0xFFFFFBFFUL    /* System event Status Register access mask (all unused fields should always be writen as zero) */

#define RX_FINFO_RXFLEN_MASK    0x0000007FUL    /* Receive Frame Length (0 to 127) */

#define RX_FINFO_RXFLE_MASK     0x00000380UL    /* Receive Frame Length Extension (0 to 7)<<7 */

#define RX_FINFO_RXFL_MASK_1023 0x000003FFUL    /* Receive Frame Length Extension (0 to 1023) */

#define RX_FINFO_RXNSPL_MASK    0x00001800UL    /* Receive Non-Standard Preamble Length */

#define RX_FINFO_RXPSR_MASK     0x000C0000UL    /* RX Preamble Repetition. 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols */

#define RX_FINFO_RXPEL_MASK     0x000C1800UL    /* Receive Preamble Length = RXPSR+RXNSPL */

#define RX_FINFO_RXPEL_64       0x00040000UL    /* Receive Preamble length = 64 */

#define RX_FINFO_RXPEL_128      0x00040800UL    /* Receive Preamble length = 128 */

#define RX_FINFO_RXPEL_256      0x00041000UL    /* Receive Preamble length = 256 */

#define RX_FINFO_RXPEL_512      0x00041800UL    /* Receive Preamble length = 512 */

#define RX_FINFO_RXPEL_1024     0x00080000UL    /* Receive Preamble length = 1024 */

#define RX_FINFO_RXPEL_1536     0x00080800UL    /* Receive Preamble length = 1536 */

#define RX_FINFO_RXPEL_2048     0x00081000UL    /* Receive Preamble length = 2048 */

#define RX_FINFO_RXPEL_4096     0x000C0000UL    /* Receive Preamble length = 4096 */

#define RX_FINFO_RXBR_MASK      0x00006000UL    /* Receive Bit Rate report. This field reports the received bit rate */

#define RX_FINFO_RXBR_110k      0x00000000UL    /* Received bit rate = 110 kbps */

#define RX_FINFO_RXBR_850k      0x00002000UL    /* Received bit rate = 850 kbps */

#define RX_FINFO_RXBR_6M        0x00004000UL    /* Received bit rate = 6.8 Mbps */

#define RX_FINFO_RXBR_SHIFT     (13)

#define RX_FINFO_RNG            0x00008000UL    /* Receiver Ranging. Ranging bit in the received PHY header identifying the frame as a ranging packet. */

#define RX_FINFO_RNG_SHIFT      (15)

#define RX_FINFO_RXPRF_MASK     0x00030000UL    /* RX Pulse Repetition Rate report */

#define RX_FINFO_RXPRF_16M      0x00010000UL    /* PRF being employed in the receiver = 16M */

#define RX_FINFO_RXPRF_64M      0x00020000UL    /* PRF being employed in the receiver = 64M */

#define RX_FINFO_RXPRF_SHIFT    (16)

#define RX_FINFO_RXPACC_MASK    0xFFF00000UL    /* Preamble Accumulation Count */

#define RX_FINFO_RXPACC_SHIFT   (20)

/****************************************************************************//**

 * @brief Bit definitions for register RX_BUFFER

**/

#define RX_BUFFER_ID            0x11            /* Receive Data Buffer (in double buffer set) */

#define RX_BUFFER_LEN           (1024)

/****************************************************************************//**

 * @brief Bit definitions for register RX_FQUAL

**/

#define RX_FQUAL_ID             0x12            /* Rx Frame Quality information (in double buffer set) */

#define RX_FQUAL_LEN            (8)             /* note 64 bit register*/

/*mask and shift */

/*offset 0 */

#define RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL   /* Standard Deviation of Noise */

#define RX_EQUAL_STD_NOISE_SHIFT (0)

#define STD_NOISE_MASK          RX_EQUAL_STD_NOISE_MASK

#define STD_NOISE_SHIFT         RX_EQUAL_STD_NOISE_SHIFT

/*offset 16 */

#define RX_EQUAL_FP_AMPL2_MASK  0xFFFF0000ULL   /* First Path Amplitude point 2 */

#define RX_EQUAL_FP_AMPL2_SHIFT (16)

#define FP_AMPL2_MASK           RX_EQUAL_FP_AMPL2_MASK

#define FP_AMPL2_SHIFT          RX_EQUAL_FP_AMPL2_SHIFT

/*offset 32*/

#define RX_EQUAL_PP_AMPL3_MASK  0x0000FFFF00000000ULL   /* First Path Amplitude point 3 */

#define RX_EQUAL_PP_AMPL3_SHIFT (32)