Revision 7df78c60

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include/AT42QT1050/v1/alld_AT42QT1050_v1.h
250 250
  float at42qt1050_lld_samples2pulse(const uint16_t samples);
251 251
  uint16_t at42qt1050_lld_scale2scaling(const uint8_t scale);
252 252
  float at42qt1050_lld_scaling2scale(const uint16_t factor);
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  /**
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   * @brief   Calculates n-th address based on address of register 0.
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   * @details Calculation: <scale value> = log2(<scaling factor>
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   * )
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   * @param[in]   base    Base address = frist register
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   * @param[in]   inc     Jump to the next register inc times
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   *
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   * @return    Calculated register address
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   */
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  inline at42qt1050_lld_register_t at42qt1050_lld_addr_calc(const at42qt1050_lld_register_t base, const uint8_t inc) {
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    apalDbgAssert(inc < 5);
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    uint8_t double_result = 0; //16bit access
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    switch (base) {
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      case AT42QT1050_LLD_REG_KEYSIGNAL_0:         //2 4 2 2
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      case AT42QT1050_LLD_REG_REFERENCEDATA_0:     //2 4 2 2
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        double_result = 1;
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      case AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_0: //1 2 1 1
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      case AT42QT1050_LLD_REG_PULSE_SCALE_0:       //1 2 1 1
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      case AT42QT1050_LLD_REG_INTEGRATOR_AKS_0:    //1 2 1 1
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      case AT42QT1050_LLD_REG_CHARGESHAREDELAY_0:  //1 2 1 1
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      {
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        uint8_t increase = ((inc>1)?inc+1:inc);
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        return (at42qt1050_lld_register_t) (((uint8_t) base)+(increase << double_result));
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      }
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      default:
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      {
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        apalDbgPrintf("invalid base register 0x%04X\n", base);
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        return (at42qt1050_lld_register_t) 0xFF; //does not exist
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      }
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    }
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  }
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#ifdef __cplusplus
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}
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#endif
source/AT42QT1050/v1/alld_AT42QT1050_v1.c
109 109
  apalDbgAssert(key < AT42QT1050_LLD_NUM_KEYS);
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  apalDbgAssert(signal != NULL);
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  const uint8_t txbuf = AT42QT1050_LLD_REG_KEYSIGNAL_0 + (2*key) + ((key > 1) ? 2 : 0);
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  const at42qt1050_lld_register_t txbuf = at42qt1050_lld_addr_calc(AT42QT1050_LLD_REG_KEYSIGNAL_0, key);
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  uint8_t rxbuf[2];
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  const apalExitStatus_t status = apalI2CMasterTransmit(at42qt1050d->i2cd, at42qt1050d->addr, &txbuf, 1, rxbuf, 2, timeout);
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  *signal = (rxbuf[0] << 8) | rxbuf[1];
......
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  apalDbgAssert(key < AT42QT1050_LLD_NUM_KEYS);
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  apalDbgAssert(refdata != NULL);
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  const uint8_t txbuf = AT42QT1050_LLD_REG_REFERENCEDATA_0 + (2*key) + ((key > 1) ? 2 : 0);
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  const at42qt1050_lld_register_t txbuf = at42qt1050_lld_addr_calc(AT42QT1050_LLD_REG_REFERENCEDATA_0, key);
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  uint8_t rxbuf[2];
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  const apalExitStatus_t status = apalI2CMasterTransmit(at42qt1050d->i2cd, at42qt1050d->addr, &txbuf, 1, rxbuf, 2, timeout);
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  *refdata = (rxbuf[0] << 8) | rxbuf[1];
......
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  apalDbgAssert(at42qt1050d != NULL && at42qt1050d->i2cd != NULL);
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  const apalExitStatus_t status = at42qt1050_lld_write_reg(
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	at42qt1050d, AT42QT1050_LLD_RESETCALIBRATE_RESET, AT42QT1050_LLD_RESETCALIBRATE_RESET, timeout);
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    at42qt1050d, AT42QT1050_LLD_REG_RESET_CALIBRATE, AT42QT1050_LLD_RESETCALIBRATE_RESET, timeout);
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  if(wait4wakeup)
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	usleep(AT42QT1050_LLD_WATCHDOGTIME_MAX+AT42QT1050_LLD_INITIALIZATION_TIME_MAX); // watchdog timer+initialization -> datasheet
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    usleep(AT42QT1050_LLD_WATCHDOGTIME_MAX+AT42QT1050_LLD_INITIALIZATION_TIME_MAX+timeout); // watchdog timer+initialization -> datasheet
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  return status;
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}
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