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amiro-lld / include / AT42QT1050 / v1 / alld_AT42QT1050_v1.h @ 7df78c60

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/*
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AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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 * @file    alld_AT42QT1050_v1.h
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 * @brief   Touch sensor macros and structures.
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 *
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 * @addtogroup lld_touch
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 * @{
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 */
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#ifndef AMIROLLD_AT42QT1050_V1_H
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#define AMIROLLD_AT42QT1050_V1_H
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#include <amiro-lld.h>
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#if (defined(AMIROLLD_CFG_AT42QT1050) && (AMIROLLD_CFG_AT42QT1050 == 1)) || defined(__DOXYGEN__)
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/******************************************************************************/
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/* CONSTANTS                                                                  */
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/******************************************************************************/
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/**
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 * @brief   Maximum I2C frequency.
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 */
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#define AT42QT1050_LLD_I2C_MAXFREQUENCY         400000
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/**
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 * @brief   A falling edge indicats an interrupt.
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 */
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#define AT42QT1050_LLD_INT_EDGE                 APAL_GPIO_EDGE_FALLING
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/**
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 * @brief   Number of touch keys supported by AT42QT1050.
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 */
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#define AT42QT1050_LLD_NUM_KEYS                 5
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/**
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 * @brief   Maximum time (in microseconds) to acquire all key signals before the overflow bit of the detection status register is set.
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 */
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#define AT42QT1050_LLD_MAX_KEY_ACQUIRATION_TIME 8000
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/**
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 * @brief   The chip ID as can be read from the according register (constant).
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 */
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#define AT42QT1050_LLD_CHIPID                   0x46
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/******************************************************************************/
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/* SETTINGS                                                                   */
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/******************************************************************************/
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/******************************************************************************/
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/* CHECKS                                                                     */
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/******************************************************************************/
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/******************************************************************************/
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/* DATA STRUCTURES AND TYPES                                                  */
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/******************************************************************************/
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/**
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 * @brief   The AT42QT1050Driver sruct.
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 */
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typedef struct {
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  apalI2CDriver_t* i2cd;
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  apalI2Caddr_t addr;
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} AT42QT1050Driver;
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/**
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 * @brief   Possible I2C address configurations.
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 */
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enum {
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  AT42QT1050_LLD_I2C_ADDRSEL_LOW  = 0x0041u,  /**< ADDR_SEL pin is pulled low. */
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  AT42QT1050_LLD_I2C_ADDRSEL_HIGH = 0x0046u,  /**< ADDR_SEL pin is pulled high. */
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};
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/**
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 * @brief   Available register addresses of the AT42Q1050.
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 */
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typedef enum {
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  AT42QT1050_LLD_REG_CHIPID               = 0x00u,  /**<  read only */
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  AT42QT1050_LLD_REG_FIRMWAREVERSION      = 0x01u,  /**<  read only */
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  AT42QT1050_LLD_REG_DETECTIONSTATUS      = 0x02u,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSTATUS            = 0x03u,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSIGNAL_0          = 0x06u,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSIGNAL_1          = 0x08u,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSIGNAL_2          = 0x0Du,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSIGNAL_3          = 0x0Fu,  /**<  read only */
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  AT42QT1050_LLD_REG_KEYSIGNAL_4          = 0x11u,  /**<  read only */
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  AT42QT1050_LLD_REG_REFERENCEDATA_0      = 0x14u,  /**<  read only */
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  AT42QT1050_LLD_REG_REFERENCEDATA_1      = 0x16u,  /**<  read only */
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  AT42QT1050_LLD_REG_REFERENCEDATA_2      = 0x1Au,  /**<  read only */
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  AT42QT1050_LLD_REG_REFERENCEDATA_3      = 0x1Cu,  /**<  read only */
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  AT42QT1050_LLD_REG_REFERENCEDATA_4      = 0x1Eu,  /**<  read only */
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  AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_0  = 0x21u,  /**< read/write */
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  AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_1  = 0x22u,  /**< read/write */
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  AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_2  = 0x24u,  /**< read/write */
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  AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_3  = 0x25u,  /**< read/write */
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  AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_4  = 0x26u,  /**< read/write */
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  AT42QT1050_LLD_REG_PULSE_SCALE_0        = 0x28u,  /**< read/write */
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  AT42QT1050_LLD_REG_PULSE_SCALE_1        = 0x29u,  /**< read/write */
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  AT42QT1050_LLD_REG_PULSE_SCALE_2        = 0x2Bu,  /**< read/write */
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  AT42QT1050_LLD_REG_PULSE_SCALE_3        = 0x2Cu,  /**< read/write */
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  AT42QT1050_LLD_REG_PULSE_SCALE_4        = 0x2Du,  /**< read/write */
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  AT42QT1050_LLD_REG_INTEGRATOR_AKS_0     = 0x2Fu,  /**< read/write */
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  AT42QT1050_LLD_REG_INTEGRATOR_AKS_1     = 0x30u,  /**< read/write */
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  AT42QT1050_LLD_REG_INTEGRATOR_AKS_2     = 0x32u,  /**< read/write */
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  AT42QT1050_LLD_REG_INTEGRATOR_AKS_3     = 0x33u,  /**< read/write */
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  AT42QT1050_LLD_REG_INTEGRATOR_AKS_4     = 0x34u,  /**< read/write */
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  AT42QT1050_LLD_REG_CHARGESHAREDELAY_0   = 0x36u,  /**< read/write */
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  AT42QT1050_LLD_REG_CHARGESHAREDELAY_1   = 0x37u,  /**< read/write */
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  AT42QT1050_LLD_REG_CHARGESHAREDELAY_2   = 0x39u,  /**< read/write */
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  AT42QT1050_LLD_REG_CHARGESHAREDELAY_3   = 0x3Au,  /**< read/write */
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  AT42QT1050_LLD_REG_CHARGESHAREDELAY_4   = 0x3Bu,  /**< read/write */
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  AT42QT1050_LLD_REG_FINFOUTMAXCALGUARD   = 0x3Cu,  /**< read/write */
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  AT42QT1050_LLD_REG_LOWPOWERMODE         = 0x3Du,  /**< read/write */
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  AT42QT1050_LLD_REG_MAXONDURATION        = 0x3Eu,  /**< read/write */
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  AT42QT1050_LLD_REG_RESET_CALIBRATE      = 0x3Fu,  /**< read/write */
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} at42qt1050_lld_register_t;
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/**
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 * @brief   Firmware version register structure.
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 */
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typedef union {
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  uint8_t raw;
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  struct {
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    uint8_t minor : 4;
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    uint8_t major : 4;
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  };
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} at42qt1050_lld_firmwarereg_t;
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/**
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 * @brief   Relevant bits of the detection status register.
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 */
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typedef enum {
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  AT42QT1050_LLD_DETECTIONSTATUS_TOUCH      = 0x01u,  /**< Set if any keys are in detect.  */
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  AT42QT1050_LLD_DETECTIONSTATUS_OVERFLOW   = 0x40u,  /**< Set if the time to acquire all key signals exceeds 8ms. */
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  AT42QT1050_LLD_DETECTIONSTATUS_CALIBRATE  = 0x80u,  /**< Set during calibration sequence. */
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} at42q1050_lld_detectionstatusreg_t;
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/**
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 * @brief   Key status register masks.
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 */
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typedef enum {
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  AT42QT1050_LLD_KEYSTATUS_KEY0 = 0x02u,
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  AT42QT1050_LLD_KEYSTATUS_KEY1 = 0x04u,
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  AT42QT1050_LLD_KEYSTATUS_KEY2 = 0x10u,
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  AT42QT1050_LLD_KEYSTATUS_KEY3 = 0x20u,
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  AT42QT1050_LLD_KEYSTATUS_KEY4 = 0x40u,
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} at42qt1050_lld_keystatusreg_t;
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/**
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 * @brief   Pulse/Scale register structure.
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 */
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typedef union {
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  uint8_t raw;
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  struct {
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    uint8_t scale : 4;
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    uint8_t pulse : 4;
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  };
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} at42qt1050_lld_pulsescalereg_t;
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/**
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 * @brief   Detection Integrator (DI) / AKS register structure.
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 */
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typedef union {
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  uint8_t raw;
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  struct {
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    uint8_t aks : 2;
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    uint8_t detection_integrator : 6;
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  };
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} at42qt1050_lld_detectionintegratoraksreg_t;
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/**
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 * @brief   Charge share delay constant sclaing factor.
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 * @details Values in the charge share delay registers are multiplied by this factor.
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 *          Unit is microseconds (µs).
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 */
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#define AT42QT1050_LLD_CHARGESHAREDELAY_FACTOR  2.5f
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/**
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 * @brief   FastIn / FastOutDI / Max Cal / Guard Channel register masks.
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 */
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typedef enum {
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  AT42QT1050_LLD_FINFOUTMAXCALGUARD_GUARD   = 0x0Fu,
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  AT42QT1050_LLD_FINFOUTMAXCALGUARD_MAXCAL  = 0x10u,
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  AT42QT1050_LLD_FINFOUTMAXCALGUARD_FO      = 0x20u,
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  AT42QT1050_LLD_FINFOUTMAXCALGUARD_FI      = 0x40u,
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} at42qt1050_lld_finfoutmaxcalguardreg_t;
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/**
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 * @brief   Low power mode constant scaling factor.
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 * @details The values in the low poer mode register is multiplied by this factor.
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 *          Unit is microseconds (µs).
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 * @note    Setting the power mode scaling register value to zero makes the AT42QT1050 enter deep-sleep mode.
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 */
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#define AT42QT1050_LLD_LOWPOWER_FACTOR          8000
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/**
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 * @brief   Man on duration constant scaling factor.
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 * @details The value in the max on duration register is multiplied by this factor.
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 *          Unit is microseconds (µs).
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 */
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#define AT42QT1050_LLD_MAXONDURATION_FACTOR     160000
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/**
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 * @brief   RESET / Calibrate register masks.
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 */
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typedef enum {
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  AT42QT1050_LLD_RESETCALIBRATE_CALIBRATE = 0x7Fu,
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  AT42QT1050_LLD_RESETCALIBRATE_RESET     = 0x80u,
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} at42qt1050_lld_resetcalibratereg_t;
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/******************************************************************************/
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/* MACROS                                                                     */
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/******************************************************************************/
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/******************************************************************************/
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/* EXTERN DECLARATIONS                                                        */
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/******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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  apalExitStatus_t at42qt1050_lld_read_reg(const AT42QT1050Driver* at42qt1050d, const at42qt1050_lld_register_t reg, uint8_t* const data, const apalTime_t timeout);
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  apalExitStatus_t at42qt1050_lld_write_reg(const AT42QT1050Driver* at42qt1050d, const at42qt1050_lld_register_t reg, const uint8_t data, const apalTime_t timeout);
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  apalExitStatus_t at42qt1050_lld_read_keyssignal(const AT42QT1050Driver* at42qt1050d, const uint8_t key, uint16_t* signal, const apalTime_t timeout);
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  apalExitStatus_t at42qt1050_lld_read_referencedata(const AT42QT1050Driver* at42qt1050d, const uint8_t key, uint16_t* refdata, const apalTime_t timeout);
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  apalExitStatus_t at42qt1050_lld_reset_safe(const AT42QT1050Driver* at42qt1050d, const bool wait4wakeup, const apalTime_t timeout);
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  apalExitStatus_t at42qt1050_lld_reset(const AT42QT1050Driver* at42qt1050d, const apalTime_t timeout, const bool wait4wakeup);
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  uint16_t at42qt1050_lld_pulse2samples(const uint8_t pulse);
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  float at42qt1050_lld_samples2pulse(const uint16_t samples);
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  uint16_t at42qt1050_lld_scale2scaling(const uint8_t scale);
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  float at42qt1050_lld_scaling2scale(const uint16_t factor);
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  /**
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   * @brief   Calculates n-th address based on address of register 0.
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   * @details Calculation: <scale value> = log2(<scaling factor>
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   * )
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   * @param[in]   base    Base address = frist register
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   * @param[in]   inc     Jump to the next register inc times
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   *
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   * @return    Calculated register address
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   */
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  inline at42qt1050_lld_register_t at42qt1050_lld_addr_calc(const at42qt1050_lld_register_t base, const uint8_t inc) {
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    apalDbgAssert(inc < 5);
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    uint8_t double_result = 0; //16bit access
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    switch (base) {
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      case AT42QT1050_LLD_REG_KEYSIGNAL_0:         //2 4 2 2
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      case AT42QT1050_LLD_REG_REFERENCEDATA_0:     //2 4 2 2
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        double_result = 1;
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      case AT42QT1050_LLD_REG_NEGATIVETHRESHOLD_0: //1 2 1 1
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      case AT42QT1050_LLD_REG_PULSE_SCALE_0:       //1 2 1 1
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      case AT42QT1050_LLD_REG_INTEGRATOR_AKS_0:    //1 2 1 1
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      case AT42QT1050_LLD_REG_CHARGESHAREDELAY_0:  //1 2 1 1
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      {
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        uint8_t increase = ((inc>1)?inc+1:inc);
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        return (at42qt1050_lld_register_t) (((uint8_t) base)+(increase << double_result));
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      }
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      default:
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      {
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        apalDbgPrintf("invalid base register 0x%04X\n", base);
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        return (at42qt1050_lld_register_t) 0xFF; //does not exist
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      }
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    }
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  }
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#ifdef __cplusplus
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}
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#endif
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/******************************************************************************/
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/* INLINE FUNCTIONS                                                           */
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/******************************************************************************/
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#endif /* defined(AMIROLLD_CFG_AT42QT1050) && (AMIROLLD_CFG_AT42QT1050 == 1) */
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#endif /* AMIROLLD_AT42QT1050_V1_H */
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/** @} */