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amiro-lld / include / alld_pcal6524.h @ 8c47f14b

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1 e3287406 Thomas Schöpping
/*
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AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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 * @file    alld_pcal6524.h
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 * @brief   GPIO extender macros and structures.
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 *
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 * @addtogroup lld_gpioext
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 * @{
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 */
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#ifndef AMIROLLD_PCAL6524_H
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#define AMIROLLD_PCAL6524_H
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#include <amiro-lld.h>
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#if defined(AMIROLLD_CFG_USE_PCAL6524) || defined(__DOXYGEN__)
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/**
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 * @brief   Maximum I2C frequency.
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 */
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#define PCAL6524_LLD_I2C_MAXFREQUENCY           1000000
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/**
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 * @brief   A falling edge indicats an interrupt.
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 */
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#define PCAL6524_LLD_INT_EDGE                   APAL_GPIO_EDGE_FALLING
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/**
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 * @brief   The PCAL6524Driver sruct.
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 */
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typedef struct {
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  apalI2CDriver_t* i2cd;
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  apalI2Caddr_t addr;
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} PCAL6524Driver;
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/**
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 * @brief   Possible I2C address configurations.
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 */
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enum {
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  PCAL6524_LLD_I2C_ADDR_FIXED     = 0x0020u,  /**< Fixed part of the I2C address. */
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  PCAL6524_LLD_I2C_ADDR_SCL       = 0x0020u,  /**< ADDR pin connected to SCL. */
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  PCAL6524_LLD_I2C_ADDR_SDA       = 0x0021u,  /**< ADDR pin connected to SDA. */
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  PCAL6524_LLD_I2C_ADDR_VSS       = 0x0022u,  /**< ADDR pin connected to VSS. */
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  PCAL6524_LLD_I2C_ADDR_VDD       = 0x0023u,  /**< ADDR pin connected to VDD. */
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  PCAL6524_LLD_I2C_ADDR_DEVICEID  = 0x007Cu,  /**< Special address to read device ID information. */
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};
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/**
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 * @brief   Command bit to enable auto-incrementation of command value.
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 * @details Can be added (ORed) to any command value.
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 */
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#define PCAL6524_LLD_CMD_AUTOINCREMENT          0x80u
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/**
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 * @brief   The total number of registers that can be accessed.
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 * @note    This is the maximum number of bytes that may be read or written continuously.
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 */
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#define PCAL6524_LLD_NUM_REGISTERS              52
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typedef union {
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  uint8_t raw[3];
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  struct {
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    uint16_t name : 12;
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    uint16_t part : 9;
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    uint8_t revision : 3;
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  };
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} pcal6524_lld_deviceid_t;
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/**
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 * @brief   Control commands for the PCAL6524.
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 */
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typedef enum {
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  PCAL6524_LLD_CMD_INPUT_P0                             = 0x00u,  /**<  read only */
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  PCAL6524_LLD_CMD_INPUT_P1                             = 0x01u,  /**<  read only */
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  PCAL6524_LLD_CMD_INPUT_P2                             = 0x02u,  /**<  read only */
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  PCAL6524_LLD_CMD_OUTPUT_P0                            = 0x04u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUT_P1                            = 0x05u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUT_P2                            = 0x06u,  /**< read/write */
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  PCAL6524_LLD_CMD_POLARITYINVERSION_P0                 = 0x08u,  /**< read/write */
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  PCAL6524_LLD_CMD_POLARITYINVERSION_P1                 = 0x09u,  /**< read/write */
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  PCAL6524_LLD_CMD_POLARITYINVERSION_P2                 = 0x0Au,  /**< read/write */
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  PCAL6524_LLD_CMD_CONFIGURATION_P0                     = 0x0Cu,  /**< read/write */
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  PCAL6524_LLD_CMD_CONFIGURATION_P1                     = 0x0Du,  /**< read/write */
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  PCAL6524_LLD_CMD_CONFIGURATION_P2                     = 0x0Eu,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0A              = 0x40u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0B              = 0x41u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1A              = 0x42u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1B              = 0x43u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2A              = 0x44u,  /**< read/write */
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  PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2B              = 0x45u,  /**< read/write */
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  PCAL6524_LLD_CMD_INPUTLATCH_P0                        = 0x48u,  /**< read/write */
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  PCAL6524_LLD_CMD_INPUTLATCH_P1                        = 0x49u,  /**< read/write */
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  PCAL6524_LLD_CMD_INPUTLATCH_P2                        = 0x4Au,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDENABLE_P0                        = 0x4Cu,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDENABLE_P1                        = 0x4Du,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDENABLE_P2                        = 0x4Eu,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDSELECTION_P0                     = 0x50u,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDSELECTION_P1                     = 0x51u,  /**< read/write */
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  PCAL6524_LLD_CMD_PUPDSELECTION_P2                     = 0x52u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTMASK_P0                     = 0x54u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTMASK_P1                     = 0x55u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTMASK_P2                     = 0x56u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTSTATUS_P0                   = 0x58u,  /**<  read only */
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  PCAL6524_LLD_CMD_INTERRUPTSTATUS_P1                   = 0x59u,  /**<  read only */
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  PCAL6524_LLD_CMD_INTERRUPTSTATUS_P2                   = 0x5Au,  /**<  read only */
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  PCAL6524_LLD_CMD_OUTPUTCONFIGURATION                  = 0x5Cu,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P0A                    = 0x60u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P0B                    = 0x61u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P1A                    = 0x62u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P1B                    = 0x63u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P2A                    = 0x64u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTEDGE_P2B                    = 0x65u,  /**< read/write */
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  PCAL6524_LLD_CMD_INTERRUPTCLEAR_P0                    = 0x68u,  /**< write only */
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  PCAL6524_LLD_CMD_INTERRUPTCLEAR_P1                    = 0x69u,  /**< write only */
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  PCAL6524_LLD_CMD_INTERRUPTCLEAR_P2                    = 0x6Au,  /**< write only */
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  PCAL6524_LLD_CMD_INPUTSTATUS_P0                       = 0x6Cu,  /**<  read only */
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  PCAL6524_LLD_CMD_INPUTSTATUS_P1                       = 0x6Du,  /**<  read only */
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  PCAL6524_LLD_CMD_INPUTSTATUS_P2                       = 0x6Eu,  /**<  read only */
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  PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P0  = 0x70u,  /**< read/write */
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  PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P1  = 0x71u,  /**< read/write */
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  PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P2  = 0x72u,  /**< read/write */
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  PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P0              = 0x74u,  /**< read/write */
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  PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P1              = 0x75u,  /**< read/write */
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  PCAL6524_LLD_CMD_SWITCHDEBOUNCECOUNT                  = 0x76u,  /**< read/write */
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} pcal6524_lld_cmd_t;
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/**
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 * @brief   Input register bit values.
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 * @details The bits in the input register reflect the incoming logic levels per pin.
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 *          If a pin is configured as ouput, the bit reflects th set value or is forced to 0 in case the outpus is configured as open-drain.
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 *          If a pin is configured as input with latched interrupts, reading the according port will reset the input value and clear the interrupt.
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 */
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typedef enum {
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  PCAL6524_LLD_INPUT_LOW  = 0b0,
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  PCAL6524_LLD_INPUT_HIGH = 0b1,
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} pcal6524_lld_input_t;
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/**
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 * @brief   Output register bit values.
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 * @details Defines the logic level to be driven by output pins.
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 *          The default value (after reset) is 0b1 (high),
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 */
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typedef enum {
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  PCAL6524_LLD_OUTPUT_LOW     = 0b0,
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  PCAL6524_LLD_OUTPUT_HIGH    = 0b1,
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} pcal6524_lld_output_t;
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/**
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 * @brief   Polarity inversion register values.
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 * @details Allows to inverse the logic values written to the input register.
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 *          The default value (after reset) is 0b0 (disabled).
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 */
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typedef enum {
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  PCAL6524_LLD_POLARITYINVERSION_DISABLED = 0b0,
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  PCAL6524_LLD_POLARITYINVERSION_ENABLED  = 0b1,
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} pcal6524_lld_polarityinversion_t;
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/**
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 * @brief   Configuration regsiter bit values.
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 * @details Configures the direction of the I/O pins to either high-impedance input or output.
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 *          The default value (after reset) is 0b1 (input).
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 */
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typedef enum {
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  PCAL6524_LLD_CONFIGURATION_INPUT    = 0b1,
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  PCAL6524_LLD_CONFIGURATION_OUTPUT   = 0b0,
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} pcal6524_lld_configuration_t;
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/**
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 * @brief   Output drive strength register mask values.
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 * @details Configures maximum current of output pins can be defined via a 2 bit mask per pin.
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 *          Toggling multiple output pins simultaneously a peak current may induce noise to supply voltage and ground.
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 *          By lowering the maximum current per pin. this effect can be minimized.
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 *          The default value (after reset) is 0b11 (factor 1x)
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 */
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typedef enum {
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  PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_25    = 0b00,
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  PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_5     = 0b01,
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  PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_75    = 0b10,
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  PCAL6524_LL_OUTPUTDRIVESTRENGTH_1       = 0b11,
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} pcal6524_lld_outputdrivestrength_t;
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/**
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 * @brief   Input latch register bit values.
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 * @details Allows to latch interrupt and input states per pin, if an interrupt occurred.
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 *          The default value (after reset) is 0b0 (disabled).
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 */
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typedef enum {
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  PCAL6524_LLD_INPUTLATCH_ENABLED   = 0b1,
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  PCAL6524_LLD_INPUTLATCH_DISABLED  = 0b0,
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} pcal6524_lld_inputlatch_t;
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/**
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 * @brief   Pull-up/Pull-down enable register bis values.
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 * @details Configures per pin whether the pull-up/pull-down resistors shall be enabled.
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 *          If a pin is configured as open-drain output, the setting in this register are overridden and the resistors are disconnected.
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 *          The default value (after reset) is 0b0 (disabled).
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 */
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typedef enum {
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  PCAL6524_LLD_PUPD_ENABLED   = 0b1,
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  PCAL6524_LLD_PUPD_DISABLED  = 0b0,
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} pcal6524_lld_pupdenable_t;
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/**
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 * @brief   Pull-up/Pull-dpwn selection register bit values.
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 * @details Selects between pull-up and pull-down resistor (100 kΩ) per pin.
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 *          Has no effect if the according bit is the pull-up/pull-down enable register is disabled.
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 *          The default value (after reset) is 0b1 (pull-up).
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 */
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typedef enum {
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  PCAL6524_LLD_PUPDSELECTION_PULLUP   = 0b1,
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  PCAL6524_LLD_PUPDSELECTION_PULLDOWN = 0b0,
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} pcal6524_lld_pupdselection_t;
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/**
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 * @brief   Interrupt mask register bit values.
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 * @details Allows to enable (value 0) or disable (value 1) interrupts per pin.
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 *          The default value (after reset) is 0b1 (interrupt disabled).
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 */
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typedef enum {
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  PCAL6524_LLD_INTERRUPTMASK_ENABLED  = 0b0,
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  PCAL6524_LLD_INTERRUPTMASK_DSIABLED = 0b1,
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} pcal6524_lld_interruptmask_t;
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/**
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 * @brief   Interrupt status register bit value.
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 * @details Indicates whether an interrupt occurred per pin.
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 *          After reset the register is initialized with 0b0 (no interrupt occurred yet).
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 */
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typedef enum {
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  PCAL6524_LLD_INTERRUPTSTATUS_ACTIVE   = 0b1,
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  PCAL6524_LLD_INTERRUPTSTATUS_INACTIVE = 0b0,
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} pcal6542_lld_interruptstatus_t;
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/**
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 * @brief   Output port configuration register mask of valid bits.
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 */
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#define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK       0x07u
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/**
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 * @brief   Output port configuration register mask for I/O port 0.
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 */
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#define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT0 0x01u
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/**
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 * @brief   Output port configuration register mask for I/O port 1.
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 */
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#define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT1 0x02u
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/**
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 * @brief   Output port configuration register mask for I/O port 2.
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 */
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#define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT2 0x04u
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/**
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 * @brief   Output port configuration register bit values.
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 * @details Configures all ouput pins per port to be push-pull or open-drain.
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 *          The default value (after reset) is 0b0 (push-pull).
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 */
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typedef enum {
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  PCAL6524_LLD_OUTPUTCONFIGURATION_PUSHPULL   = 0b0,
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  PCAL6524_LLD_OUTPUTCONFIGURATION_OPENDRAIN  = 0b1,
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} pcal6524_lld_outputconfiguration_t;
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/**
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 * @brief   Interrupt edge register mask values.
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 * @details Configures the type of event that would cause an interrupt per pin.
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 *          The default value (after reset) is 0b00 (level triggered).
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 */
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typedef enum {
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  PCAL6524_LLD_INTERRUPTEDGE_LEVELTRIGGERED = 0b00,
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  PCAL6524_LLD_INTERRUPTEDGE_RISINGEDGE     = 0b01,
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  PCAL6524_LLD_INTERRUPTEDGE_FALLINGEDGE    = 0b10,
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  PCAL6524_LLD_INTERRUPTEDGE_ANYEDGE        = 0b11,
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} pcal6524_lld_interruptedge_t;
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/**
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 * @brief   Input status register bit values.
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 * @details Reflects the current logic level per pin similar to the input register.
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 *          However, values are not latched and reading the register will not reset interrupts.
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 */
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typedef enum {
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  PCAL6524_LLD_INPUTSTATUS_LOW  = 0b0,
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  PCAL6524_LLD_INPUTSTATUS_HIGH = 0b1,
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} pcal6524_lld_inputstatus_t;
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/**
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 * @brief   Individual pin output configuration register bit values.
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 * @details Can be used to invert the port-wide push-pull/open-drain configuration via the ouput port configuration register per pin.
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 *          the default value (after reset) is 0b0 (not inverted).
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 */
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typedef enum {
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  PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_PORT      = 0b0,
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  PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_INVERTED  = 0b1,
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} pcal6524_lld_individualpinoutputconfiguration_t;
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/**
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 * @brief   Switch debounce enable register bit values.
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 * @details Allows to enable debounce functionality for I/O ports 0 and 1.
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 *          In order to use the debounce feature, an oscillator signal must be applied to pin 0 of port 0.
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 *          The default value (after reset) is 0b0 (disabled).
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 */
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typedef enum {
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  PCAL6524_LLD_SWITCHDEBOUNCE_ENABLED   = 0b1,
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  PCAL6524_LLD_SWITCHDEBOUNCE_DISABLED  = 0b0,
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} pcal6524_lld_switchdebounceenable_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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  uint8_t pcal6524_lld_cmd_groupsize(const pcal6524_lld_cmd_t cmd);
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//  apalExitStatus_t pcal6524_lld_read_id(const PCAL6524Driver* const pcal6524d, uint8_t* const data, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_read_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_write_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t data, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_read_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_write_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_read_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const uint8_t length, const apalTime_t timeout);
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  apalExitStatus_t pcal6524_lld_write_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const uint8_t length, const apalTime_t timeout);
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#ifdef __cplusplus
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}
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#endif
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#endif /* defined(AMIROLLD_CFG_USE_PCAL6524) */
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#endif /* AMIROLLD_PCAL6524_H */
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/** @} */