amiro-lld / source / alld_dw1000.c @ 8c47f14b
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1 | fce9feec | Robin Ewers | /*
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2 | AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
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3 | f125ae07 | Thomas Schöpping | Copyright (C) 2016..2019 Thomas Schöpping et al.
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4 | fce9feec | Robin Ewers | |
5 | This program is free software: you can redistribute it and/or modify
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6 | it under the terms of the GNU Lesser General Public License as published by
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7 | the Free Software Foundation, either version 3 of the License, or
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8 | (at your option) any later version.
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9 | |||
10 | This program is distributed in the hope that it will be useful,
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11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 | GNU Lesser General Public License for more details.
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14 | |||
15 | You should have received a copy of the GNU Lesser General Public License
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16 | along with this program. If not, see <http://www.gnu.org/licenses/>.
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17 | */
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18 | |||
19 | /*! ------------------------------------------------------------------------------------------------------------------
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20 | * @file deca_device.c
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21 | * @brief Decawave device configuration and control functions
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22 | *
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23 | * @attention
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24 | *
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25 | * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
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26 | *
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27 | * All rights reserved.
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28 | *
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29 | */
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30 | |||
31 | |||
32 | #include <alld_dw1000.h> |
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33 | #if defined(AMIROLLD_CFG_USE_DW1000) || defined(__DOXYGEN__)
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34 | |||
35 | #include <alld_dw1000_regs.h> |
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36 | #include <aos_thread.h> |
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37 | #include <assert.h> |
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38 | #include <string.h> |
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39 | #include <stdlib.h> |
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40 | #include <math.h> |
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41 | |||
42 | |||
43 | // HW dependent implementation (see bottom of file)
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44 | static int _alld_dw1000_writespi(uint16_t headerLength, |
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45 | const uint8_t *headerBuffer,
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46 | uint32_t bodyLength, |
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47 | const uint8_t *bodyBuffer);
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48 | |||
49 | static int _alld_dw1000_readspi(uint16_t headerLength, |
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50 | const uint8_t *headerBuffer,
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51 | uint32_t readlength, |
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52 | uint8_t *readBuffer); |
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53 | |||
54 | // Defines for enable_clocks function
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55 | #define FORCE_SYS_XTI 0 |
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56 | #define ENABLE_ALL_SEQ 1 |
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57 | #define FORCE_SYS_PLL 2 |
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58 | #define READ_ACC_ON 7 |
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59 | #define READ_ACC_OFF 8 |
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60 | #define FORCE_OTP_ON 11 |
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61 | #define FORCE_OTP_OFF 12 |
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62 | #define FORCE_TX_PLL 13 |
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63 | #define FORCE_LDE 14 |
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64 | |||
65 | // Defines for ACK request bitmask in DATA and MAC COMMAND frame control (first byte) - Used to detect AAT bit wrongly set.
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66 | #define FCTRL_ACK_REQ_MASK 0x20 |
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67 | // Frame control maximum length in bytes.
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68 | #define FCTRL_LEN_MAX 2 |
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69 | |||
70 | |||
71 | #define NUM_BR 3 |
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72 | #define NUM_PRF 2 |
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73 | #define NUM_PACS 4 |
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74 | #define NUM_BW 2 //2 bandwidths are supported |
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75 | #define NUM_SFD 2 //supported number of SFDs - standard = 0, non-standard = 1 |
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76 | #define NUM_CH 6 //supported channels are 1, 2, 3, 4, 5, 7 |
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77 | #define NUM_CH_SUPPORTED 8 //supported channels are '0', 1, 2, 3, 4, 5, '6', 7 |
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78 | #define PCODES 25 //supported preamble codes |
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79 | |||
80 | |||
81 | typedef struct { |
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82 | uint32_t lo32; |
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83 | uint16_t target[NUM_PRF]; |
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84 | } agc_cfg_struct ; |
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85 | |||
86 | extern const agc_cfg_struct agc_config ; |
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87 | |||
88 | //SFD threshold settings for 110k, 850k, 6.8Mb standard and non-standard
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89 | extern const uint16_t sftsh[NUM_BR][NUM_SFD]; |
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90 | |||
91 | extern const uint16_t dtune1[NUM_PRF]; |
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92 | |||
93 | #define XMLPARAMS_VERSION (1.17f) |
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94 | |||
95 | extern const uint32_t fs_pll_cfg[NUM_CH]; |
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96 | extern const uint8_t fs_pll_tune[NUM_CH]; |
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97 | extern const uint8_t rx_config[NUM_BW]; |
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98 | extern const uint32_t tx_config[NUM_CH]; |
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99 | extern const uint8_t dwnsSFDlen[NUM_BR]; //length of SFD for each of the bitrates |
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100 | extern const uint32_t digital_bb_config[NUM_PRF][NUM_PACS]; |
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101 | extern const uint8_t chan_idx[NUM_CH_SUPPORTED]; |
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102 | extern const double txpwr_compensation[NUM_CH]; |
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103 | |||
104 | #define PEAK_MULTPLIER (0x60) //3 -> (0x3 * 32) & 0x00E0 |
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105 | #define N_STD_FACTOR (13) |
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106 | #define LDE_PARAM1 (PEAK_MULTPLIER | N_STD_FACTOR)
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107 | |||
108 | #define LDE_PARAM3_16 (0x1607) |
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109 | #define LDE_PARAM3_64 (0x0607) |
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110 | |||
111 | #define MIXER_GAIN_STEP (0.5) |
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112 | #define DA_ATTN_STEP (2.5) |
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113 | |||
114 | // #define DWT_API_ERROR_CHECK // define so API checks config input parameters
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115 | |||
116 | //-----------------------------------------
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117 | // map the channel number to the index in the configuration arrays below
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118 | // 0th element is chan 1, 1st is chan 2, 2nd is chan 3, 3rd is chan 4, 4th is chan 5, 5th is chan 7
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119 | const uint8_t chan_idx[NUM_CH_SUPPORTED] = {0, 0, 1, 2, 3, 4, 0, 5}; |
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120 | |||
121 | //-----------------------------------------
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122 | const uint32_t tx_config[NUM_CH] =
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123 | { |
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124 | RF_TXCTRL_CH1, |
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125 | RF_TXCTRL_CH2, |
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126 | RF_TXCTRL_CH3, |
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127 | RF_TXCTRL_CH4, |
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128 | RF_TXCTRL_CH5, |
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129 | RF_TXCTRL_CH7, |
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130 | }; |
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131 | |||
132 | //Frequency Synthesiser - PLL configuration
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133 | const uint32_t fs_pll_cfg[NUM_CH] =
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134 | { |
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135 | FS_PLLCFG_CH1, |
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136 | FS_PLLCFG_CH2, |
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137 | FS_PLLCFG_CH3, |
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138 | FS_PLLCFG_CH4, |
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139 | FS_PLLCFG_CH5, |
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140 | FS_PLLCFG_CH7 |
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141 | }; |
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142 | |||
143 | //Frequency Synthesiser - PLL tuning
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144 | const uint8_t fs_pll_tune[NUM_CH] =
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145 | { |
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146 | FS_PLLTUNE_CH1, |
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147 | FS_PLLTUNE_CH2, |
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148 | FS_PLLTUNE_CH3, |
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149 | FS_PLLTUNE_CH4, |
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150 | FS_PLLTUNE_CH5, |
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151 | FS_PLLTUNE_CH7 |
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152 | }; |
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153 | |||
154 | //bandwidth configuration
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155 | const uint8_t rx_config[NUM_BW] =
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156 | { |
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157 | RF_RXCTRLH_NBW, |
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158 | RF_RXCTRLH_WBW |
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159 | }; |
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160 | |||
161 | |||
162 | const agc_cfg_struct agc_config =
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163 | { |
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164 | AGC_TUNE2_VAL, |
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165 | { AGC_TUNE1_16M , AGC_TUNE1_64M } //adc target
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166 | }; |
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167 | |||
168 | //DW non-standard SFD length for 110k, 850k and 6.81M
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169 | const uint8_t dwnsSFDlen[NUM_BR] =
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170 | { |
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171 | DW_NS_SFD_LEN_110K, |
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172 | DW_NS_SFD_LEN_850K, |
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173 | DW_NS_SFD_LEN_6M8 |
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174 | }; |
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175 | |||
176 | // SFD Threshold
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177 | const uint16_t sftsh[NUM_BR][NUM_SFD] =
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178 | { |
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179 | { |
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180 | DRX_TUNE0b_110K_STD, |
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181 | DRX_TUNE0b_110K_NSTD |
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182 | }, |
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183 | { |
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184 | DRX_TUNE0b_850K_STD, |
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185 | DRX_TUNE0b_850K_NSTD |
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186 | }, |
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187 | { |
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188 | DRX_TUNE0b_6M8_STD, |
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189 | DRX_TUNE0b_6M8_NSTD |
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190 | } |
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191 | }; |
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192 | |||
193 | const uint16_t dtune1[NUM_PRF] =
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194 | { |
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195 | DRX_TUNE1a_PRF16, |
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196 | DRX_TUNE1a_PRF64 |
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197 | }; |
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198 | |||
199 | const uint32_t digital_bb_config[NUM_PRF][NUM_PACS] =
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200 | { |
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201 | { |
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202 | DRX_TUNE2_PRF16_PAC8, |
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203 | DRX_TUNE2_PRF16_PAC16, |
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204 | DRX_TUNE2_PRF16_PAC32, |
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205 | DRX_TUNE2_PRF16_PAC64 |
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206 | }, |
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207 | { |
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208 | DRX_TUNE2_PRF64_PAC8, |
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209 | DRX_TUNE2_PRF64_PAC16, |
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210 | DRX_TUNE2_PRF64_PAC32, |
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211 | DRX_TUNE2_PRF64_PAC64 |
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212 | } |
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213 | }; |
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214 | |||
215 | const uint16_t lde_replicaCoeff[PCODES] =
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216 | { |
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217 | 0, // No preamble code 0 |
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218 | LDE_REPC_PCODE_1, |
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219 | LDE_REPC_PCODE_2, |
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220 | LDE_REPC_PCODE_3, |
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221 | LDE_REPC_PCODE_4, |
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222 | LDE_REPC_PCODE_5, |
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223 | LDE_REPC_PCODE_6, |
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224 | LDE_REPC_PCODE_7, |
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225 | LDE_REPC_PCODE_8, |
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226 | LDE_REPC_PCODE_9, |
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227 | LDE_REPC_PCODE_10, |
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228 | LDE_REPC_PCODE_11, |
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229 | LDE_REPC_PCODE_12, |
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230 | LDE_REPC_PCODE_13, |
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231 | LDE_REPC_PCODE_14, |
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232 | LDE_REPC_PCODE_15, |
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233 | LDE_REPC_PCODE_16, |
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234 | LDE_REPC_PCODE_17, |
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235 | LDE_REPC_PCODE_18, |
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236 | LDE_REPC_PCODE_19, |
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237 | LDE_REPC_PCODE_20, |
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238 | LDE_REPC_PCODE_21, |
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239 | LDE_REPC_PCODE_22, |
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240 | LDE_REPC_PCODE_23, |
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241 | LDE_REPC_PCODE_24 |
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242 | }; |
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243 | |||
244 | const double txpwr_compensation[NUM_CH] = { |
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245 | 0.0, |
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246 | 0.035, |
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247 | 0.0, |
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248 | 0.0, |
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249 | 0.065, |
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250 | 0.0 |
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251 | }; |
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252 | |||
253 | |||
254 | #define NUM_16M_OFFSET (37) |
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255 | #define NUM_16M_OFFSETWB (68) |
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256 | #define NUM_64M_OFFSET (26) |
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257 | #define NUM_64M_OFFSETWB (59) |
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258 | |||
259 | const uint8_t chan_idxnb[NUM_CH_SUPPORTED] = {0, 0, 1, 2, 0, 3, 0, 0}; //only channels 1,2,3 and 5 are in the narrow band tables |
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260 | const uint8_t chan_idxwb[NUM_CH_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 1}; //only channels 4 and 7 are in in the wide band tables |
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261 | |||
262 | //---------------------------------------------------------------------------------------------------------------------------
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263 | // Range Bias Correction TABLES of range values in integer units of 25 CM, for 8-bit unsigned storage, MUST END IN 255 !!!!!!
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264 | //---------------------------------------------------------------------------------------------------------------------------
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265 | |||
266 | // offsets to nearest centimeter for index 0, all rest are +1 cm per value
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267 | |||
268 | #define CM_OFFSET_16M_NB (-23) // for normal band channels at 16 MHz PRF |
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269 | #define CM_OFFSET_16M_WB (-28) // for wider band channels at 16 MHz PRF |
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270 | #define CM_OFFSET_64M_NB (-17) // for normal band channels at 64 MHz PRF |
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271 | #define CM_OFFSET_64M_WB (-30) // for wider band channels at 64 MHz PRF |
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272 | |||
273 | |||
274 | //---------------------------------------------------------------------------------------------------------------------------
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275 | // range25cm16PRFnb: Range Bias Correction table for narrow band channels at 16 MHz PRF, NB: !!!! each MUST END IN 255 !!!!
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276 | //---------------------------------------------------------------------------------------------------------------------------
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277 | |||
278 | const uint8_t range25cm16PRFnb[4][NUM_16M_OFFSET] = |
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279 | { |
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280 | // ch 1 - range25cm16PRFnb
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281 | { |
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282 | 1,
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283 | 3,
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284 | 4,
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285 | 5,
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286 | 7,
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287 | 9,
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288 | 11,
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289 | 12,
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290 | 13,
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291 | 15,
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292 | 18,
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293 | 20,
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294 | 23,
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295 | 25,
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296 | 28,
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297 | 30,
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298 | 33,
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299 | 36,
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300 | 40,
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301 | 43,
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302 | 47,
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303 | 50,
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304 | 54,
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305 | 58,
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306 | 63,
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307 | 66,
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308 | 71,
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309 | 76,
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310 | 82,
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311 | 89,
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312 | 98,
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313 | 109,
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314 | 127,
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315 | 155,
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316 | 222,
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317 | 255,
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318 | 255
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319 | }, |
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320 | |||
321 | // ch 2 - range25cm16PRFnb
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322 | { |
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323 | 1,
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324 | 2,
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325 | 4,
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326 | 5,
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327 | 6,
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328 | 8,
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329 | 9,
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330 | 10,
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331 | 12,
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332 | 13,
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333 | 15,
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334 | 18,
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335 | 20,
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336 | 22,
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337 | 24,
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338 | 27,
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339 | 29,
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340 | 32,
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341 | 35,
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342 | 38,
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343 | 41,
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344 | 44,
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345 | 47,
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346 | 51,
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347 | 55,
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348 | 58,
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349 | 62,
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350 | 66,
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351 | 71,
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352 | 78,
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353 | 85,
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354 | 96,
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355 | 111,
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356 | 135,
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357 | 194,
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358 | 240,
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359 | 255
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360 | }, |
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361 | |||
362 | // ch 3 - range25cm16PRFnb
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363 | { |
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364 | 1,
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365 | 2,
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366 | 3,
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367 | 4,
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368 | 5,
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369 | 7,
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370 | 8,
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371 | 9,
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372 | 10,
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373 | 12,
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374 | 14,
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375 | 16,
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376 | 18,
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377 | 20,
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378 | 22,
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379 | 24,
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380 | 26,
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381 | 28,
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382 | 31,
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383 | 33,
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384 | 36,
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385 | 39,
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386 | 42,
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387 | 45,
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388 | 49,
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389 | 52,
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390 | 55,
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391 | 59,
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392 | 63,
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393 | 69,
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394 | 76,
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395 | 85,
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396 | 98,
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397 | 120,
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398 | 173,
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399 | 213,
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400 | 255
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401 | }, |
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402 | |||
403 | // ch 5 - range25cm16PRFnb
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404 | { |
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405 | 1,
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406 | 1,
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407 | 2,
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408 | 3,
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409 | 4,
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410 | 5,
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411 | 6,
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412 | 6,
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413 | 7,
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414 | 8,
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415 | 9,
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416 | 11,
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417 | 12,
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418 | 14,
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419 | 15,
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420 | 16,
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421 | 18,
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422 | 20,
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423 | 21,
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424 | 23,
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425 | 25,
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426 | 27,
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427 | 29,
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428 | 31,
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429 | 34,
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430 | 36,
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431 | 38,
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432 | 41,
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433 | 44,
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434 | 48,
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435 | 53,
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436 | 59,
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437 | 68,
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438 | 83,
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439 | 120,
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440 | 148,
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441 | 255
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442 | } |
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443 | }; // end range25cm16PRFnb
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444 | |||
445 | |||
446 | //---------------------------------------------------------------------------------------------------------------------------
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447 | // range25cm16PRFwb: Range Bias Correction table for wide band channels at 16 MHz PRF, NB: !!!! each MUST END IN 255 !!!!
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448 | //---------------------------------------------------------------------------------------------------------------------------
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449 | |||
450 | const uint8_t range25cm16PRFwb[2][NUM_16M_OFFSETWB] = |
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451 | { |
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452 | // ch 4 - range25cm16PRFwb
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453 | { |
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454 | 7,
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455 | 7,
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456 | 8,
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457 | 9,
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458 | 9,
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459 | 10,
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460 | 11,
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461 | 11,
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462 | 12,
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463 | 13,
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464 | 14,
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465 | 15,
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466 | 16,
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467 | 17,
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468 | 18,
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469 | 19,
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470 | 20,
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471 | 21,
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472 | 22,
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473 | 23,
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474 | 24,
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475 | 26,
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476 | 27,
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477 | 28,
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478 | 30,
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479 | 31,
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480 | 32,
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481 | 34,
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482 | 36,
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483 | 38,
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484 | 40,
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485 | 42,
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486 | 44,
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487 | 46,
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488 | 48,
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489 | 50,
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490 | 52,
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491 | 55,
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492 | 57,
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493 | 59,
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494 | 61,
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495 | 63,
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496 | 66,
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497 | 68,
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498 | 71,
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499 | 74,
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500 | 78,
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501 | 81,
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502 | 85,
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503 | 89,
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504 | 94,
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505 | 99,
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506 | 104,
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507 | 110,
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508 | 116,
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509 | 123,
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510 | 130,
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511 | 139,
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512 | 150,
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513 | 164,
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514 | 182,
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515 | 207,
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516 | 238,
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517 | 255,
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518 | 255,
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519 | 255,
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520 | 255,
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521 | 255
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522 | }, |
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523 | |||
524 | // ch 7 - range25cm16PRFwb
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525 | { |
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526 | 4,
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527 | 5,
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528 | 5,
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529 | 5,
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530 | 6,
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531 | 6,
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532 | 7,
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533 | 7,
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534 | 7,
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535 | 8,
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536 | 9,
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537 | 9,
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538 | 10,
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539 | 10,
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540 | 11,
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541 | 11,
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542 | 12,
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543 | 13,
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544 | 13,
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545 | 14,
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546 | 15,
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547 | 16,
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548 | 17,
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549 | 17,
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550 | 18,
|
||
551 | 19,
|
||
552 | 20,
|
||
553 | 21,
|
||
554 | 22,
|
||
555 | 23,
|
||
556 | 25,
|
||
557 | 26,
|
||
558 | 27,
|
||
559 | 29,
|
||
560 | 30,
|
||
561 | 31,
|
||
562 | 32,
|
||
563 | 34,
|
||
564 | 35,
|
||
565 | 36,
|
||
566 | 38,
|
||
567 | 39,
|
||
568 | 40,
|
||
569 | 42,
|
||
570 | 44,
|
||
571 | 46,
|
||
572 | 48,
|
||
573 | 50,
|
||
574 | 52,
|
||
575 | 55,
|
||
576 | 58,
|
||
577 | 61,
|
||
578 | 64,
|
||
579 | 68,
|
||
580 | 72,
|
||
581 | 75,
|
||
582 | 80,
|
||
583 | 85,
|
||
584 | 92,
|
||
585 | 101,
|
||
586 | 112,
|
||
587 | 127,
|
||
588 | 147,
|
||
589 | 168,
|
||
590 | 182,
|
||
591 | 194,
|
||
592 | 205,
|
||
593 | 255
|
||
594 | } |
||
595 | }; // end range25cm16PRFwb
|
||
596 | |||
597 | //---------------------------------------------------------------------------------------------------------------------------
|
||
598 | // range25cm64PRFnb: Range Bias Correction table for narrow band channels at 64 MHz PRF, NB: !!!! each MUST END IN 255 !!!!
|
||
599 | //---------------------------------------------------------------------------------------------------------------------------
|
||
600 | |||
601 | const uint8_t range25cm64PRFnb[4][NUM_64M_OFFSET] = |
||
602 | { |
||
603 | // ch 1 - range25cm64PRFnb
|
||
604 | { |
||
605 | 1,
|
||
606 | 2,
|
||
607 | 2,
|
||
608 | 3,
|
||
609 | 4,
|
||
610 | 5,
|
||
611 | 7,
|
||
612 | 10,
|
||
613 | 13,
|
||
614 | 16,
|
||
615 | 19,
|
||
616 | 22,
|
||
617 | 24,
|
||
618 | 27,
|
||
619 | 30,
|
||
620 | 32,
|
||
621 | 35,
|
||
622 | 38,
|
||
623 | 43,
|
||
624 | 48,
|
||
625 | 56,
|
||
626 | 78,
|
||
627 | 101,
|
||
628 | 120,
|
||
629 | 157,
|
||
630 | 255
|
||
631 | }, |
||
632 | |||
633 | // ch 2 - range25cm64PRFnb
|
||
634 | { |
||
635 | 1,
|
||
636 | 2,
|
||
637 | 2,
|
||
638 | 3,
|
||
639 | 4,
|
||
640 | 4,
|
||
641 | 6,
|
||
642 | 9,
|
||
643 | 12,
|
||
644 | 14,
|
||
645 | 17,
|
||
646 | 19,
|
||
647 | 21,
|
||
648 | 24,
|
||
649 | 26,
|
||
650 | 28,
|
||
651 | 31,
|
||
652 | 33,
|
||
653 | 37,
|
||
654 | 42,
|
||
655 | 49,
|
||
656 | 68,
|
||
657 | 89,
|
||
658 | 105,
|
||
659 | 138,
|
||
660 | 255
|
||
661 | }, |
||
662 | |||
663 | // ch 3 - range25cm64PRFnb
|
||
664 | { |
||
665 | 1,
|
||
666 | 1,
|
||
667 | 2,
|
||
668 | 3,
|
||
669 | 3,
|
||
670 | 4,
|
||
671 | 5,
|
||
672 | 8,
|
||
673 | 10,
|
||
674 | 13,
|
||
675 | 15,
|
||
676 | 17,
|
||
677 | 19,
|
||
678 | 21,
|
||
679 | 23,
|
||
680 | 25,
|
||
681 | 27,
|
||
682 | 30,
|
||
683 | 33,
|
||
684 | 37,
|
||
685 | 44,
|
||
686 | 60,
|
||
687 | 79,
|
||
688 | 93,
|
||
689 | 122,
|
||
690 | 255
|
||
691 | }, |
||
692 | |||
693 | // ch 5 - range25cm64PRFnb
|
||
694 | { |
||
695 | 1,
|
||
696 | 1,
|
||
697 | 1,
|
||
698 | 2,
|
||
699 | 2,
|
||
700 | 3,
|
||
701 | 4,
|
||
702 | 6,
|
||
703 | 7,
|
||
704 | 9,
|
||
705 | 10,
|
||
706 | 12,
|
||
707 | 13,
|
||
708 | 15,
|
||
709 | 16,
|
||
710 | 17,
|
||
711 | 19,
|
||
712 | 21,
|
||
713 | 23,
|
||
714 | 26,
|
||
715 | 30,
|
||
716 | 42,
|
||
717 | 55,
|
||
718 | 65,
|
||
719 | 85,
|
||
720 | 255
|
||
721 | } |
||
722 | }; // end range25cm64PRFnb
|
||
723 | |||
724 | //---------------------------------------------------------------------------------------------------------------------------
|
||
725 | // range25cm64PRFwb: Range Bias Correction table for wide band channels at 64 MHz PRF, NB: !!!! each MUST END IN 255 !!!!
|
||
726 | //---------------------------------------------------------------------------------------------------------------------------
|
||
727 | |||
728 | const uint8_t range25cm64PRFwb[2][NUM_64M_OFFSETWB] = |
||
729 | { |
||
730 | // ch 4 - range25cm64PRFwb
|
||
731 | { |
||
732 | 7,
|
||
733 | 8,
|
||
734 | 8,
|
||
735 | 9,
|
||
736 | 9,
|
||
737 | 10,
|
||
738 | 11,
|
||
739 | 12,
|
||
740 | 13,
|
||
741 | 13,
|
||
742 | 14,
|
||
743 | 15,
|
||
744 | 16,
|
||
745 | 16,
|
||
746 | 17,
|
||
747 | 18,
|
||
748 | 19,
|
||
749 | 19,
|
||
750 | 20,
|
||
751 | 21,
|
||
752 | 22,
|
||
753 | 24,
|
||
754 | 25,
|
||
755 | 27,
|
||
756 | 28,
|
||
757 | 29,
|
||
758 | 30,
|
||
759 | 32,
|
||
760 | 33,
|
||
761 | 34,
|
||
762 | 35,
|
||
763 | 37,
|
||
764 | 39,
|
||
765 | 41,
|
||
766 | 43,
|
||
767 | 45,
|
||
768 | 48,
|
||
769 | 50,
|
||
770 | 53,
|
||
771 | 56,
|
||
772 | 60,
|
||
773 | 64,
|
||
774 | 68,
|
||
775 | 74,
|
||
776 | 81,
|
||
777 | 89,
|
||
778 | 98,
|
||
779 | 109,
|
||
780 | 122,
|
||
781 | 136,
|
||
782 | 146,
|
||
783 | 154,
|
||
784 | 162,
|
||
785 | 178,
|
||
786 | 220,
|
||
787 | 249,
|
||
788 | 255,
|
||
789 | 255,
|
||
790 | 255
|
||
791 | }, |
||
792 | |||
793 | // ch 7 - range25cm64PRFwb
|
||
794 | { |
||
795 | 4,
|
||
796 | 5,
|
||
797 | 5,
|
||
798 | 5,
|
||
799 | 6,
|
||
800 | 6,
|
||
801 | 7,
|
||
802 | 7,
|
||
803 | 8,
|
||
804 | 8,
|
||
805 | 9,
|
||
806 | 9,
|
||
807 | 10,
|
||
808 | 10,
|
||
809 | 10,
|
||
810 | 11,
|
||
811 | 11,
|
||
812 | 12,
|
||
813 | 13,
|
||
814 | 13,
|
||
815 | 14,
|
||
816 | 15,
|
||
817 | 16,
|
||
818 | 16,
|
||
819 | 17,
|
||
820 | 18,
|
||
821 | 19,
|
||
822 | 19,
|
||
823 | 20,
|
||
824 | 21,
|
||
825 | 22,
|
||
826 | 23,
|
||
827 | 24,
|
||
828 | 25,
|
||
829 | 26,
|
||
830 | 28,
|
||
831 | 29,
|
||
832 | 31,
|
||
833 | 33,
|
||
834 | 35,
|
||
835 | 37,
|
||
836 | 39,
|
||
837 | 42,
|
||
838 | 46,
|
||
839 | 50,
|
||
840 | 54,
|
||
841 | 60,
|
||
842 | 67,
|
||
843 | 75,
|
||
844 | 83,
|
||
845 | 90,
|
||
846 | 95,
|
||
847 | 100,
|
||
848 | 110,
|
||
849 | 135,
|
||
850 | 153,
|
||
851 | 172,
|
||
852 | 192,
|
||
853 | 255
|
||
854 | } |
||
855 | }; // end range25cm64PRFwb
|
||
856 | |||
857 | |||
858 | |||
859 | |||
860 | |||
861 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
862 | * Function: dwt_getrangebias()
|
||
863 | *
|
||
864 | * Description: This function is used to return the range bias correction need for TWR with DW1000 units.
|
||
865 | *
|
||
866 | * input parameters:
|
||
867 | * @param chan - specifies the operating channel (e.g. 1, 2, 3, 4, 5, 6 or 7)
|
||
868 | * @param range - the calculated distance before correction
|
||
869 | * @param prf - this is the PRF e.g. DWT_PRF_16M or DWT_PRF_64M
|
||
870 | *
|
||
871 | * output parameters
|
||
872 | *
|
||
873 | * returns correction needed in meters
|
||
874 | */
|
||
875 | double dwt_getrangebias(uint8_t chan, float range, uint8_t prf) |
||
876 | { |
||
877 | //first get the lookup index that corresponds to given range for a particular channel at 16M PRF
|
||
878 | int i = 0 ; |
||
879 | int chanIdx ;
|
||
880 | int cmoffseti ; // integer number of CM offset |
||
881 | |||
882 | double mOffset ; // final offset result in metres |
||
883 | |||
884 | // NB: note we may get some small negitive values e.g. up to -50 cm.
|
||
885 | |||
886 | int rangeint25cm = (int) (range * 4.00) ; // convert range to integer number of 25cm values. |
||
887 | |||
888 | if (rangeint25cm > 255) rangeint25cm = 255 ; // make sure it matches largest value in table (all tables end in 255 !!!!) |
||
889 | |||
890 | if (prf == DWT_PRF_16M)
|
||
891 | { |
||
892 | switch(chan)
|
||
893 | { |
||
894 | case 4: |
||
895 | case 7: |
||
896 | { |
||
897 | chanIdx = chan_idxwb[chan]; |
||
898 | while (rangeint25cm > range25cm16PRFwb[chanIdx][i]) i++ ; // find index in table corresponding to range |
||
899 | cmoffseti = i + CM_OFFSET_16M_WB ; // nearest centimeter correction
|
||
900 | } |
||
901 | break;
|
||
902 | default:
|
||
903 | { |
||
904 | chanIdx = chan_idxnb[chan]; |
||
905 | while (rangeint25cm > range25cm16PRFnb[chanIdx][i]) i++ ; // find index in table corresponding to range |
||
906 | cmoffseti = i + CM_OFFSET_16M_NB ; // nearest centimeter correction
|
||
907 | } |
||
908 | }//end of switch
|
||
909 | } |
||
910 | else // 64M PRF |
||
911 | { |
||
912 | switch(chan)
|
||
913 | { |
||
914 | case 4: |
||
915 | case 7: |
||
916 | { |
||
917 | chanIdx = chan_idxwb[chan]; |
||
918 | while (rangeint25cm > range25cm64PRFwb[chanIdx][i]) i++ ; // find index in table corresponding to range |
||
919 | cmoffseti = i + CM_OFFSET_64M_WB ; // nearest centimeter correction
|
||
920 | } |
||
921 | break;
|
||
922 | default:
|
||
923 | { |
||
924 | chanIdx = chan_idxnb[chan]; |
||
925 | while (rangeint25cm > range25cm64PRFnb[chanIdx][i]) i++ ; // find index in table corresponding to range |
||
926 | cmoffseti = i + CM_OFFSET_64M_NB ; // nearest centimeter correction
|
||
927 | } |
||
928 | }//end of switch
|
||
929 | } // end else
|
||
930 | |||
931 | |||
932 | mOffset = (float) cmoffseti ; // offset result in centimmetres |
||
933 | |||
934 | mOffset *= 0.01 ; // convert to metres |
||
935 | |||
936 | return (mOffset) ;
|
||
937 | } |
||
938 | |||
939 | |||
940 | |||
941 | // -------------------------------------------------------------------------------------------------------------------
|
||
942 | //
|
||
943 | // Internal functions for controlling and configuring the device
|
||
944 | //
|
||
945 | // -------------------------------------------------------------------------------------------------------------------
|
||
946 | |||
947 | // Enable and Configure specified clocks
|
||
948 | void _dwt_enableclocks(int clocks) ; |
||
949 | // Configure the ucode (FP algorithm) parameters
|
||
950 | void _dwt_configlde(int prf); |
||
951 | // Load ucode from OTP/ROM
|
||
952 | void _dwt_loaducodefromrom(void); |
||
953 | // Read non-volatile memory
|
||
954 | uint32_t _dwt_otpread(uint32_t address); |
||
955 | // Program the non-volatile memory
|
||
956 | uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address); |
||
957 | // Upload the device configuration into always on memory
|
||
958 | void _dwt_aonarrayupload(void); |
||
959 | // -------------------------------------------------------------------------------------------------------------------
|
||
960 | |||
961 | /*!
|
||
962 | * Static data for DW1000 DecaWave Transceiver control
|
||
963 | */
|
||
964 | |||
965 | static dwt_local_data_t dw1000local[DWT_NUM_DW_DEV] ; // Static local device data, can be an array to support multiple DW1000 testing applications/platforms |
||
966 | static dwt_local_data_t *pdw1000local = dw1000local ; // Static local data structure pointer |
||
967 | |||
968 | |||
969 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
970 | * @fn dwt_setdevicedataptr()
|
||
971 | *
|
||
972 | * @brief This function sets the local data structure pointer to point to the structure in the local array as given by the index.
|
||
973 | *
|
||
974 | * input parameters
|
||
975 | * @param index - selects the array object to point to. Must be within the array bounds, i.e. < DWT_NUM_DW_DEV
|
||
976 | *
|
||
977 | * output parameters
|
||
978 | *
|
||
979 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
980 | */
|
||
981 | int dwt_setdevicedataptr(unsigned int index) |
||
982 | { |
||
983 | // Check the index is within the array bounds
|
||
984 | if (DWT_NUM_DW_DEV > index) // return error if index outside the array bounds |
||
985 | { |
||
986 | return DWT_ERROR ;
|
||
987 | } |
||
988 | |||
989 | pdw1000local = &dw1000local[index]; |
||
990 | |||
991 | return DWT_SUCCESS ;
|
||
992 | } |
||
993 | |||
994 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
995 | * @fn dwt_initialise()
|
||
996 | *
|
||
997 | * @brief This function initiates communications with the DW1000 transceiver
|
||
998 | * and reads its DEV_ID register (address 0x00) to verify the IC is one supported
|
||
999 | * by this software (e.g. DW1000 32-bit device ID value is 0xDECA0130). Then it
|
||
1000 | * does any initial once only device configurations needed for use and initialises
|
||
1001 | * as necessary any static data items belonging to this low-level driver.
|
||
1002 | *
|
||
1003 | * NOTES:
|
||
1004 | * 1.this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
|
||
1005 | * 2.it also reads and applies LDO tune and crystal trim values from OTP memory
|
||
1006 | *
|
||
1007 | * input parameters
|
||
1008 | * @param config - specifies what configuration to load
|
||
1009 | * DWT_LOADUCODE 0x1 - load the LDE microcode from ROM - enabled accurate RX timestamp
|
||
1010 | * DWT_LOADNONE 0x0 - do not load any values from OTP memory
|
||
1011 | *
|
||
1012 | * output parameters
|
||
1013 | *
|
||
1014 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
1015 | */
|
||
1016 | // OTP addresses definitions
|
||
1017 | #define LDOTUNE_ADDRESS (0x04) |
||
1018 | #define PARTID_ADDRESS (0x06) |
||
1019 | #define LOTID_ADDRESS (0x07) |
||
1020 | #define VBAT_ADDRESS (0x08) |
||
1021 | #define VTEMP_ADDRESS (0x09) |
||
1022 | #define XTRIM_ADDRESS (0x1E) |
||
1023 | |||
1024 | int dwt_initialise(const uint16_t config, DW1000Driver* drv) |
||
1025 | { |
||
1026 | uint16_t otp_addr = 0;
|
||
1027 | uint32_t ldo_tune = 0;
|
||
1028 | |||
1029 | pdw1000local->dblbuffon = 0; // Double buffer mode off by default |
||
1030 | pdw1000local->wait4resp = 0;
|
||
1031 | pdw1000local->sleep_mode = 0;
|
||
1032 | |||
1033 | pdw1000local->cbTxDone = NULL;
|
||
1034 | pdw1000local->cbRxOk = NULL;
|
||
1035 | pdw1000local->cbRxTo = NULL;
|
||
1036 | pdw1000local->cbRxErr = NULL;
|
||
1037 | |||
1038 | pdw1000local->driver = drv; |
||
1039 | |||
1040 | // Read and validate device ID return -1 if not recognised
|
||
1041 | if (DWT_DEVICE_ID != dwt_readdevid()) // MP IC ONLY (i.e. DW1000) FOR THIS CODE |
||
1042 | { |
||
1043 | return DWT_ERROR ;
|
||
1044 | } |
||
1045 | |||
1046 | // Make sure the device is completely reset before starting initialisation
|
||
1047 | dwt_softreset(); |
||
1048 | |||
1049 | _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: set system clock to XTI - this is necessary to make sure the values read by _dwt_otpread are reliable
|
||
1050 | |||
1051 | // Configure the CPLL lock detect
|
||
1052 | dwt_write8bitoffsetreg(EXT_SYNC_ID, EC_CTRL_OFFSET, EC_CTRL_PLLLCK); |
||
1053 | |||
1054 | // Read OTP revision number
|
||
1055 | otp_addr = _dwt_otpread(XTRIM_ADDRESS) & 0xffff; // Read 32 bit value, XTAL trim val is in low octet-0 (5 bits) |
||
1056 | pdw1000local->otprev = (otp_addr >> 8) & 0xff; // OTP revision is next byte |
||
1057 | |||
1058 | // Load LDO tune from OTP and kick it if there is a value actually programmed.
|
||
1059 | ldo_tune = _dwt_otpread(LDOTUNE_ADDRESS); |
||
1060 | if((ldo_tune & 0xFF) != 0) |
||
1061 | { |
||
1062 | // Kick LDO tune
|
||
1063 | dwt_write8bitoffsetreg(OTP_IF_ID, OTP_SF, OTP_SF_LDO_KICK); // Set load LDE kick bit
|
||
1064 | pdw1000local->sleep_mode |= AON_WCFG_ONW_LLDO; // LDO tune must be kicked at wake-up
|
||
1065 | } |
||
1066 | |||
1067 | // Load Part and Lot ID from OTP
|
||
1068 | pdw1000local->partID = _dwt_otpread(PARTID_ADDRESS); |
||
1069 | pdw1000local->lotID = _dwt_otpread(LOTID_ADDRESS); |
||
1070 | |||
1071 | // XTAL trim value is set in OTP for DW1000 module and EVK/TREK boards but that might not be the case in a custom design
|
||
1072 | pdw1000local->init_xtrim = otp_addr & 0x1F;
|
||
1073 | if (!pdw1000local->init_xtrim) // A value of 0 means that the crystal has not been trimmed |
||
1074 | { |
||
1075 | pdw1000local->init_xtrim = FS_XTALT_MIDRANGE ; // Set to mid-range if no calibration value inside
|
||
1076 | } |
||
1077 | // Configure XTAL trim
|
||
1078 | dwt_setxtaltrim(pdw1000local->init_xtrim); |
||
1079 | |||
1080 | // Load leading edge detect code
|
||
1081 | if(config & DWT_LOADUCODE)
|
||
1082 | { |
||
1083 | _dwt_loaducodefromrom(); |
||
1084 | pdw1000local->sleep_mode |= AON_WCFG_ONW_LLDE; // microcode must be loaded at wake-up
|
||
1085 | } |
||
1086 | else // Should disable the LDERUN enable bit in 0x36, 0x4 |
||
1087 | { |
||
1088 | uint16_t rega = dwt_read16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1) ;
|
||
1089 | rega &= 0xFDFF ; // Clear LDERUN bit |
||
1090 | dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET+1, rega) ;
|
||
1091 | } |
||
1092 | |||
1093 | _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
|
||
1094 | |||
1095 | // The 3 bits in AON CFG1 register must be cleared to ensure proper operation of the DW1000 in DEEPSLEEP mode.
|
||
1096 | dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
|
||
1097 | |||
1098 | // Read system register / store local copy
|
||
1099 | pdw1000local->sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
|
||
1100 | |||
1101 | return DWT_SUCCESS ;
|
||
1102 | |||
1103 | } // end dwt_initialise()
|
||
1104 | |||
1105 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1106 | * @fn dwt_otprevision()
|
||
1107 | *
|
||
1108 | * @brief This is used to return the read OTP revision
|
||
1109 | *
|
||
1110 | * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
|
||
1111 | *
|
||
1112 | * input parameters
|
||
1113 | *
|
||
1114 | * output parameters
|
||
1115 | *
|
||
1116 | * returns the read OTP revision value
|
||
1117 | */
|
||
1118 | uint8_t dwt_otprevision(void)
|
||
1119 | { |
||
1120 | return pdw1000local->otprev ;
|
||
1121 | } |
||
1122 | |||
1123 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1124 | * @fn dwt_setfinegraintxseq()
|
||
1125 | *
|
||
1126 | * @brief This function enables/disables the fine grain TX sequencing (enabled by default).
|
||
1127 | *
|
||
1128 | * input parameters
|
||
1129 | * @param enable - 1 to enable fine grain TX sequencing, 0 to disable it.
|
||
1130 | *
|
||
1131 | * output parameters none
|
||
1132 | *
|
||
1133 | * no return value
|
||
1134 | */
|
||
1135 | void dwt_setfinegraintxseq(int enable) |
||
1136 | { |
||
1137 | if (enable)
|
||
1138 | { |
||
1139 | dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_ENABLE); |
||
1140 | } |
||
1141 | else
|
||
1142 | { |
||
1143 | dwt_write16bitoffsetreg(PMSC_ID, PMSC_TXFINESEQ_OFFSET, PMSC_TXFINESEQ_DISABLE); |
||
1144 | } |
||
1145 | } |
||
1146 | |||
1147 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1148 | * @fn dwt_setlnapamode()
|
||
1149 | *
|
||
1150 | * @brief This is used to enable GPIO for external LNA or PA functionality - HW dependent, consult the DW1000 User Manual.
|
||
1151 | * This can also be used for debug as enabling TX and RX GPIOs is quite handy to monitor DW1000's activity.
|
||
1152 | *
|
||
1153 | * NOTE: Enabling PA functionality requires that fine grain TX sequencing is deactivated. This can be done using
|
||
1154 | * dwt_setfinegraintxseq().
|
||
1155 | *
|
||
1156 | * input parameters
|
||
1157 | * @param lna - 1 to enable LNA functionality, 0 to disable it
|
||
1158 | * @param pa - 1 to enable PA functionality, 0 to disable it
|
||
1159 | *
|
||
1160 | * output parameters
|
||
1161 | *
|
||
1162 | * no return value
|
||
1163 | */
|
||
1164 | void dwt_setlnapamode(int lna, int pa) |
||
1165 | { |
||
1166 | uint32_t gpio_mode = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET); |
||
1167 | gpio_mode &= ~(GPIO_MSGP4_MASK | GPIO_MSGP5_MASK | GPIO_MSGP6_MASK); |
||
1168 | if (lna)
|
||
1169 | { |
||
1170 | gpio_mode |= GPIO_PIN6_EXTRXE; |
||
1171 | } |
||
1172 | if (pa)
|
||
1173 | { |
||
1174 | gpio_mode |= (GPIO_PIN5_EXTTXE | GPIO_PIN4_EXTPA); |
||
1175 | } |
||
1176 | dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, gpio_mode); |
||
1177 | } |
||
1178 | |||
1179 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1180 | * @fn dwt_setgpiodirection()
|
||
1181 | *
|
||
1182 | * @brief This is used to set GPIO direction as an input (1) or output (0)
|
||
1183 | *
|
||
1184 | * input parameters
|
||
1185 | * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
|
||
1186 | * @param direction - this sets the GPIO direction - see GxP0... GxP8 in the deca_regs.h file
|
||
1187 | *
|
||
1188 | * output parameters
|
||
1189 | *
|
||
1190 | * no return value
|
||
1191 | */
|
||
1192 | void dwt_setgpiodirection(uint32_t gpioNum, uint32_t direction)
|
||
1193 | { |
||
1194 | uint8_t buf[GPIO_DIR_LEN]; |
||
1195 | uint32_t command = direction | gpioNum; |
||
1196 | |||
1197 | buf[0] = command & 0xff; |
||
1198 | buf[1] = (command >> 8) & 0xff; |
||
1199 | buf[2] = (command >> 16) & 0xff; |
||
1200 | |||
1201 | dwt_writetodevice(GPIO_CTRL_ID, GPIO_DIR_OFFSET, GPIO_DIR_LEN, buf); |
||
1202 | } |
||
1203 | |||
1204 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1205 | * @fn dwt_setgpiovalue()
|
||
1206 | *
|
||
1207 | * @brief This is used to set GPIO value as (1) or (0) only applies if the GPIO is configured as output
|
||
1208 | *
|
||
1209 | * input parameters
|
||
1210 | * @param gpioNum - this is the GPIO to configure - see GxM0... GxM8 in the deca_regs.h file
|
||
1211 | * @param value - this sets the GPIO value - see GDP0... GDP8 in the deca_regs.h file
|
||
1212 | *
|
||
1213 | * output parameters
|
||
1214 | *
|
||
1215 | * no return value
|
||
1216 | */
|
||
1217 | void dwt_setgpiovalue(uint32_t gpioNum, uint32_t value)
|
||
1218 | { |
||
1219 | uint8_t buf[GPIO_DOUT_LEN]; |
||
1220 | uint32_t command = value | gpioNum; |
||
1221 | |||
1222 | buf[0] = command & 0xff; |
||
1223 | buf[1] = (command >> 8) & 0xff; |
||
1224 | buf[2] = (command >> 16) & 0xff; |
||
1225 | |||
1226 | dwt_writetodevice(GPIO_CTRL_ID, GPIO_DOUT_OFFSET, GPIO_DOUT_LEN, buf); |
||
1227 | } |
||
1228 | |||
1229 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1230 | * @fn dwt_getpartid()
|
||
1231 | *
|
||
1232 | * @brief This is used to return the read part ID of the device
|
||
1233 | *
|
||
1234 | * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
|
||
1235 | *
|
||
1236 | * input parameters
|
||
1237 | *
|
||
1238 | * output parameters
|
||
1239 | *
|
||
1240 | * returns the 32 bit part ID value as programmed in the factory
|
||
1241 | */
|
||
1242 | uint32_t dwt_getpartid(void)
|
||
1243 | { |
||
1244 | return pdw1000local->partID;
|
||
1245 | } |
||
1246 | |||
1247 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1248 | * @fn dwt_getlotid()
|
||
1249 | *
|
||
1250 | * @brief This is used to return the read lot ID of the device
|
||
1251 | *
|
||
1252 | * NOTE: dwt_initialise() must be called prior to this function so that it can return a relevant value.
|
||
1253 | *
|
||
1254 | * input parameters
|
||
1255 | *
|
||
1256 | * output parameters
|
||
1257 | *
|
||
1258 | * returns the 32 bit lot ID value as programmed in the factory
|
||
1259 | */
|
||
1260 | uint32_t dwt_getlotid(void)
|
||
1261 | { |
||
1262 | return pdw1000local->lotID;
|
||
1263 | } |
||
1264 | |||
1265 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1266 | * @fn dwt_readdevid()
|
||
1267 | *
|
||
1268 | * @brief This is used to return the read device type and revision information of the DW1000 device (MP part is 0xDECA0130)
|
||
1269 | *
|
||
1270 | * input parameters
|
||
1271 | *
|
||
1272 | * output parameters
|
||
1273 | *
|
||
1274 | * returns the read value which for DW1000 is 0xDECA0130
|
||
1275 | */
|
||
1276 | uint32_t dwt_readdevid(void)
|
||
1277 | { |
||
1278 | return dwt_read32bitoffsetreg(DEV_ID_ID,0); |
||
1279 | } |
||
1280 | |||
1281 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1282 | * @fn dwt_configuretxrf()
|
||
1283 | *
|
||
1284 | * @brief This function provides the API for the configuration of the TX spectrum
|
||
1285 | * including the power and pulse generator delay. The input is a pointer to the data structure
|
||
1286 | * of type dwt_txconfig_t that holds all the configurable items.
|
||
1287 | *
|
||
1288 | * input parameters
|
||
1289 | * @param config - pointer to the txrf configuration structure, which contains the tx rf config data
|
||
1290 | *
|
||
1291 | * output parameters
|
||
1292 | *
|
||
1293 | * no return value
|
||
1294 | */
|
||
1295 | void dwt_configuretxrf(dwt_txconfig_t* config)
|
||
1296 | { |
||
1297 | |||
1298 | // Configure RF TX PG_DELAY
|
||
1299 | dwt_write8bitoffsetreg(TX_CAL_ID, TC_PGDELAY_OFFSET, config->PGdly); |
||
1300 | |||
1301 | // Configure TX power
|
||
1302 | dwt_write32bitreg(TX_POWER_ID, config->power); |
||
1303 | |||
1304 | } |
||
1305 | |||
1306 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1307 | * @fn dwt_configure()
|
||
1308 | *
|
||
1309 | * @brief This function provides the main API for the configuration of the
|
||
1310 | * DW1000 and this low-level driver. The input is a pointer to the data structure
|
||
1311 | * of type dwt_config_t that holds all the configurable items.
|
||
1312 | * The dwt_config_t structure shows which ones are supported
|
||
1313 | *
|
||
1314 | * input parameters
|
||
1315 | * @param config - pointer to the configuration structure, which contains the device configuration data.
|
||
1316 | *
|
||
1317 | * output parameters
|
||
1318 | *
|
||
1319 | * no return value
|
||
1320 | */
|
||
1321 | void dwt_configure(dwt_config_t *config)
|
||
1322 | { |
||
1323 | uint8_t nsSfd_result = 0;
|
||
1324 | uint8_t useDWnsSFD = 0;
|
||
1325 | uint8_t chan = config->chan ; |
||
1326 | uint32_t regval ; |
||
1327 | uint16_t reg16 = lde_replicaCoeff[config->rxCode]; |
||
1328 | uint8_t prfIndex = config->prf - DWT_PRF_16M; |
||
1329 | uint8_t bw = ((chan == 4) || (chan == 7)) ? 1 : 0 ; // Select wide or narrow band |
||
1330 | |||
1331 | #ifdef DWT_API_ERROR_CHECK
|
||
1332 | assert(config->dataRate <= DWT_BR_6M8); |
||
1333 | assert(config->rxPAC <= DWT_PAC64); |
||
1334 | assert((chan >= 1) && (chan <= 7) && (chan != 6)); |
||
1335 | assert(((config->prf == DWT_PRF_64M) && (config->txCode >= 9) && (config->txCode <= 24)) |
||
1336 | || ((config->prf == DWT_PRF_16M) && (config->txCode >= 1) && (config->txCode <= 8))); |
||
1337 | assert(((config->prf == DWT_PRF_64M) && (config->rxCode >= 9) && (config->rxCode <= 24)) |
||
1338 | || ((config->prf == DWT_PRF_16M) && (config->rxCode >= 1) && (config->rxCode <= 8))); |
||
1339 | assert((config->txPreambLength == DWT_PLEN_64) || (config->txPreambLength == DWT_PLEN_128) || (config->txPreambLength == DWT_PLEN_256) |
||
1340 | || (config->txPreambLength == DWT_PLEN_512) || (config->txPreambLength == DWT_PLEN_1024) || (config->txPreambLength == DWT_PLEN_1536) |
||
1341 | || (config->txPreambLength == DWT_PLEN_2048) || (config->txPreambLength == DWT_PLEN_4096)); |
||
1342 | assert((config->phrMode == DWT_PHRMODE_STD) || (config->phrMode == DWT_PHRMODE_EXT)); |
||
1343 | #endif
|
||
1344 | |||
1345 | // For 110 kbps we need a special setup
|
||
1346 | if(DWT_BR_110K == config->dataRate)
|
||
1347 | { |
||
1348 | pdw1000local->sysCFGreg |= SYS_CFG_RXM110K ; |
||
1349 | reg16 >>= 3; // lde_replicaCoeff must be divided by 8 |
||
1350 | } |
||
1351 | else
|
||
1352 | { |
||
1353 | pdw1000local->sysCFGreg &= (~SYS_CFG_RXM110K) ; |
||
1354 | } |
||
1355 | |||
1356 | pdw1000local->longFrames = config->phrMode ; |
||
1357 | |||
1358 | pdw1000local->sysCFGreg &= ~SYS_CFG_PHR_MODE_11; |
||
1359 | pdw1000local->sysCFGreg |= (SYS_CFG_PHR_MODE_11 & (config->phrMode << SYS_CFG_PHR_MODE_SHFT)); |
||
1360 | |||
1361 | dwt_write32bitreg(SYS_CFG_ID,pdw1000local->sysCFGreg) ; |
||
1362 | // Set the lde_replicaCoeff
|
||
1363 | dwt_write16bitoffsetreg(LDE_IF_ID, LDE_REPC_OFFSET, reg16) ; |
||
1364 | |||
1365 | _dwt_configlde(prfIndex); |
||
1366 | |||
1367 | // Configure PLL2/RF PLL block CFG/TUNE (for a given channel)
|
||
1368 | dwt_write32bitoffsetreg(FS_CTRL_ID, FS_PLLCFG_OFFSET, fs_pll_cfg[chan_idx[chan]]); |
||
1369 | dwt_write8bitoffsetreg(FS_CTRL_ID, FS_PLLTUNE_OFFSET, fs_pll_tune[chan_idx[chan]]); |
||
1370 | |||
1371 | // Configure RF RX blocks (for specified channel/bandwidth)
|
||
1372 | dwt_write8bitoffsetreg(RF_CONF_ID, RF_RXCTRLH_OFFSET, rx_config[bw]); |
||
1373 | |||
1374 | // Configure RF TX blocks (for specified channel and PRF)
|
||
1375 | // Configure RF TX control
|
||
1376 | dwt_write32bitoffsetreg(RF_CONF_ID, RF_TXCTRL_OFFSET, tx_config[chan_idx[chan]]); |
||
1377 | |||
1378 | // Configure the baseband parameters (for specified PRF, bit rate, PAC, and SFD settings)
|
||
1379 | // DTUNE0
|
||
1380 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE0b_OFFSET, sftsh[config->dataRate][config->nsSFD]); |
||
1381 | |||
1382 | // DTUNE1
|
||
1383 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1a_OFFSET, dtune1[prfIndex]); |
||
1384 | |||
1385 | if(config->dataRate == DWT_BR_110K)
|
||
1386 | { |
||
1387 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_110K); |
||
1388 | } |
||
1389 | else
|
||
1390 | { |
||
1391 | if(config->txPreambLength == DWT_PLEN_64)
|
||
1392 | { |
||
1393 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_6M8_PRE64); |
||
1394 | dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE64); |
||
1395 | } |
||
1396 | else
|
||
1397 | { |
||
1398 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, DRX_TUNE1b_850K_6M8); |
||
1399 | dwt_write8bitoffsetreg(DRX_CONF_ID, DRX_TUNE4H_OFFSET, DRX_TUNE4H_PRE128PLUS); |
||
1400 | } |
||
1401 | } |
||
1402 | |||
1403 | // DTUNE2
|
||
1404 | dwt_write32bitoffsetreg(DRX_CONF_ID, DRX_TUNE2_OFFSET, digital_bb_config[prfIndex][config->rxPAC]); |
||
1405 | |||
1406 | // DTUNE3 (SFD timeout)
|
||
1407 | // Don't allow 0 - SFD timeout will always be enabled
|
||
1408 | if(config->sfdTO == 0) |
||
1409 | { |
||
1410 | config->sfdTO = DWT_SFDTOC_DEF; |
||
1411 | } |
||
1412 | dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_SFDTOC_OFFSET, config->sfdTO); |
||
1413 | |||
1414 | // Configure AGC parameters
|
||
1415 | dwt_write32bitoffsetreg( AGC_CFG_STS_ID, 0xC, agc_config.lo32);
|
||
1416 | dwt_write16bitoffsetreg( AGC_CFG_STS_ID, 0x4, agc_config.target[prfIndex]);
|
||
1417 | |||
1418 | // Set (non-standard) user SFD for improved performance,
|
||
1419 | if(config->nsSFD)
|
||
1420 | { |
||
1421 | // Write non standard (DW) SFD length
|
||
1422 | dwt_write8bitoffsetreg(USR_SFD_ID, 0x00, dwnsSFDlen[config->dataRate]);
|
||
1423 | nsSfd_result = 3 ;
|
||
1424 | useDWnsSFD = 1 ;
|
||
1425 | } |
||
1426 | regval = (CHAN_CTRL_TX_CHAN_MASK & (chan << CHAN_CTRL_TX_CHAN_SHIFT)) | // Transmit Channel
|
||
1427 | (CHAN_CTRL_RX_CHAN_MASK & (chan << CHAN_CTRL_RX_CHAN_SHIFT)) | // Receive Channel
|
||
1428 | (CHAN_CTRL_RXFPRF_MASK & (config->prf << CHAN_CTRL_RXFPRF_SHIFT)) | // RX PRF
|
||
1429 | ((CHAN_CTRL_TNSSFD|CHAN_CTRL_RNSSFD) & (nsSfd_result << CHAN_CTRL_TNSSFD_SHIFT)) | // nsSFD enable RX&TX
|
||
1430 | (CHAN_CTRL_DWSFD & (useDWnsSFD << CHAN_CTRL_DWSFD_SHIFT)) | // Use DW nsSFD
|
||
1431 | (CHAN_CTRL_TX_PCOD_MASK & (config->txCode << CHAN_CTRL_TX_PCOD_SHIFT)) | // TX Preamble Code
|
||
1432 | (CHAN_CTRL_RX_PCOD_MASK & (config->rxCode << CHAN_CTRL_RX_PCOD_SHIFT)) ; // RX Preamble Code
|
||
1433 | |||
1434 | dwt_write32bitreg(CHAN_CTRL_ID,regval) ; |
||
1435 | |||
1436 | // Set up TX Preamble Size, PRF and Data Rate
|
||
1437 | pdw1000local->txFCTRL = ((config->txPreambLength | config->prf) << TX_FCTRL_TXPRF_SHFT) | (config->dataRate << TX_FCTRL_TXBR_SHFT); |
||
1438 | dwt_write32bitreg(TX_FCTRL_ID, pdw1000local->txFCTRL); |
||
1439 | |||
1440 | // The SFD transmit pattern is initialised by the DW1000 upon a user TX request, but (due to an IC issue) it is not done for an auto-ACK TX. The
|
||
1441 | // SYS_CTRL write below works around this issue, by simultaneously initiating and aborting a transmission, which correctly initialises the SFD
|
||
1442 | // after its configuration or reconfiguration.
|
||
1443 | // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
|
||
1444 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, SYS_CTRL_TXSTRT | SYS_CTRL_TRXOFF); // Request TX start and TRX off at the same time
|
||
1445 | } // end dwt_configure()
|
||
1446 | |||
1447 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1448 | * @fn dwt_setrxantennadelay()
|
||
1449 | *
|
||
1450 | * @brief This API function writes the antenna delay (in time units) to RX registers
|
||
1451 | *
|
||
1452 | * input parameters:
|
||
1453 | * @param rxDelay - this is the total (RX) antenna delay value, which
|
||
1454 | * will be programmed into the RX register
|
||
1455 | *
|
||
1456 | * output parameters
|
||
1457 | *
|
||
1458 | * no return value
|
||
1459 | */
|
||
1460 | void dwt_setrxantennadelay(uint16_t rxDelay)
|
||
1461 | { |
||
1462 | // Set the RX antenna delay for auto TX timestamp adjustment
|
||
1463 | dwt_write16bitoffsetreg(LDE_IF_ID, LDE_RXANTD_OFFSET, rxDelay); |
||
1464 | } |
||
1465 | |||
1466 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1467 | * @fn dwt_settxantennadelay()
|
||
1468 | *
|
||
1469 | * @brief This API function writes the antenna delay (in time units) to TX registers
|
||
1470 | *
|
||
1471 | * input parameters:
|
||
1472 | * @param txDelay - this is the total (TX) antenna delay value, which
|
||
1473 | * will be programmed into the TX delay register
|
||
1474 | *
|
||
1475 | * output parameters
|
||
1476 | *
|
||
1477 | * no return value
|
||
1478 | */
|
||
1479 | void dwt_settxantennadelay(uint16_t txDelay)
|
||
1480 | { |
||
1481 | // Set the TX antenna delay for auto TX timestamp adjustment
|
||
1482 | dwt_write16bitoffsetreg(TX_ANTD_ID, TX_ANTD_OFFSET, txDelay); |
||
1483 | } |
||
1484 | |||
1485 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1486 | * @fn dwt_writetxdata()
|
||
1487 | *
|
||
1488 | * @brief This API function writes the supplied TX data into the DW1000's
|
||
1489 | * TX buffer. The input parameters are the data length in bytes and a pointer
|
||
1490 | * to those data bytes.
|
||
1491 | *
|
||
1492 | * input parameters
|
||
1493 | * @param txFrameLength - This is the total frame length, including the two byte CRC.
|
||
1494 | * Note: this is the length of TX message (including the 2 byte CRC) - max is 1023
|
||
1495 | * standard PHR mode allows up to 127 bytes
|
||
1496 | * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
|
||
1497 | * see dwt_configure function
|
||
1498 | * @param txFrameBytes - Pointer to the user’s buffer containing the data to send.
|
||
1499 | * @param txBufferOffset - This specifies an offset in the DW1000’s TX Buffer at which to start writing data.
|
||
1500 | *
|
||
1501 | * output parameters
|
||
1502 | *
|
||
1503 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
1504 | */
|
||
1505 | int dwt_writetxdata(uint16_t txFrameLength, uint8_t *txFrameBytes, uint16_t txBufferOffset)
|
||
1506 | { |
||
1507 | #ifdef DWT_API_ERROR_CHECK
|
||
1508 | assert(txFrameLength >= 2);
|
||
1509 | assert((pdw1000local->longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127)); |
||
1510 | assert((txBufferOffset + txFrameLength) <= 1024);
|
||
1511 | #endif
|
||
1512 | |||
1513 | if ((txBufferOffset + txFrameLength) <= 1024) |
||
1514 | { |
||
1515 | // Write the data to the IC TX buffer, (-2 bytes for auto generated CRC)
|
||
1516 | dwt_writetodevice( TX_BUFFER_ID, txBufferOffset, txFrameLength-2, txFrameBytes);
|
||
1517 | return DWT_SUCCESS;
|
||
1518 | } |
||
1519 | else
|
||
1520 | { |
||
1521 | return DWT_ERROR;
|
||
1522 | } |
||
1523 | } // end dwt_writetxdata()
|
||
1524 | |||
1525 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1526 | * @fn dwt_writetxfctrl()
|
||
1527 | *
|
||
1528 | * @brief This API function configures the TX frame control register before the transmission of a frame
|
||
1529 | *
|
||
1530 | * input parameters:
|
||
1531 | * @param txFrameLength - this is the length of TX message (including the 2 byte CRC) - max is 1023
|
||
1532 | * NOTE: standard PHR mode allows up to 127 bytes
|
||
1533 | * if > 127 is programmed, DWT_PHRMODE_EXT needs to be set in the phrMode configuration
|
||
1534 | * see dwt_configure function
|
||
1535 | * @param txBufferOffset - the offset in the tx buffer to start writing the data
|
||
1536 | * @param ranging - 1 if this is a ranging frame, else 0
|
||
1537 | *
|
||
1538 | * output parameters
|
||
1539 | *
|
||
1540 | * no return value
|
||
1541 | */
|
||
1542 | void dwt_writetxfctrl(uint16_t txFrameLength, uint16_t txBufferOffset, int ranging) |
||
1543 | { |
||
1544 | |||
1545 | #ifdef DWT_API_ERROR_CHECK
|
||
1546 | assert((pdw1000local->longFrames && (txFrameLength <= 1023)) || (txFrameLength <= 127)); |
||
1547 | #endif
|
||
1548 | |||
1549 | // Write the frame length to the TX frame control register
|
||
1550 | // pdw1000local->txFCTRL has kept configured bit rate information
|
||
1551 | uint32_t reg32 = pdw1000local->txFCTRL | txFrameLength | (txBufferOffset << TX_FCTRL_TXBOFFS_SHFT) | (ranging << TX_FCTRL_TR_SHFT); |
||
1552 | dwt_write32bitreg(TX_FCTRL_ID, reg32); |
||
1553 | } // end dwt_writetxfctrl()
|
||
1554 | |||
1555 | |||
1556 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1557 | * @fn dwt_readrxdata()
|
||
1558 | *
|
||
1559 | * @brief This is used to read the data from the RX buffer, from an offset location give by offset parameter
|
||
1560 | *
|
||
1561 | * input parameters
|
||
1562 | * @param buffer - the buffer into which the data will be read
|
||
1563 | * @param length - the length of data to read (in bytes)
|
||
1564 | * @param rxBufferOffset - the offset in the rx buffer from which to read the data
|
||
1565 | *
|
||
1566 | * output parameters
|
||
1567 | *
|
||
1568 | * no return value
|
||
1569 | */
|
||
1570 | void dwt_readrxdata(uint8_t *buffer, uint16_t length, uint16_t rxBufferOffset)
|
||
1571 | { |
||
1572 | dwt_readfromdevice(RX_BUFFER_ID,rxBufferOffset,length,buffer) ; |
||
1573 | } |
||
1574 | |||
1575 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1576 | * @fn dwt_readaccdata()
|
||
1577 | *
|
||
1578 | * @brief This is used to read the data from the Accumulator buffer, from an offset location give by offset parameter
|
||
1579 | *
|
||
1580 | * NOTE: Because of an internal memory access delay when reading the accumulator the first octet output is a dummy octet
|
||
1581 | * that should be discarded. This is true no matter what sub-index the read begins at.
|
||
1582 | *
|
||
1583 | * input parameters
|
||
1584 | * @param buffer - the buffer into which the data will be read
|
||
1585 | * @param length - the length of data to read (in bytes)
|
||
1586 | * @param accOffset - the offset in the acc buffer from which to read the data
|
||
1587 | *
|
||
1588 | * output parameters
|
||
1589 | *
|
||
1590 | * no return value
|
||
1591 | */
|
||
1592 | void dwt_readaccdata(uint8_t *buffer, uint16_t len, uint16_t accOffset)
|
||
1593 | { |
||
1594 | // Force on the ACC clocks if we are sequenced
|
||
1595 | _dwt_enableclocks(READ_ACC_ON); |
||
1596 | |||
1597 | dwt_readfromdevice(ACC_MEM_ID,accOffset,len,buffer) ; |
||
1598 | |||
1599 | _dwt_enableclocks(READ_ACC_OFF); // Revert clocks back
|
||
1600 | } |
||
1601 | |||
1602 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1603 | * @fn dwt_readdiagnostics()
|
||
1604 | *
|
||
1605 | * @brief this function reads the RX signal quality diagnostic data
|
||
1606 | *
|
||
1607 | * input parameters
|
||
1608 | * @param diagnostics - diagnostic structure pointer, this will contain the diagnostic data read from the DW1000
|
||
1609 | *
|
||
1610 | * output parameters
|
||
1611 | *
|
||
1612 | * no return value
|
||
1613 | */
|
||
1614 | void dwt_readdiagnostics(dwt_rxdiag_t *diagnostics)
|
||
1615 | { |
||
1616 | // Read the HW FP index
|
||
1617 | diagnostics->firstPath = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_INDEX_OFFSET); |
||
1618 | |||
1619 | // LDE diagnostic data
|
||
1620 | diagnostics->maxNoise = dwt_read16bitoffsetreg(LDE_IF_ID, LDE_THRESH_OFFSET); |
||
1621 | |||
1622 | // Read all 8 bytes in one SPI transaction
|
||
1623 | dwt_readfromdevice(RX_FQUAL_ID, 0x0, 8, (uint8_t*)&diagnostics->stdNoise); |
||
1624 | |||
1625 | diagnostics->firstPathAmp1 = dwt_read16bitoffsetreg(RX_TIME_ID, RX_TIME_FP_AMPL1_OFFSET); |
||
1626 | |||
1627 | diagnostics->rxPreamCount = (dwt_read32bitreg(RX_FINFO_ID) & RX_FINFO_RXPACC_MASK) >> RX_FINFO_RXPACC_SHIFT ; |
||
1628 | } |
||
1629 | |||
1630 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1631 | * @fn dwt_readtxtimestamp()
|
||
1632 | *
|
||
1633 | * @brief This is used to read the TX timestamp (adjusted with the programmed antenna delay)
|
||
1634 | *
|
||
1635 | * input parameters
|
||
1636 | * @param timestamp - a pointer to a 5-byte buffer which will store the read TX timestamp time
|
||
1637 | *
|
||
1638 | * output parameters - the timestamp buffer will contain the value after the function call
|
||
1639 | *
|
||
1640 | * no return value
|
||
1641 | */
|
||
1642 | void dwt_readtxtimestamp(uint8_t * timestamp)
|
||
1643 | { |
||
1644 | dwt_readfromdevice(TX_TIME_ID, TX_TIME_TX_STAMP_OFFSET, TX_TIME_TX_STAMP_LEN, timestamp) ; // Read bytes directly into buffer
|
||
1645 | } |
||
1646 | |||
1647 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1648 | * @fn dwt_readtxtimestamphi32()
|
||
1649 | *
|
||
1650 | * @brief This is used to read the high 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
|
||
1651 | *
|
||
1652 | * input parameters
|
||
1653 | *
|
||
1654 | * output parameters
|
||
1655 | *
|
||
1656 | * returns high 32-bits of TX timestamp
|
||
1657 | */
|
||
1658 | uint32_t dwt_readtxtimestamphi32(void)
|
||
1659 | { |
||
1660 | return dwt_read32bitoffsetreg(TX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5 |
||
1661 | } |
||
1662 | |||
1663 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1664 | * @fn dwt_readtxtimestamplo32()
|
||
1665 | *
|
||
1666 | * @brief This is used to read the low 32-bits of the TX timestamp (adjusted with the programmed antenna delay)
|
||
1667 | *
|
||
1668 | * input parameters
|
||
1669 | *
|
||
1670 | * output parameters
|
||
1671 | *
|
||
1672 | * returns low 32-bits of TX timestamp
|
||
1673 | */
|
||
1674 | uint32_t dwt_readtxtimestamplo32(void)
|
||
1675 | { |
||
1676 | return dwt_read32bitreg(TX_TIME_ID); // Read TX TIME as a 32-bit register to get the 4 lower bytes out of 5 |
||
1677 | } |
||
1678 | |||
1679 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1680 | * @fn dwt_readrxtimestamp()
|
||
1681 | *
|
||
1682 | * @brief This is used to read the RX timestamp (adjusted time of arrival)
|
||
1683 | *
|
||
1684 | * input parameters
|
||
1685 | * @param timestamp - a pointer to a 5-byte buffer which will store the read RX timestamp time
|
||
1686 | *
|
||
1687 | * output parameters - the timestamp buffer will contain the value after the function call
|
||
1688 | *
|
||
1689 | * no return value
|
||
1690 | */
|
||
1691 | void dwt_readrxtimestamp(uint8_t * timestamp)
|
||
1692 | { |
||
1693 | dwt_readfromdevice(RX_TIME_ID, RX_TIME_RX_STAMP_OFFSET, RX_TIME_RX_STAMP_LEN, timestamp) ; // Get the adjusted time of arrival
|
||
1694 | } |
||
1695 | |||
1696 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1697 | * @fn dwt_readrxtimestamphi32()
|
||
1698 | *
|
||
1699 | * @brief This is used to read the high 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
|
||
1700 | *
|
||
1701 | * input parameters
|
||
1702 | *
|
||
1703 | * output parameters
|
||
1704 | *
|
||
1705 | * returns high 32-bits of RX timestamp
|
||
1706 | */
|
||
1707 | uint32_t dwt_readrxtimestamphi32(void)
|
||
1708 | { |
||
1709 | return dwt_read32bitoffsetreg(RX_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5 |
||
1710 | } |
||
1711 | |||
1712 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1713 | * @fn dwt_readrxtimestamplo32()
|
||
1714 | *
|
||
1715 | * @brief This is used to read the low 32-bits of the RX timestamp (adjusted with the programmed antenna delay)
|
||
1716 | *
|
||
1717 | * input parameters
|
||
1718 | *
|
||
1719 | * output parameters
|
||
1720 | *
|
||
1721 | * returns low 32-bits of RX timestamp
|
||
1722 | */
|
||
1723 | uint32_t dwt_readrxtimestamplo32(void)
|
||
1724 | { |
||
1725 | return dwt_read32bitreg(RX_TIME_ID); // Read RX TIME as a 32-bit register to get the 4 lower bytes out of 5 |
||
1726 | } |
||
1727 | |||
1728 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1729 | * @fn dwt_readsystimestamphi32()
|
||
1730 | *
|
||
1731 | * @brief This is used to read the high 32-bits of the system time
|
||
1732 | *
|
||
1733 | * input parameters
|
||
1734 | *
|
||
1735 | * output parameters
|
||
1736 | *
|
||
1737 | * returns high 32-bits of system time timestamp
|
||
1738 | */
|
||
1739 | uint32_t dwt_readsystimestamphi32(void)
|
||
1740 | { |
||
1741 | return dwt_read32bitoffsetreg(SYS_TIME_ID, 1); // Offset is 1 to get the 4 upper bytes out of 5 |
||
1742 | } |
||
1743 | |||
1744 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1745 | * @fn dwt_readsystime()
|
||
1746 | *
|
||
1747 | * @brief This is used to read the system time
|
||
1748 | *
|
||
1749 | * input parameters
|
||
1750 | * @param timestamp - a pointer to a 5-byte buffer which will store the read system time
|
||
1751 | *
|
||
1752 | * output parameters
|
||
1753 | * @param timestamp - the timestamp buffer will contain the value after the function call
|
||
1754 | *
|
||
1755 | * no return value
|
||
1756 | */
|
||
1757 | void dwt_readsystime(uint8_t * timestamp)
|
||
1758 | { |
||
1759 | dwt_readfromdevice(SYS_TIME_ID, SYS_TIME_OFFSET, SYS_TIME_LEN, timestamp) ; |
||
1760 | } |
||
1761 | |||
1762 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1763 | * @fn dwt_writetodevice()
|
||
1764 | *
|
||
1765 | * @brief this function is used to write to the DW1000 device registers
|
||
1766 | * Notes:
|
||
1767 | * 1. Firstly we create a header (the first byte is a header byte)
|
||
1768 | * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
|
||
1769 | * b. set bit-7 (or with 0x80) for write operation
|
||
1770 | * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
|
||
1771 | *
|
||
1772 | * 2. Write the header followed by the data bytes to the DW1000 device
|
||
1773 | *
|
||
1774 | *
|
||
1775 | * input parameters:
|
||
1776 | * @param recordNumber - ID of register file or buffer being accessed
|
||
1777 | * @param index - byte index into register file or buffer being accessed
|
||
1778 | * @param length - number of bytes being written
|
||
1779 | * @param buffer - pointer to buffer containing the 'length' bytes to be written
|
||
1780 | *
|
||
1781 | * output parameters
|
||
1782 | *
|
||
1783 | * no return value
|
||
1784 | */
|
||
1785 | void dwt_writetodevice
|
||
1786 | ( |
||
1787 | uint16_t recordNumber, |
||
1788 | uint16_t index, |
||
1789 | uint32_t length, |
||
1790 | const uint8_t *buffer
|
||
1791 | ) |
||
1792 | { |
||
1793 | uint8_t header[3] ; // Buffer to compose header in |
||
1794 | int cnt = 0; // Counter for length of header |
||
1795 | #ifdef DWT_API_ERROR_CHECK
|
||
1796 | assert(recordNumber <= 0x3F); // Record number is limited to 6-bits. |
||
1797 | #endif
|
||
1798 | |||
1799 | // Write message header selecting WRITE operation and addresses as appropriate (this is one to three bytes long)
|
||
1800 | if (index == 0) // For index of 0, no sub-index is required |
||
1801 | { |
||
1802 | header[cnt++] = 0x80 | recordNumber ; // Bit-7 is WRITE operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id |
||
1803 | } |
||
1804 | else
|
||
1805 | { |
||
1806 | #ifdef DWT_API_ERROR_CHECK
|
||
1807 | assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits. |
||
1808 | #endif
|
||
1809 | header[cnt++] = 0xC0 | recordNumber ; // Bit-7 is WRITE operation, bit-6 one=sub-address follows, bits 5-0 is reg file id |
||
1810 | |||
1811 | if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required |
||
1812 | { |
||
1813 | header[cnt++] = (uint8_t)index ; // Bit-7 zero means no extension, bits 6-0 is index.
|
||
1814 | } |
||
1815 | else
|
||
1816 | { |
||
1817 | header[cnt++] = 0x80 | (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index. |
||
1818 | header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index. |
||
1819 | } |
||
1820 | } |
||
1821 | |||
1822 | // Write it to the SPI
|
||
1823 | _alld_dw1000_writespi(cnt,header,length,buffer); |
||
1824 | } // end dwt_writetodevice()
|
||
1825 | |||
1826 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1827 | * @fn dwt_readfromdevice()
|
||
1828 | *
|
||
1829 | * @brief this function is used to read from the DW1000 device registers
|
||
1830 | * Notes:
|
||
1831 | * 1. Firstly we create a header (the first byte is a header byte)
|
||
1832 | * a. check if sub index is used, if subindexing is used - set bit-6 to 1 to signify that the sub-index address follows the register index byte
|
||
1833 | * b. set bit-7 (or with 0x80) for write operation
|
||
1834 | * c. if extended sub address index is used (i.e. if index > 127) set bit-7 of the first sub-index byte following the first header byte
|
||
1835 | *
|
||
1836 | * 2. Write the header followed by the data bytes to the DW1000 device
|
||
1837 | * 3. Store the read data in the input buffer
|
||
1838 | *
|
||
1839 | * input parameters:
|
||
1840 | * @param recordNumber - ID of register file or buffer being accessed
|
||
1841 | * @param index - byte index into register file or buffer being accessed
|
||
1842 | * @param length - number of bytes being read
|
||
1843 | * @param buffer - pointer to buffer in which to return the read data.
|
||
1844 | *
|
||
1845 | * output parameters
|
||
1846 | *
|
||
1847 | * no return value
|
||
1848 | */
|
||
1849 | void dwt_readfromdevice
|
||
1850 | ( |
||
1851 | uint16_t recordNumber, |
||
1852 | uint16_t index, |
||
1853 | uint32_t length, |
||
1854 | uint8_t *buffer |
||
1855 | ) |
||
1856 | { |
||
1857 | uint8_t header[3] ; // Buffer to compose header in |
||
1858 | int cnt = 0; // Counter for length of header |
||
1859 | #ifdef DWT_API_ERROR_CHECK
|
||
1860 | assert(recordNumber <= 0x3F); // Record number is limited to 6-bits. |
||
1861 | #endif
|
||
1862 | |||
1863 | // Write message header selecting READ operation and addresses as appropriate (this is one to three bytes long)
|
||
1864 | if (index == 0) // For index of 0, no sub-index is required |
||
1865 | { |
||
1866 | header[cnt++] = (uint8_t) recordNumber ; // Bit-7 zero is READ operation, bit-6 zero=NO sub-addressing, bits 5-0 is reg file id
|
||
1867 | } |
||
1868 | else
|
||
1869 | { |
||
1870 | #ifdef DWT_API_ERROR_CHECK
|
||
1871 | assert((index <= 0x7FFF) && ((index + length) <= 0x7FFF)); // Index and sub-addressable area are limited to 15-bits. |
||
1872 | #endif
|
||
1873 | header[cnt++] = (uint8_t)(0x40 | recordNumber) ; // Bit-7 zero is READ operation, bit-6 one=sub-address follows, bits 5-0 is reg file id |
||
1874 | |||
1875 | if (index <= 127) // For non-zero index < 127, just a single sub-index byte is required |
||
1876 | { |
||
1877 | header[cnt++] = (uint8_t) index ; // Bit-7 zero means no extension, bits 6-0 is index.
|
||
1878 | } |
||
1879 | else
|
||
1880 | { |
||
1881 | header[cnt++] = 0x80 | (uint8_t)(index) ; // Bit-7 one means extended index, bits 6-0 is low seven bits of index. |
||
1882 | header[cnt++] = (uint8_t) (index >> 7) ; // 8-bit value = high eight bits of index. |
||
1883 | } |
||
1884 | } |
||
1885 | |||
1886 | // Do the read from the SPI
|
||
1887 | _alld_dw1000_readspi(cnt, header, length, buffer); // result is stored in the buffer
|
||
1888 | } // end dwt_readfromdevice()
|
||
1889 | |||
1890 | |||
1891 | |||
1892 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1893 | * @fn dwt_read32bitoffsetreg()
|
||
1894 | *
|
||
1895 | * @brief this function is used to read 32-bit value from the DW1000 device registers
|
||
1896 | *
|
||
1897 | * input parameters:
|
||
1898 | * @param regFileID - ID of register file or buffer being accessed
|
||
1899 | * @param regOffset - the index into register file or buffer being accessed
|
||
1900 | *
|
||
1901 | * output parameters
|
||
1902 | *
|
||
1903 | * returns 32 bit register value
|
||
1904 | */
|
||
1905 | uint32_t dwt_read32bitoffsetreg(int regFileID,int regOffset) |
||
1906 | { |
||
1907 | uint32_t regval = 0 ;
|
||
1908 | int j ;
|
||
1909 | uint8_t buffer[4] ;
|
||
1910 | |||
1911 | dwt_readfromdevice(regFileID,regOffset,4,buffer); // Read 4 bytes (32-bits) register into buffer |
||
1912 | |||
1913 | for (j = 3 ; j >= 0 ; j --) |
||
1914 | { |
||
1915 | regval = (regval << 8) + buffer[j] ;
|
||
1916 | } |
||
1917 | return regval ;
|
||
1918 | |||
1919 | } // end dwt_read32bitoffsetreg()
|
||
1920 | |||
1921 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1922 | * @fn dwt_read16bitoffsetreg()
|
||
1923 | *
|
||
1924 | * @brief this function is used to read 16-bit value from the DW1000 device registers
|
||
1925 | *
|
||
1926 | * input parameters:
|
||
1927 | * @param regFileID - ID of register file or buffer being accessed
|
||
1928 | * @param regOffset - the index into register file or buffer being accessed
|
||
1929 | *
|
||
1930 | * output parameters
|
||
1931 | *
|
||
1932 | * returns 16 bit register value
|
||
1933 | */
|
||
1934 | uint16_t dwt_read16bitoffsetreg(int regFileID,int regOffset) |
||
1935 | { |
||
1936 | uint16_t regval = 0 ;
|
||
1937 | uint8_t buffer[2] ;
|
||
1938 | |||
1939 | dwt_readfromdevice(regFileID,regOffset,2,buffer); // Read 2 bytes (16-bits) register into buffer |
||
1940 | |||
1941 | regval = (buffer[1] << 8) + buffer[0] ; |
||
1942 | return regval ;
|
||
1943 | |||
1944 | } // end dwt_read16bitoffsetreg()
|
||
1945 | |||
1946 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1947 | * @fn dwt_read8bitoffsetreg()
|
||
1948 | *
|
||
1949 | * @brief this function is used to read an 8-bit value from the DW1000 device registers
|
||
1950 | *
|
||
1951 | * input parameters:
|
||
1952 | * @param regFileID - ID of register file or buffer being accessed
|
||
1953 | * @param regOffset - the index into register file or buffer being accessed
|
||
1954 | *
|
||
1955 | * output parameters
|
||
1956 | *
|
||
1957 | * returns 8-bit register value
|
||
1958 | */
|
||
1959 | uint8_t dwt_read8bitoffsetreg(int regFileID, int regOffset) |
||
1960 | { |
||
1961 | uint8_t regval; |
||
1962 | |||
1963 | dwt_readfromdevice(regFileID, regOffset, 1, ®val);
|
||
1964 | |||
1965 | return regval ;
|
||
1966 | } |
||
1967 | |||
1968 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1969 | * @fn dwt_write8bitoffsetreg()
|
||
1970 | *
|
||
1971 | * @brief this function is used to write an 8-bit value to the DW1000 device registers
|
||
1972 | *
|
||
1973 | * input parameters:
|
||
1974 | * @param regFileID - ID of register file or buffer being accessed
|
||
1975 | * @param regOffset - the index into register file or buffer being accessed
|
||
1976 | * @param regval - the value to write
|
||
1977 | *
|
||
1978 | * output parameters
|
||
1979 | *
|
||
1980 | * no return value
|
||
1981 | */
|
||
1982 | void dwt_write8bitoffsetreg(int regFileID, int regOffset, uint8_t regval) |
||
1983 | { |
||
1984 | dwt_writetodevice(regFileID, regOffset, 1, ®val);
|
||
1985 | } |
||
1986 | |||
1987 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
1988 | * @fn dwt_write16bitoffsetreg()
|
||
1989 | *
|
||
1990 | * @brief this function is used to write 16-bit value to the DW1000 device registers
|
||
1991 | *
|
||
1992 | * input parameters:
|
||
1993 | * @param regFileID - ID of register file or buffer being accessed
|
||
1994 | * @param regOffset - the index into register file or buffer being accessed
|
||
1995 | * @param regval - the value to write
|
||
1996 | *
|
||
1997 | * output parameters
|
||
1998 | *
|
||
1999 | * no return value
|
||
2000 | */
|
||
2001 | void dwt_write16bitoffsetreg(int regFileID,int regOffset,uint16_t regval) |
||
2002 | { |
||
2003 | uint8_t buffer[2] ;
|
||
2004 | |||
2005 | buffer[0] = regval & 0xFF; |
||
2006 | buffer[1] = regval >> 8 ; |
||
2007 | |||
2008 | dwt_writetodevice(regFileID,regOffset,2,buffer);
|
||
2009 | } // end dwt_write16bitoffsetreg()
|
||
2010 | |||
2011 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2012 | * @fn dwt_write32bitoffsetreg()
|
||
2013 | *
|
||
2014 | * @brief this function is used to write 32-bit value to the DW1000 device registers
|
||
2015 | *
|
||
2016 | * input parameters:
|
||
2017 | * @param regFileID - ID of register file or buffer being accessed
|
||
2018 | * @param regOffset - the index into register file or buffer being accessed
|
||
2019 | * @param regval - the value to write
|
||
2020 | *
|
||
2021 | * output parameters
|
||
2022 | *
|
||
2023 | * no return value
|
||
2024 | */
|
||
2025 | void dwt_write32bitoffsetreg(int regFileID,int regOffset,uint32_t regval) |
||
2026 | { |
||
2027 | int j ;
|
||
2028 | uint8_t buffer[4] ;
|
||
2029 | |||
2030 | for ( j = 0 ; j < 4 ; j++ ) |
||
2031 | { |
||
2032 | buffer[j] = regval & 0xff ;
|
||
2033 | regval >>= 8 ;
|
||
2034 | } |
||
2035 | |||
2036 | dwt_writetodevice(regFileID,regOffset,4,buffer);
|
||
2037 | } // end dwt_write32bitoffsetreg()
|
||
2038 | |||
2039 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2040 | * @fn dwt_enableframefilter()
|
||
2041 | *
|
||
2042 | * @brief This is used to enable the frame filtering - (the default option is to
|
||
2043 | * accept any data and ACK frames with correct destination address
|
||
2044 | *
|
||
2045 | * input parameters
|
||
2046 | * @param - bitmask - enables/disables the frame filtering options according to
|
||
2047 | * DWT_FF_NOTYPE_EN 0x000 no frame types allowed
|
||
2048 | * DWT_FF_COORD_EN 0x002 behave as coordinator (can receive frames with no destination address (PAN ID has to match))
|
||
2049 | * DWT_FF_BEACON_EN 0x004 beacon frames allowed
|
||
2050 | * DWT_FF_DATA_EN 0x008 data frames allowed
|
||
2051 | * DWT_FF_ACK_EN 0x010 ack frames allowed
|
||
2052 | * DWT_FF_MAC_EN 0x020 mac control frames allowed
|
||
2053 | * DWT_FF_RSVD_EN 0x040 reserved frame types allowed
|
||
2054 | *
|
||
2055 | * output parameters
|
||
2056 | *
|
||
2057 | * no return value
|
||
2058 | */
|
||
2059 | void dwt_enableframefilter(uint16_t enable)
|
||
2060 | { |
||
2061 | uint32_t sysconfig = SYS_CFG_MASK & dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
|
||
2062 | |||
2063 | if(enable)
|
||
2064 | { |
||
2065 | // Enable frame filtering and configure frame types
|
||
2066 | sysconfig &= ~(SYS_CFG_FF_ALL_EN); // Clear all
|
||
2067 | sysconfig |= (enable & SYS_CFG_FF_ALL_EN) | SYS_CFG_FFE; |
||
2068 | } |
||
2069 | else
|
||
2070 | { |
||
2071 | sysconfig &= ~(SYS_CFG_FFE); |
||
2072 | } |
||
2073 | |||
2074 | pdw1000local->sysCFGreg = sysconfig ; |
||
2075 | dwt_write32bitreg(SYS_CFG_ID,sysconfig) ; |
||
2076 | } |
||
2077 | |||
2078 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2079 | * @fn dwt_setpanid()
|
||
2080 | *
|
||
2081 | * @brief This is used to set the PAN ID
|
||
2082 | *
|
||
2083 | * input parameters
|
||
2084 | * @param panID - this is the PAN ID
|
||
2085 | *
|
||
2086 | * output parameters
|
||
2087 | *
|
||
2088 | * no return value
|
||
2089 | */
|
||
2090 | void dwt_setpanid(uint16_t panID)
|
||
2091 | { |
||
2092 | // PAN ID is high 16 bits of register
|
||
2093 | dwt_write16bitoffsetreg(PANADR_ID, PANADR_PAN_ID_OFFSET, panID); |
||
2094 | } |
||
2095 | |||
2096 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2097 | * @fn dwt_setaddress16()
|
||
2098 | *
|
||
2099 | * @brief This is used to set 16-bit (short) address
|
||
2100 | *
|
||
2101 | * input parameters
|
||
2102 | * @param shortAddress - this sets the 16 bit short address
|
||
2103 | *
|
||
2104 | * output parameters
|
||
2105 | *
|
||
2106 | * no return value
|
||
2107 | */
|
||
2108 | void dwt_setaddress16(uint16_t shortAddress)
|
||
2109 | { |
||
2110 | // Short address into low 16 bits
|
||
2111 | dwt_write16bitoffsetreg(PANADR_ID, PANADR_SHORT_ADDR_OFFSET, shortAddress); |
||
2112 | } |
||
2113 | |||
2114 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2115 | * @fn dwt_seteui()
|
||
2116 | *
|
||
2117 | * @brief This is used to set the EUI 64-bit (long) address
|
||
2118 | *
|
||
2119 | * input parameters
|
||
2120 | * @param eui64 - this is the pointer to a buffer that contains the 64bit address
|
||
2121 | *
|
||
2122 | * output parameters
|
||
2123 | *
|
||
2124 | * no return value
|
||
2125 | */
|
||
2126 | void dwt_seteui(uint8_t *eui64)
|
||
2127 | { |
||
2128 | dwt_writetodevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64); |
||
2129 | } |
||
2130 | |||
2131 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2132 | * @fn dwt_geteui()
|
||
2133 | *
|
||
2134 | * @brief This is used to get the EUI 64-bit from the DW1000
|
||
2135 | *
|
||
2136 | * input parameters
|
||
2137 | * @param eui64 - this is the pointer to a buffer that will contain the read 64-bit EUI value
|
||
2138 | *
|
||
2139 | * output parameters
|
||
2140 | *
|
||
2141 | * no return value
|
||
2142 | */
|
||
2143 | void dwt_geteui(uint8_t *eui64)
|
||
2144 | { |
||
2145 | dwt_readfromdevice(EUI_64_ID, EUI_64_OFFSET, EUI_64_LEN, eui64); |
||
2146 | } |
||
2147 | |||
2148 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2149 | * @fn dwt_otpread()
|
||
2150 | *
|
||
2151 | * @brief This is used to read the OTP data from given address into provided array
|
||
2152 | *
|
||
2153 | * input parameters
|
||
2154 | * @param address - this is the OTP address to read from
|
||
2155 | * @param array - this is the pointer to the array into which to read the data
|
||
2156 | * @param length - this is the number of 32 bit words to read (array needs to be at least this length)
|
||
2157 | *
|
||
2158 | * output parameters
|
||
2159 | *
|
||
2160 | * no return value
|
||
2161 | */
|
||
2162 | void dwt_otpread(uint32_t address, uint32_t *array, uint8_t length)
|
||
2163 | { |
||
2164 | int i;
|
||
2165 | |||
2166 | _dwt_enableclocks(FORCE_SYS_XTI); // NOTE: Set system clock to XTAL - this is necessary to make sure the values read by _dwt_otpread are reliable
|
||
2167 | |||
2168 | for(i=0; i<length; i++) |
||
2169 | { |
||
2170 | array[i] = _dwt_otpread(address + i) ; |
||
2171 | } |
||
2172 | |||
2173 | _dwt_enableclocks(ENABLE_ALL_SEQ); // Restore system clock to PLL
|
||
2174 | |||
2175 | return ;
|
||
2176 | } |
||
2177 | |||
2178 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2179 | * @fn _dwt_otpread()
|
||
2180 | *
|
||
2181 | * @brief function to read the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
|
||
2182 | *
|
||
2183 | * input parameters
|
||
2184 | * @param address - address to read at
|
||
2185 | *
|
||
2186 | * output parameters
|
||
2187 | *
|
||
2188 | * returns the 32bit of read data
|
||
2189 | */
|
||
2190 | uint32_t _dwt_otpread(uint32_t address) |
||
2191 | { |
||
2192 | uint32_t ret_data; |
||
2193 | |||
2194 | // Write the address
|
||
2195 | dwt_write16bitoffsetreg(OTP_IF_ID, OTP_ADDR, address); |
||
2196 | |||
2197 | // Perform OTP Read - Manual read mode has to be set
|
||
2198 | dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_OTPREAD | OTP_CTRL_OTPRDEN); |
||
2199 | dwt_write8bitoffsetreg(OTP_IF_ID, OTP_CTRL, 0x00); // OTPREAD is self clearing but OTPRDEN is not |
||
2200 | |||
2201 | // Read read data, available 40ns after rising edge of OTP_READ
|
||
2202 | ret_data = dwt_read32bitoffsetreg(OTP_IF_ID, OTP_RDAT); |
||
2203 | |||
2204 | // Return the 32bit of read data
|
||
2205 | return ret_data;
|
||
2206 | } |
||
2207 | |||
2208 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2209 | * @fn _dwt_otpsetmrregs()
|
||
2210 | *
|
||
2211 | * @brief Configure the MR registers for initial programming (enable charge pump).
|
||
2212 | * Read margin is used to stress the read back from the
|
||
2213 | * programmed bit. In normal operation this is relaxed.
|
||
2214 | *
|
||
2215 | * input parameters
|
||
2216 | * @param mode - "0" : Reset all to 0x0: MRA=0x0000, MRB=0x0000, MR=0x0000
|
||
2217 | * "1" : Set for inital programming: MRA=0x9220, MRB=0x000E, MR=0x1024
|
||
2218 | * "2" : Set for soak programming: MRA=0x9220, MRB=0x0003, MR=0x1824
|
||
2219 | * "3" : High Vpp: MRA=0x9220, MRB=0x004E, MR=0x1824
|
||
2220 | * "4" : Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
|
||
2221 | * "5" : Array Clean: MRA=0x0049, MRB=0x0003, MR=0x0024
|
||
2222 | * "4" : Very Low Read Margin: MRA=0x0000, MRB=0x0003, MR=0x0000
|
||
2223 | *
|
||
2224 | * output parameters
|
||
2225 | *
|
||
2226 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
2227 | */
|
||
2228 | uint32_t _dwt_otpsetmrregs(int mode)
|
||
2229 | { |
||
2230 | uint8_t rd_buf[4];
|
||
2231 | uint8_t wr_buf[4];
|
||
2232 | uint32_t mra=0,mrb=0,mr=0; |
||
2233 | |||
2234 | // PROGRAMME MRA
|
||
2235 | // Set MRA, MODE_SEL
|
||
2236 | wr_buf[0] = 0x03; |
||
2237 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL+1,1,wr_buf); |
||
2238 | |||
2239 | // Load data
|
||
2240 | switch(mode&0x0f) { |
||
2241 | case 0x0 : |
||
2242 | mr =0x0000;
|
||
2243 | mra=0x0000;
|
||
2244 | mrb=0x0000;
|
||
2245 | break;
|
||
2246 | case 0x1 : |
||
2247 | mr =0x1024;
|
||
2248 | mra=0x9220; // Enable CPP mon |
||
2249 | mrb=0x000e;
|
||
2250 | break;
|
||
2251 | case 0x2 : |
||
2252 | mr =0x1824;
|
||
2253 | mra=0x9220;
|
||
2254 | mrb=0x0003;
|
||
2255 | break;
|
||
2256 | case 0x3 : |
||
2257 | mr =0x1824;
|
||
2258 | mra=0x9220;
|
||
2259 | mrb=0x004e;
|
||
2260 | break;
|
||
2261 | case 0x4 : |
||
2262 | mr =0x0000;
|
||
2263 | mra=0x0000;
|
||
2264 | mrb=0x0003;
|
||
2265 | break;
|
||
2266 | case 0x5 : |
||
2267 | mr =0x0024;
|
||
2268 | mra=0x0000;
|
||
2269 | mrb=0x0003;
|
||
2270 | break;
|
||
2271 | default :
|
||
2272 | return DWT_ERROR;
|
||
2273 | } |
||
2274 | |||
2275 | wr_buf[0] = mra & 0x00ff; |
||
2276 | wr_buf[1] = (mra & 0xff00)>>8; |
||
2277 | dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
|
||
2278 | |||
2279 | |||
2280 | // Set WRITE_MR
|
||
2281 | wr_buf[0] = 0x08; |
||
2282 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2283 | |||
2284 | // Wait?
|
||
2285 | |||
2286 | // Set Clear Mode sel
|
||
2287 | wr_buf[0] = 0x02; |
||
2288 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2289 | |||
2290 | // Set AUX update, write MR
|
||
2291 | wr_buf[0] = 0x88; |
||
2292 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2293 | // Clear write MR
|
||
2294 | wr_buf[0] = 0x80; |
||
2295 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2296 | // Clear AUX update
|
||
2297 | wr_buf[0] = 0x00; |
||
2298 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2299 | |||
2300 | ///////////////////////////////////////////
|
||
2301 | // PROGRAM MRB
|
||
2302 | // Set SLOW, MRB, MODE_SEL
|
||
2303 | wr_buf[0] = 0x05; |
||
2304 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2305 | |||
2306 | wr_buf[0] = mrb & 0x00ff; |
||
2307 | wr_buf[1] = (mrb & 0xff00)>>8; |
||
2308 | dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
|
||
2309 | |||
2310 | // Set WRITE_MR
|
||
2311 | wr_buf[0] = 0x08; |
||
2312 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2313 | |||
2314 | // Wait?
|
||
2315 | |||
2316 | // Set Clear Mode sel
|
||
2317 | wr_buf[0] = 0x04; |
||
2318 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2319 | |||
2320 | // Set AUX update, write MR
|
||
2321 | wr_buf[0] = 0x88; |
||
2322 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2323 | // Clear write MR
|
||
2324 | wr_buf[0] = 0x80; |
||
2325 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2326 | // Clear AUX update
|
||
2327 | wr_buf[0] = 0x00; |
||
2328 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2329 | |||
2330 | ///////////////////////////////////////////
|
||
2331 | // PROGRAM MR
|
||
2332 | // Set SLOW, MODE_SEL
|
||
2333 | wr_buf[0] = 0x01; |
||
2334 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2335 | // Load data
|
||
2336 | |||
2337 | wr_buf[0] = mr & 0x00ff; |
||
2338 | wr_buf[1] = (mr & 0xff00)>>8; |
||
2339 | dwt_writetodevice(OTP_IF_ID, OTP_WDAT,2,wr_buf);
|
||
2340 | |||
2341 | // Set WRITE_MR
|
||
2342 | wr_buf[0] = 0x08; |
||
2343 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2344 | |||
2345 | // Wait?
|
||
2346 | deca_sleep(10);
|
||
2347 | // Set Clear Mode sel
|
||
2348 | wr_buf[0] = 0x00; |
||
2349 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2350 | |||
2351 | // Read confirm mode writes.
|
||
2352 | // Set man override, MRA_SEL
|
||
2353 | wr_buf[0] = OTP_CTRL_OTPRDEN;
|
||
2354 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2355 | wr_buf[0] = 0x02; |
||
2356 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2357 | // MRB_SEL
|
||
2358 | wr_buf[0] = 0x04; |
||
2359 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2360 | deca_sleep(100);
|
||
2361 | |||
2362 | // Clear mode sel
|
||
2363 | wr_buf[0] = 0x00; |
||
2364 | dwt_writetodevice(OTP_IF_ID,OTP_CTRL+1,1,wr_buf); |
||
2365 | // Clear MAN_OVERRIDE
|
||
2366 | wr_buf[0] = 0x00; |
||
2367 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL,1,wr_buf);
|
||
2368 | |||
2369 | deca_sleep(10);
|
||
2370 | |||
2371 | if (((mode&0x0f) == 0x1)||((mode&0x0f) == 0x2)) |
||
2372 | { |
||
2373 | // Read status register
|
||
2374 | dwt_readfromdevice(OTP_IF_ID, OTP_STAT,1,rd_buf);
|
||
2375 | } |
||
2376 | |||
2377 | return DWT_SUCCESS;
|
||
2378 | } |
||
2379 | |||
2380 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2381 | * @fn _dwt_otpprogword32()
|
||
2382 | *
|
||
2383 | * @brief function to program the OTP memory. Ensure that MR,MRa,MRb are reset to 0.
|
||
2384 | * VNM Charge pump needs to be enabled (see _dwt_otpsetmrregs)
|
||
2385 | * Note the address is only 11 bits long.
|
||
2386 | *
|
||
2387 | * input parameters
|
||
2388 | * @param address - address to read at
|
||
2389 | *
|
||
2390 | * output parameters
|
||
2391 | *
|
||
2392 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
2393 | */
|
||
2394 | uint32_t _dwt_otpprogword32(uint32_t data, uint16_t address) |
||
2395 | { |
||
2396 | uint8_t rd_buf[1];
|
||
2397 | uint8_t wr_buf[4];
|
||
2398 | uint8_t otp_done; |
||
2399 | |||
2400 | // Read status register
|
||
2401 | dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
|
||
2402 | |||
2403 | if((rd_buf[0] & 0x02) != 0x02) |
||
2404 | { |
||
2405 | return DWT_ERROR;
|
||
2406 | } |
||
2407 | |||
2408 | // Write the data
|
||
2409 | wr_buf[3] = (data>>24) & 0xff; |
||
2410 | wr_buf[2] = (data>>16) & 0xff; |
||
2411 | wr_buf[1] = (data>>8) & 0xff; |
||
2412 | wr_buf[0] = data & 0xff; |
||
2413 | dwt_writetodevice(OTP_IF_ID, OTP_WDAT, 4, wr_buf);
|
||
2414 | |||
2415 | // Write the address [10:0]
|
||
2416 | wr_buf[1] = (address>>8) & 0x07; |
||
2417 | wr_buf[0] = address & 0xff; |
||
2418 | dwt_writetodevice(OTP_IF_ID, OTP_ADDR, 2, wr_buf);
|
||
2419 | |||
2420 | // Enable Sequenced programming
|
||
2421 | wr_buf[0] = OTP_CTRL_OTPPROG;
|
||
2422 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
|
||
2423 | wr_buf[0] = 0x00; // And clear |
||
2424 | dwt_writetodevice(OTP_IF_ID, OTP_CTRL, 1, wr_buf);
|
||
2425 | |||
2426 | // WAIT for status to flag PRGM OK..
|
||
2427 | otp_done = 0;
|
||
2428 | while(otp_done == 0) |
||
2429 | { |
||
2430 | deca_sleep(1);
|
||
2431 | dwt_readfromdevice(OTP_IF_ID, OTP_STAT, 1, rd_buf);
|
||
2432 | |||
2433 | if((rd_buf[0] & 0x01) == 0x01) |
||
2434 | { |
||
2435 | otp_done = 1;
|
||
2436 | } |
||
2437 | } |
||
2438 | |||
2439 | return DWT_SUCCESS;
|
||
2440 | } |
||
2441 | |||
2442 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2443 | * @fn dwt_otpwriteandverify()
|
||
2444 | *
|
||
2445 | * @brief This is used to program 32-bit value into the DW1000 OTP memory.
|
||
2446 | *
|
||
2447 | * input parameters
|
||
2448 | * @param value - this is the 32-bit value to be programmed into OTP
|
||
2449 | * @param address - this is the 16-bit OTP address into which the 32-bit value is programmed
|
||
2450 | *
|
||
2451 | * output parameters
|
||
2452 | *
|
||
2453 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
2454 | */
|
||
2455 | int dwt_otpwriteandverify(uint32_t value, uint16_t address)
|
||
2456 | { |
||
2457 | int prog_ok = DWT_SUCCESS;
|
||
2458 | int retry = 0; |
||
2459 | // Firstly set the system clock to crystal
|
||
2460 | _dwt_enableclocks(FORCE_SYS_XTI); //set system clock to XTI
|
||
2461 | |||
2462 | //
|
||
2463 | //!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!
|
||
2464 | //Set the supply to 3.7V
|
||
2465 | //
|
||
2466 | |||
2467 | _dwt_otpsetmrregs(1); // Set mode for programming |
||
2468 | |||
2469 | // For each value to program - the readback/check is done couple of times to verify it has programmed successfully
|
||
2470 | while(1) |
||
2471 | { |
||
2472 | _dwt_otpprogword32(value, address); |
||
2473 | |||
2474 | if(_dwt_otpread(address) == value)
|
||
2475 | { |
||
2476 | break;
|
||
2477 | } |
||
2478 | retry++; |
||
2479 | if(retry==5) |
||
2480 | { |
||
2481 | break;
|
||
2482 | } |
||
2483 | } |
||
2484 | |||
2485 | // Even if the above does not exit before retry reaches 5, the programming has probably been successful
|
||
2486 | |||
2487 | _dwt_otpsetmrregs(4); // Set mode for reading |
||
2488 | |||
2489 | if(_dwt_otpread(address) != value) // If this does not pass please check voltage supply on VDDIO |
||
2490 | { |
||
2491 | prog_ok = DWT_ERROR; |
||
2492 | } |
||
2493 | |||
2494 | _dwt_otpsetmrregs(0); // Setting OTP mode register for low RM read - resetting the device would be alternative |
||
2495 | |||
2496 | return prog_ok;
|
||
2497 | } |
||
2498 | |||
2499 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2500 | * @fn _dwt_aonconfigupload()
|
||
2501 | *
|
||
2502 | * @brief This function uploads always on (AON) configuration, as set in the AON_CFG0_OFFSET register.
|
||
2503 | *
|
||
2504 | * input parameters
|
||
2505 | *
|
||
2506 | * output parameters
|
||
2507 | *
|
||
2508 | * no return value
|
||
2509 | */
|
||
2510 | void _dwt_aonconfigupload(void) |
||
2511 | { |
||
2512 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_UPL_CFG); |
||
2513 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register |
||
2514 | } |
||
2515 | |||
2516 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2517 | * @fn _dwt_aonarrayupload()
|
||
2518 | *
|
||
2519 | * @brief This function uploads always on (AON) data array and configuration. Thus if this function is used, then _dwt_aonconfigupload
|
||
2520 | * is not necessary. The DW1000 will go so SLEEP straight after this if the DWT_SLP_EN has been set.
|
||
2521 | *
|
||
2522 | * input parameters
|
||
2523 | *
|
||
2524 | * output parameters
|
||
2525 | *
|
||
2526 | * no return value
|
||
2527 | */
|
||
2528 | void _dwt_aonarrayupload(void) |
||
2529 | { |
||
2530 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00); // Clear the register |
||
2531 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_SAVE); |
||
2532 | } |
||
2533 | |||
2534 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2535 | * @fn dwt_entersleep()
|
||
2536 | *
|
||
2537 | * @brief This function puts the device into deep sleep or sleep. dwt_configuresleep() should be called first
|
||
2538 | * to configure the sleep and on-wake/wake-up parameters
|
||
2539 | *
|
||
2540 | * input parameters
|
||
2541 | *
|
||
2542 | * output parameters
|
||
2543 | *
|
||
2544 | * no return value
|
||
2545 | */
|
||
2546 | void dwt_entersleep(void) |
||
2547 | { |
||
2548 | // Copy config to AON - upload the new configuration
|
||
2549 | _dwt_aonarrayupload(); |
||
2550 | } |
||
2551 | |||
2552 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2553 | * @fn dwt_configuresleepcnt()
|
||
2554 | *
|
||
2555 | * @brief sets the sleep counter to new value, this function programs the high 16-bits of the 28-bit counter
|
||
2556 | *
|
||
2557 | * NOTE: this function needs to be run before dwt_configuresleep, also the SPI frequency has to be < 3MHz
|
||
2558 | *
|
||
2559 | * input parameters
|
||
2560 | * @param sleepcnt - this it value of the sleep counter to program
|
||
2561 | *
|
||
2562 | * output parameters
|
||
2563 | *
|
||
2564 | * no return value
|
||
2565 | */
|
||
2566 | void dwt_configuresleepcnt(uint16_t sleepcnt)
|
||
2567 | { |
||
2568 | // Force system clock to crystal
|
||
2569 | _dwt_enableclocks(FORCE_SYS_XTI); |
||
2570 | |||
2571 | // Reset sleep configuration to make sure we don't accidentally go to sleep
|
||
2572 | dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, 0x00); // NB: this write change the default LPCLKDIVA value which is not used anyway. |
||
2573 | dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
|
||
2574 | |||
2575 | // Disable the sleep counter
|
||
2576 | _dwt_aonconfigupload(); |
||
2577 | |||
2578 | // Set new value
|
||
2579 | dwt_write16bitoffsetreg(AON_ID, AON_CFG0_OFFSET + AON_CFG0_SLEEP_TIM_OFFSET, sleepcnt); |
||
2580 | _dwt_aonconfigupload(); |
||
2581 | |||
2582 | // Enable the sleep counter
|
||
2583 | dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_SLEEP_CEN); |
||
2584 | _dwt_aonconfigupload(); |
||
2585 | |||
2586 | // Put system PLL back on
|
||
2587 | _dwt_enableclocks(ENABLE_ALL_SEQ); |
||
2588 | } |
||
2589 | |||
2590 | |||
2591 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2592 | * @fn dwt_calibratesleepcnt()
|
||
2593 | *
|
||
2594 | * @brief calibrates the local oscillator as its frequency can vary between 7 and 13kHz depending on temp and voltage
|
||
2595 | *
|
||
2596 | * NOTE: this function needs to be run before dwt_configuresleepcnt, so that we know what the counter units are
|
||
2597 | *
|
||
2598 | * input parameters
|
||
2599 | *
|
||
2600 | * output parameters
|
||
2601 | *
|
||
2602 | * returns the number of XTAL/2 cycles per low-power oscillator cycle. LP OSC frequency = 19.2 MHz/return value
|
||
2603 | */
|
||
2604 | uint16_t dwt_calibratesleepcnt(void)
|
||
2605 | { |
||
2606 | uint16_t result; |
||
2607 | |||
2608 | // Enable calibration of the sleep counter
|
||
2609 | dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, AON_CFG1_LPOSC_CAL); |
||
2610 | _dwt_aonconfigupload(); |
||
2611 | |||
2612 | // Disable calibration of the sleep counter
|
||
2613 | dwt_write8bitoffsetreg(AON_ID, AON_CFG1_OFFSET, 0x00);
|
||
2614 | _dwt_aonconfigupload(); |
||
2615 | |||
2616 | // Force system clock to crystal
|
||
2617 | _dwt_enableclocks(FORCE_SYS_XTI); |
||
2618 | |||
2619 | deca_sleep(1);
|
||
2620 | |||
2621 | // Read the number of XTAL/2 cycles one LP oscillator cycle took.
|
||
2622 | // Set up address - Read upper byte first
|
||
2623 | dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_1); |
||
2624 | |||
2625 | // Enable manual override
|
||
2626 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB); |
||
2627 | |||
2628 | // Read confirm data that was written
|
||
2629 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ); |
||
2630 | |||
2631 | // Read back byte from AON
|
||
2632 | result = dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET); |
||
2633 | result <<= 8;
|
||
2634 | |||
2635 | // Set up address - Read lower byte
|
||
2636 | dwt_write8bitoffsetreg(AON_ID, AON_ADDR_OFFSET, AON_ADDR_LPOSC_CAL_0); |
||
2637 | |||
2638 | // Enable manual override
|
||
2639 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB); |
||
2640 | |||
2641 | // Read confirm data that was written
|
||
2642 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, AON_CTRL_DCA_ENAB | AON_CTRL_DCA_READ); |
||
2643 | |||
2644 | // Read back byte from AON
|
||
2645 | result |= dwt_read8bitoffsetreg(AON_ID, AON_RDAT_OFFSET); |
||
2646 | |||
2647 | // Disable manual override
|
||
2648 | dwt_write8bitoffsetreg(AON_ID, AON_CTRL_OFFSET, 0x00);
|
||
2649 | |||
2650 | // Put system PLL back on
|
||
2651 | _dwt_enableclocks(ENABLE_ALL_SEQ); |
||
2652 | |||
2653 | // Returns the number of XTAL/2 cycles per one LP OSC cycle
|
||
2654 | // This can be converted into LP OSC frequency by 19.2 MHz/result
|
||
2655 | return result;
|
||
2656 | } |
||
2657 | |||
2658 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2659 | * @fn dwt_configuresleep()
|
||
2660 | *
|
||
2661 | * @brief configures the device for both DEEP_SLEEP and SLEEP modes, and on-wake mode
|
||
2662 | * i.e. before entering the sleep, the device should be programmed for TX or RX, then upon "waking up" the TX/RX settings
|
||
2663 | * will be preserved and the device can immediately perform the desired action TX/RX
|
||
2664 | *
|
||
2665 | * NOTE: e.g. Tag operation - after deep sleep, the device needs to just load the TX buffer and send the frame
|
||
2666 | *
|
||
2667 | *
|
||
2668 | * mode: the array and LDE code (OTP/ROM) and LDO tune, and set sleep persist
|
||
2669 | * DWT_PRESRV_SLEEP 0x0100 - preserve sleep
|
||
2670 | * DWT_LOADOPSET 0x0080 - load operating parameter set on wakeup
|
||
2671 | * DWT_CONFIG 0x0040 - download the AON array into the HIF (configuration download)
|
||
2672 | * DWT_LOADEUI 0x0008
|
||
2673 | * DWT_GOTORX 0x0002
|
||
2674 | * DWT_TANDV 0x0001
|
||
2675 | *
|
||
2676 | * wake: wake up parameters
|
||
2677 | * DWT_XTAL_EN 0x10 - keep XTAL running during sleep
|
||
2678 | * DWT_WAKE_SLPCNT 0x8 - wake up after sleep count
|
||
2679 | * DWT_WAKE_CS 0x4 - wake up on chip select
|
||
2680 | * DWT_WAKE_WK 0x2 - wake up on WAKEUP PIN
|
||
2681 | * DWT_SLP_EN 0x1 - enable sleep/deep sleep functionality
|
||
2682 | *
|
||
2683 | * input parameters
|
||
2684 | * @param mode - config on-wake parameters
|
||
2685 | * @param wake - config wake up parameters
|
||
2686 | *
|
||
2687 | * output parameters
|
||
2688 | *
|
||
2689 | * no return value
|
||
2690 | */
|
||
2691 | void dwt_configuresleep(uint16_t mode, uint8_t wake)
|
||
2692 | { |
||
2693 | // Add predefined sleep settings before writing the mode
|
||
2694 | mode |= pdw1000local->sleep_mode; |
||
2695 | dwt_write16bitoffsetreg(AON_ID, AON_WCFG_OFFSET, mode); |
||
2696 | |||
2697 | dwt_write8bitoffsetreg(AON_ID, AON_CFG0_OFFSET, wake); |
||
2698 | } |
||
2699 | |||
2700 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2701 | * @fn dwt_entersleepaftertx(int enable)
|
||
2702 | *
|
||
2703 | * @brief sets the auto TX to sleep bit. This means that after a frame
|
||
2704 | * transmission the device will enter deep sleep mode. The dwt_configuresleep() function
|
||
2705 | * needs to be called before this to configure the on-wake settings
|
||
2706 | *
|
||
2707 | * NOTE: the IRQ line has to be low/inactive (i.e. no pending events)
|
||
2708 | *
|
||
2709 | * input parameters
|
||
2710 | * @param enable - 1 to configure the device to enter deep sleep after TX, 0 - disables the configuration
|
||
2711 | *
|
||
2712 | * output parameters
|
||
2713 | *
|
||
2714 | * no return value
|
||
2715 | */
|
||
2716 | void dwt_entersleepaftertx(int enable) |
||
2717 | { |
||
2718 | uint32_t reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET); |
||
2719 | // Set the auto TX -> sleep bit
|
||
2720 | if(enable)
|
||
2721 | { |
||
2722 | reg |= PMSC_CTRL1_ATXSLP; |
||
2723 | } |
||
2724 | else
|
||
2725 | { |
||
2726 | reg &= ~(PMSC_CTRL1_ATXSLP); |
||
2727 | } |
||
2728 | dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, reg); |
||
2729 | } |
||
2730 | |||
2731 | |||
2732 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2733 | * @fn dwt_spicswakeup()
|
||
2734 | *
|
||
2735 | * @brief wake up the device from sleep mode using the SPI read,
|
||
2736 | * the device will wake up on chip select line going low if the line is held low for at least 500us.
|
||
2737 | * To define the length depending on the time one wants to hold
|
||
2738 | * the chip select line low, use the following formula:
|
||
2739 | *
|
||
2740 | * length (bytes) = time (s) * byte_rate (Hz)
|
||
2741 | *
|
||
2742 | * where fastest byte_rate is spi_rate (Hz) / 8 if the SPI is sending the bytes back-to-back.
|
||
2743 | * To save time and power, a system designer could determine byte_rate value more precisely.
|
||
2744 | *
|
||
2745 | * NOTE: Alternatively the device can be waken up with WAKE_UP pin if configured for that operation
|
||
2746 | *
|
||
2747 | * input parameters
|
||
2748 | * @param buff - this is a pointer to the dummy buffer which will be used in the SPI read transaction used for the WAKE UP of the device
|
||
2749 | * @param length - this is the length of the dummy buffer
|
||
2750 | *
|
||
2751 | * output parameters
|
||
2752 | *
|
||
2753 | * returns DWT_SUCCESS for success, or DWT_ERROR for error
|
||
2754 | */
|
||
2755 | int dwt_spicswakeup(uint8_t *buff, uint16_t length)
|
||
2756 | { |
||
2757 | if(dwt_readdevid() != DWT_DEVICE_ID) // Device was in deep sleep (the first read fails) |
||
2758 | { |
||
2759 | // Need to keep chip select line low for at least 500us
|
||
2760 | dwt_readfromdevice(0x0, 0x0, length, buff); // Do a long read to wake up the chip (hold the chip select low) |
||
2761 | |||
2762 | // Need 5ms for XTAL to start and stabilise (could wait for PLL lock IRQ status bit !!!)
|
||
2763 | // NOTE: Polling of the STATUS register is not possible unless frequency is < 3MHz
|
||
2764 | deca_sleep(5);
|
||
2765 | } |
||
2766 | else
|
||
2767 | { |
||
2768 | return DWT_SUCCESS;
|
||
2769 | } |
||
2770 | // DEBUG - check if still in sleep mode
|
||
2771 | if(dwt_readdevid() != DWT_DEVICE_ID)
|
||
2772 | { |
||
2773 | return DWT_ERROR;
|
||
2774 | } |
||
2775 | |||
2776 | return DWT_SUCCESS;
|
||
2777 | } |
||
2778 | |||
2779 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2780 | * @fn _dwt_configlde()
|
||
2781 | *
|
||
2782 | * @brief configure LDE algorithm parameters
|
||
2783 | *
|
||
2784 | * input parameters
|
||
2785 | * @param prf - this is the PRF index (0 or 1) 0 corresponds to 16 and 1 to 64 PRF
|
||
2786 | *
|
||
2787 | * output parameters
|
||
2788 | *
|
||
2789 | * no return value
|
||
2790 | */
|
||
2791 | void _dwt_configlde(int prfIndex) |
||
2792 | { |
||
2793 | dwt_write8bitoffsetreg(LDE_IF_ID, LDE_CFG1_OFFSET, LDE_PARAM1); // 8-bit configuration register
|
||
2794 | |||
2795 | if(prfIndex)
|
||
2796 | { |
||
2797 | dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_64); // 16-bit LDE configuration tuning register
|
||
2798 | } |
||
2799 | else
|
||
2800 | { |
||
2801 | dwt_write16bitoffsetreg( LDE_IF_ID, LDE_CFG2_OFFSET, (uint16_t) LDE_PARAM3_16); |
||
2802 | } |
||
2803 | } |
||
2804 | |||
2805 | |||
2806 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2807 | * @fn _dwt_loaducodefromrom()
|
||
2808 | *
|
||
2809 | * @brief load ucode from OTP MEMORY or ROM
|
||
2810 | *
|
||
2811 | * input parameters
|
||
2812 | *
|
||
2813 | * output parameters
|
||
2814 | *
|
||
2815 | * no return value
|
||
2816 | */
|
||
2817 | void _dwt_loaducodefromrom(void) |
||
2818 | { |
||
2819 | // Set up clocks
|
||
2820 | _dwt_enableclocks(FORCE_LDE); |
||
2821 | |||
2822 | // Kick off the LDE load
|
||
2823 | dwt_write16bitoffsetreg(OTP_IF_ID, OTP_CTRL, OTP_CTRL_LDELOAD); // Set load LDE kick bit
|
||
2824 | |||
2825 | deca_sleep(1); // Allow time for code to upload (should take up to 120 us) |
||
2826 | |||
2827 | // Default clocks (ENABLE_ALL_SEQ)
|
||
2828 | _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
|
||
2829 | } |
||
2830 | |||
2831 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2832 | * @fn dwt_loadopsettabfromotp()
|
||
2833 | *
|
||
2834 | * @brief This is used to select which Operational Parameter Set table to load from OTP memory
|
||
2835 | *
|
||
2836 | * input parameters
|
||
2837 | * @param ops_sel - Operational Parameter Set table to load:
|
||
2838 | * DWT_OPSET_64LEN = 0x0 - load the operational parameter set table for 64 length preamble configuration
|
||
2839 | * DWT_OPSET_TIGHT = 0x1 - load the operational parameter set table for tight xtal offsets (<1ppm)
|
||
2840 | * DWT_OPSET_DEFLT = 0x2 - load the default operational parameter set table (this is loaded from reset)
|
||
2841 | *
|
||
2842 | * output parameters
|
||
2843 | *
|
||
2844 | * no return value
|
||
2845 | */
|
||
2846 | void dwt_loadopsettabfromotp(uint8_t ops_sel)
|
||
2847 | { |
||
2848 | uint16_t reg = ((ops_sel << OTP_SF_OPS_SEL_SHFT) & OTP_SF_OPS_SEL_MASK) | OTP_SF_OPS_KICK; // Select defined OPS table and trigger its loading
|
||
2849 | |||
2850 | // Set up clocks
|
||
2851 | _dwt_enableclocks(FORCE_LDE); |
||
2852 | |||
2853 | dwt_write16bitoffsetreg(OTP_IF_ID, OTP_SF, reg); |
||
2854 | |||
2855 | // Default clocks (ENABLE_ALL_SEQ)
|
||
2856 | _dwt_enableclocks(ENABLE_ALL_SEQ); // Enable clocks for sequencing
|
||
2857 | |||
2858 | } |
||
2859 | |||
2860 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2861 | * @fn dwt_setsmarttxpower()
|
||
2862 | *
|
||
2863 | * @brief This call enables or disables the smart TX power feature.
|
||
2864 | *
|
||
2865 | * input parameters
|
||
2866 | * @param enable - this enables or disables the TX smart power (1 = enable, 0 = disable)
|
||
2867 | *
|
||
2868 | * output parameters
|
||
2869 | *
|
||
2870 | * no return value
|
||
2871 | */
|
||
2872 | void dwt_setsmarttxpower(int enable) |
||
2873 | { |
||
2874 | // Config system register
|
||
2875 | pdw1000local->sysCFGreg = dwt_read32bitreg(SYS_CFG_ID) ; // Read sysconfig register
|
||
2876 | |||
2877 | // Disable smart power configuration
|
||
2878 | if(enable)
|
||
2879 | { |
||
2880 | pdw1000local->sysCFGreg &= ~(SYS_CFG_DIS_STXP) ; |
||
2881 | } |
||
2882 | else
|
||
2883 | { |
||
2884 | pdw1000local->sysCFGreg |= SYS_CFG_DIS_STXP ; |
||
2885 | } |
||
2886 | |||
2887 | dwt_write32bitreg(SYS_CFG_ID,pdw1000local->sysCFGreg) ; |
||
2888 | } |
||
2889 | |||
2890 | |||
2891 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2892 | * @fn dwt_enableautoack()
|
||
2893 | *
|
||
2894 | * @brief This call enables the auto-ACK feature. If the responseDelayTime (parameter) is 0, the ACK will be sent a.s.a.p.
|
||
2895 | * otherwise it will be sent with a programmed delay (in symbols), max is 255.
|
||
2896 | * NOTE: needs to have frame filtering enabled as well
|
||
2897 | *
|
||
2898 | * input parameters
|
||
2899 | * @param responseDelayTime - if non-zero the ACK is sent after this delay, max is 255.
|
||
2900 | *
|
||
2901 | * output parameters
|
||
2902 | *
|
||
2903 | * no return value
|
||
2904 | */
|
||
2905 | void dwt_enableautoack(uint8_t responseDelayTime)
|
||
2906 | { |
||
2907 | // Set auto ACK reply delay
|
||
2908 | dwt_write8bitoffsetreg(ACK_RESP_T_ID, ACK_RESP_T_ACK_TIM_OFFSET, responseDelayTime); // In symbols
|
||
2909 | // Enable auto ACK
|
||
2910 | pdw1000local->sysCFGreg |= SYS_CFG_AUTOACK; |
||
2911 | dwt_write32bitreg(SYS_CFG_ID,pdw1000local->sysCFGreg) ; |
||
2912 | } |
||
2913 | |||
2914 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2915 | * @fn dwt_setdblrxbuffmode()
|
||
2916 | *
|
||
2917 | * @brief This call enables the double receive buffer mode
|
||
2918 | *
|
||
2919 | * input parameters
|
||
2920 | * @param enable - 1 to enable, 0 to disable the double buffer mode
|
||
2921 | *
|
||
2922 | * output parameters
|
||
2923 | *
|
||
2924 | * no return value
|
||
2925 | */
|
||
2926 | void dwt_setdblrxbuffmode(int enable) |
||
2927 | { |
||
2928 | if(enable)
|
||
2929 | { |
||
2930 | // Enable double RX buffer mode
|
||
2931 | pdw1000local->sysCFGreg &= ~SYS_CFG_DIS_DRXB; |
||
2932 | pdw1000local->dblbuffon = 1;
|
||
2933 | } |
||
2934 | else
|
||
2935 | { |
||
2936 | // Disable double RX buffer mode
|
||
2937 | pdw1000local->sysCFGreg |= SYS_CFG_DIS_DRXB; |
||
2938 | pdw1000local->dblbuffon = 0;
|
||
2939 | } |
||
2940 | |||
2941 | dwt_write32bitreg(SYS_CFG_ID,pdw1000local->sysCFGreg) ; |
||
2942 | } |
||
2943 | |||
2944 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2945 | * @fn dwt_setrxaftertxdelay()
|
||
2946 | *
|
||
2947 | * @brief This sets the receiver turn on delay time after a transmission of a frame
|
||
2948 | *
|
||
2949 | * input parameters
|
||
2950 | * @param rxDelayTime - (20 bits) - the delay is in UWB microseconds
|
||
2951 | *
|
||
2952 | * output parameters
|
||
2953 | *
|
||
2954 | * no return value
|
||
2955 | */
|
||
2956 | void dwt_setrxaftertxdelay(uint32_t rxDelayTime)
|
||
2957 | { |
||
2958 | uint32_t val = dwt_read32bitreg(ACK_RESP_T_ID) ; // Read ACK_RESP_T_ID register
|
||
2959 | |||
2960 | val &= ~(ACK_RESP_T_W4R_TIM_MASK) ; // Clear the timer (19:0)
|
||
2961 | |||
2962 | val |= (rxDelayTime & ACK_RESP_T_W4R_TIM_MASK) ; // In UWB microseconds (e.g. turn the receiver on 20uus after TX)
|
||
2963 | |||
2964 | dwt_write32bitreg(ACK_RESP_T_ID, val) ; |
||
2965 | } |
||
2966 | |||
2967 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2968 | * @fn dwt_setcallbacks()
|
||
2969 | *
|
||
2970 | * @brief This function is used to register the different callbacks called when one of the corresponding event occurs.
|
||
2971 | *
|
||
2972 | * NOTE: Callbacks can be undefined (set to NULL). In this case, dwt_isr() will process the event as usual but the 'null'
|
||
2973 | * callback will not be called.
|
||
2974 | *
|
||
2975 | * input parameters
|
||
2976 | * @param cbTxDone - the pointer to the TX confirmation event callback function
|
||
2977 | * @param cbRxOk - the pointer to the RX good frame event callback function
|
||
2978 | * @param cbRxTo - the pointer to the RX timeout events callback function
|
||
2979 | * @param cbRxErr - the pointer to the RX error events callback function
|
||
2980 | *
|
||
2981 | * output parameters
|
||
2982 | *
|
||
2983 | * no return value
|
||
2984 | */
|
||
2985 | void dwt_setcallbacks(dwt_cb_t cbTxDone, dwt_cb_t cbRxOk, dwt_cb_t cbRxTo, dwt_cb_t cbRxErr)
|
||
2986 | { |
||
2987 | pdw1000local->cbTxDone = cbTxDone; |
||
2988 | pdw1000local->cbRxOk = cbRxOk; |
||
2989 | pdw1000local->cbRxTo = cbRxTo; |
||
2990 | pdw1000local->cbRxErr = cbRxErr; |
||
2991 | } |
||
2992 | |||
2993 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
2994 | * @fn dwt_checkirq()
|
||
2995 | *
|
||
2996 | * @brief This function checks if the IRQ line is active - this is used instead of interrupt handler
|
||
2997 | *
|
||
2998 | * input parameters
|
||
2999 | *
|
||
3000 | * output parameters
|
||
3001 | *
|
||
3002 | * return value is 1 if the IRQS bit is set and 0 otherwise
|
||
3003 | */
|
||
3004 | uint8_t dwt_checkirq(void)
|
||
3005 | { |
||
3006 | return (dwt_read8bitoffsetreg(SYS_STATUS_ID, SYS_STATUS_OFFSET) & SYS_STATUS_IRQS); // Reading the lower byte only is enough for this operation |
||
3007 | } |
||
3008 | |||
3009 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3010 | * @fn dwt_isr()
|
||
3011 | *
|
||
3012 | * @brief This is the DW1000's general Interrupt Service Routine. It will process/report the following events:
|
||
3013 | * - RXFCG (through cbRxOk callback)
|
||
3014 | * - TXFRS (through cbTxDone callback)
|
||
3015 | * - RXRFTO/RXPTO (through cbRxTo callback)
|
||
3016 | * - RXPHE/RXFCE/RXRFSL/RXSFDTO/AFFREJ/LDEERR (through cbRxTo cbRxErr)
|
||
3017 | * For all events, corresponding interrupts are cleared and necessary resets are performed. In addition, in the RXFCG case,
|
||
3018 | * received frame information and frame control are read before calling the callback. If double buffering is activated, it
|
||
3019 | * will also toggle between reception buffers once the reception callback processing has ended.
|
||
3020 | *
|
||
3021 | * /!\ This version of the ISR supports double buffering but does not support automatic RX re-enabling!
|
||
3022 | *
|
||
3023 | * NOTE: In PC based system using (Cheetah or ARM) USB to SPI converter there can be no interrupts, however we still need something
|
||
3024 | * to take the place of it and operate in a polled way. In an embedded system this function should be configured to be triggered
|
||
3025 | * on any of the interrupts described above.
|
||
3026 | |||
3027 | * input parameters
|
||
3028 | *
|
||
3029 | * output parameters
|
||
3030 | *
|
||
3031 | * no return value
|
||
3032 | */
|
||
3033 | void dwt_isr(void) |
||
3034 | { |
||
3035 | uint32_t status = pdw1000local->cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
|
||
3036 | |||
3037 | // Handle RX good frame event
|
||
3038 | if(status & SYS_STATUS_RXFCG)
|
||
3039 | { |
||
3040 | uint16_t finfo16; |
||
3041 | uint16_t len; |
||
3042 | |||
3043 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
|
||
3044 | |||
3045 | pdw1000local->cbData.rx_flags = 0;
|
||
3046 | |||
3047 | // Read frame info - Only the first two bytes of the register are used here.
|
||
3048 | finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, RX_FINFO_OFFSET); |
||
3049 | |||
3050 | // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
|
||
3051 | len = finfo16 & RX_FINFO_RXFL_MASK_1023; |
||
3052 | if(pdw1000local->longFrames == 0) |
||
3053 | { |
||
3054 | len &= RX_FINFO_RXFLEN_MASK; |
||
3055 | } |
||
3056 | pdw1000local->cbData.datalength = len; |
||
3057 | |||
3058 | // Report ranging bit
|
||
3059 | if(finfo16 & RX_FINFO_RNG)
|
||
3060 | { |
||
3061 | pdw1000local->cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG; |
||
3062 | } |
||
3063 | |||
3064 | // Report frame control - First bytes of the received frame.
|
||
3065 | dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, pdw1000local->cbData.fctrl);
|
||
3066 | |||
3067 | // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
|
||
3068 | // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
|
||
3069 | // implementation works only for IEEE802.15.4-2011 compliant frames).
|
||
3070 | // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
|
||
3071 | if((status & SYS_STATUS_AAT) && ((pdw1000local->cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0)) |
||
3072 | { |
||
3073 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
|
||
3074 | pdw1000local->cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
|
||
3075 | pdw1000local->wait4resp = 0;
|
||
3076 | } |
||
3077 | |||
3078 | // Call the corresponding callback if present
|
||
3079 | if(pdw1000local->cbRxOk != NULL) |
||
3080 | { |
||
3081 | pdw1000local->cbRxOk(&pdw1000local->cbData); |
||
3082 | } |
||
3083 | |||
3084 | if (pdw1000local->dblbuffon)
|
||
3085 | { |
||
3086 | // Toggle the Host side Receive Buffer Pointer
|
||
3087 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET, 1);
|
||
3088 | } |
||
3089 | } |
||
3090 | |||
3091 | // Handle TX confirmation event
|
||
3092 | if(status & SYS_STATUS_TXFRS)
|
||
3093 | { |
||
3094 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_TX); // Clear TX event bits
|
||
3095 | |||
3096 | // In the case where this TXFRS interrupt is due to the automatic transmission of an ACK solicited by a response (with ACK request bit set)
|
||
3097 | // that we receive through using wait4resp to a previous TX (and assuming that the IRQ processing of that TX has already been handled), then
|
||
3098 | // we need to handle the IC issue which turns on the RX again in this situation (i.e. because it is wrongly applying the wait4resp after the
|
||
3099 | // ACK TX).
|
||
3100 | // See section "Transmit and automatically wait for response" in DW1000 User Manual
|
||
3101 | if((status & SYS_STATUS_AAT) && pdw1000local->wait4resp)
|
||
3102 | { |
||
3103 | dwt_forcetrxoff(); // Turn the RX off
|
||
3104 | dwt_rxreset(); // Reset in case we were late and a frame was already being received
|
||
3105 | } |
||
3106 | |||
3107 | // Call the corresponding callback if present
|
||
3108 | if(pdw1000local->cbTxDone != NULL) |
||
3109 | { |
||
3110 | pdw1000local->cbTxDone(&pdw1000local->cbData); |
||
3111 | } |
||
3112 | } |
||
3113 | |||
3114 | // Handle frame reception/preamble detect timeout events
|
||
3115 | if(status & SYS_STATUS_ALL_RX_TO)
|
||
3116 | { |
||
3117 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXRFTO); // Clear RX timeout event bits
|
||
3118 | |||
3119 | pdw1000local->wait4resp = 0;
|
||
3120 | |||
3121 | // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
|
||
3122 | // the next good frame's timestamp is computed correctly.
|
||
3123 | // See section "RX Message timestamp" in DW1000 User Manual.
|
||
3124 | dwt_forcetrxoff(); |
||
3125 | dwt_rxreset(); |
||
3126 | |||
3127 | // Call the corresponding callback if present
|
||
3128 | if(pdw1000local->cbRxTo != NULL) |
||
3129 | { |
||
3130 | pdw1000local->cbRxTo(&pdw1000local->cbData); |
||
3131 | } |
||
3132 | } |
||
3133 | |||
3134 | // Handle RX errors events
|
||
3135 | if(status & SYS_STATUS_ALL_RX_ERR)
|
||
3136 | { |
||
3137 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_ERR); // Clear RX error event bits
|
||
3138 | |||
3139 | pdw1000local->wait4resp = 0;
|
||
3140 | |||
3141 | // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure
|
||
3142 | // the next good frame's timestamp is computed correctly.
|
||
3143 | // See section "RX Message timestamp" in DW1000 User Manual.
|
||
3144 | dwt_forcetrxoff(); |
||
3145 | dwt_rxreset(); |
||
3146 | |||
3147 | // Call the corresponding callback if present
|
||
3148 | if(pdw1000local->cbRxErr != NULL) |
||
3149 | { |
||
3150 | pdw1000local->cbRxErr(&pdw1000local->cbData); |
||
3151 | } |
||
3152 | } |
||
3153 | } |
||
3154 | |||
3155 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3156 | * @fn dwt_isr_lplisten()
|
||
3157 | *
|
||
3158 | * @brief This is the DW1000's Interrupt Service Routine to use when low-power listening scheme is implemented. It will
|
||
3159 | * only process/report the RXFCG event (through cbRxOk callback).
|
||
3160 | * It clears RXFCG interrupt and reads received frame information and frame control before calling the callback.
|
||
3161 | *
|
||
3162 | * /!\ This version of the ISR is designed for single buffering case only!
|
||
3163 | *
|
||
3164 | * input parameters
|
||
3165 | *
|
||
3166 | * output parameters
|
||
3167 | *
|
||
3168 | * no return value
|
||
3169 | */
|
||
3170 | void dwt_lowpowerlistenisr(void) |
||
3171 | { |
||
3172 | uint32_t status = pdw1000local->cbData.status = dwt_read32bitreg(SYS_STATUS_ID); // Read status register low 32bits
|
||
3173 | uint16_t finfo16; |
||
3174 | uint16_t len; |
||
3175 | |||
3176 | // The only interrupt handled when in low-power listening mode is RX good frame so proceed directly to the handling of the received frame.
|
||
3177 | |||
3178 | // Deactivate low-power listening before clearing the interrupt. If not, the DW1000 will go back to sleep as soon as the interrupt is cleared.
|
||
3179 | dwt_setlowpowerlistening(0);
|
||
3180 | |||
3181 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_ALL_RX_GOOD); // Clear all receive status bits
|
||
3182 | |||
3183 | pdw1000local->cbData.rx_flags = 0;
|
||
3184 | |||
3185 | // Read frame info - Only the first two bytes of the register are used here.
|
||
3186 | finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, 0);
|
||
3187 | |||
3188 | // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes
|
||
3189 | len = finfo16 & RX_FINFO_RXFL_MASK_1023; |
||
3190 | if(pdw1000local->longFrames == 0) |
||
3191 | { |
||
3192 | len &= RX_FINFO_RXFLEN_MASK; |
||
3193 | } |
||
3194 | pdw1000local->cbData.datalength = len; |
||
3195 | |||
3196 | // Report ranging bit
|
||
3197 | if(finfo16 & RX_FINFO_RNG)
|
||
3198 | { |
||
3199 | pdw1000local->cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG; |
||
3200 | } |
||
3201 | |||
3202 | // Report frame control - First bytes of the received frame.
|
||
3203 | dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, pdw1000local->cbData.fctrl);
|
||
3204 | |||
3205 | // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for
|
||
3206 | // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this
|
||
3207 | // implementation works only for IEEE802.15.4-2011 compliant frames).
|
||
3208 | // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016).
|
||
3209 | if((status & SYS_STATUS_AAT) && ((pdw1000local->cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0)) |
||
3210 | { |
||
3211 | dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); // Clear AAT status bit in register
|
||
3212 | pdw1000local->cbData.status &= ~SYS_STATUS_AAT; // Clear AAT status bit in callback data register copy
|
||
3213 | pdw1000local->wait4resp = 0;
|
||
3214 | } |
||
3215 | |||
3216 | // Call the corresponding callback if present
|
||
3217 | if(pdw1000local->cbRxOk != NULL) |
||
3218 | { |
||
3219 | pdw1000local->cbRxOk(&pdw1000local->cbData); |
||
3220 | } |
||
3221 | } |
||
3222 | |||
3223 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3224 | * @fn dwt_setleds()
|
||
3225 | *
|
||
3226 | * @brief This is used to set up Tx/Rx GPIOs which could be used to control LEDs
|
||
3227 | * Note: not completely IC dependent, also needs board with LEDS fitted on right I/O lines
|
||
3228 | * this function enables GPIOs 2 and 3 which are connected to LED3 and LED4 on EVB1000
|
||
3229 | *
|
||
3230 | * input parameters
|
||
3231 | * @param mode - this is a bit field interpreted as follows:
|
||
3232 | * - bit 0: 1 to enable LEDs, 0 to disable them
|
||
3233 | * - bit 1: 1 to make LEDs blink once on init. Only valid if bit 0 is set (enable LEDs)
|
||
3234 | * - bit 2 to 7: reserved
|
||
3235 | *
|
||
3236 | * output parameters none
|
||
3237 | *
|
||
3238 | * no return value
|
||
3239 | */
|
||
3240 | void dwt_setleds(uint8_t mode)
|
||
3241 | { |
||
3242 | uint32_t reg; |
||
3243 | |||
3244 | if (mode & DWT_LEDS_ENABLE)
|
||
3245 | { |
||
3246 | // Set up MFIO for LED output.
|
||
3247 | reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET); |
||
3248 | reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK); |
||
3249 | reg |= (GPIO_PIN2_RXLED | GPIO_PIN3_TXLED); |
||
3250 | dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg); |
||
3251 | |||
3252 | // Enable LP Oscillator to run from counter and turn on de-bounce clock.
|
||
3253 | reg = dwt_read32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET); |
||
3254 | reg |= (PMSC_CTRL0_GPDCE | PMSC_CTRL0_KHZCLEN); |
||
3255 | dwt_write32bitoffsetreg(PMSC_ID, PMSC_CTRL0_OFFSET, reg); |
||
3256 | |||
3257 | // Enable LEDs to blink and set default blink time.
|
||
3258 | reg = PMSC_LEDC_BLNKEN | PMSC_LEDC_BLINK_TIME_DEF; |
||
3259 | // Make LEDs blink once if requested.
|
||
3260 | if (mode & DWT_LEDS_INIT_BLINK)
|
||
3261 | { |
||
3262 | reg |= PMSC_LEDC_BLINK_NOW_ALL; |
||
3263 | } |
||
3264 | dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg); |
||
3265 | // Clear force blink bits if needed.
|
||
3266 | if(mode & DWT_LEDS_INIT_BLINK)
|
||
3267 | { |
||
3268 | reg &= ~PMSC_LEDC_BLINK_NOW_ALL; |
||
3269 | dwt_write32bitoffsetreg(PMSC_ID, PMSC_LEDC_OFFSET, reg); |
||
3270 | } |
||
3271 | } |
||
3272 | else
|
||
3273 | { |
||
3274 | // Clear the GPIO bits that are used for LED control.
|
||
3275 | reg = dwt_read32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET); |
||
3276 | reg &= ~(GPIO_MSGP2_MASK | GPIO_MSGP3_MASK); |
||
3277 | dwt_write32bitoffsetreg(GPIO_CTRL_ID, GPIO_MODE_OFFSET, reg); |
||
3278 | } |
||
3279 | } |
||
3280 | |||
3281 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3282 | * @fn _dwt_enableclocks()
|
||
3283 | *
|
||
3284 | * @brief function to enable/disable clocks to particular digital blocks/system
|
||
3285 | *
|
||
3286 | * input parameters
|
||
3287 | * @param clocks - set of clocks to enable/disable
|
||
3288 | *
|
||
3289 | * output parameters none
|
||
3290 | *
|
||
3291 | * no return value
|
||
3292 | */
|
||
3293 | void _dwt_enableclocks(int clocks) |
||
3294 | { |
||
3295 | uint8_t reg[2];
|
||
3296 | |||
3297 | dwt_readfromdevice(PMSC_ID, PMSC_CTRL0_OFFSET, 2, reg);
|
||
3298 | switch(clocks)
|
||
3299 | { |
||
3300 | case ENABLE_ALL_SEQ:
|
||
3301 | { |
||
3302 | reg[0] = 0x00 ; |
||
3303 | reg[1] = reg[1] & 0xfe; |
||
3304 | } |
||
3305 | break;
|
||
3306 | case FORCE_SYS_XTI:
|
||
3307 | { |
||
3308 | // System and RX
|
||
3309 | reg[0] = 0x01 | (reg[0] & 0xfc); |
||
3310 | } |
||
3311 | break;
|
||
3312 | case FORCE_SYS_PLL:
|
||
3313 | { |
||
3314 | // System
|
||
3315 | reg[0] = 0x02 | (reg[0] & 0xfc); |
||
3316 | } |
||
3317 | break;
|
||
3318 | case READ_ACC_ON:
|
||
3319 | { |
||
3320 | reg[0] = 0x48 | (reg[0] & 0xb3); |
||
3321 | reg[1] = 0x80 | reg[1]; |
||
3322 | } |
||
3323 | break;
|
||
3324 | case READ_ACC_OFF:
|
||
3325 | { |
||
3326 | reg[0] = reg[0] & 0xb3; |
||
3327 | reg[1] = 0x7f & reg[1]; |
||
3328 | } |
||
3329 | break;
|
||
3330 | case FORCE_OTP_ON:
|
||
3331 | { |
||
3332 | reg[1] = 0x02 | reg[1]; |
||
3333 | } |
||
3334 | break;
|
||
3335 | case FORCE_OTP_OFF:
|
||
3336 | { |
||
3337 | reg[1] = reg[1] & 0xfd; |
||
3338 | } |
||
3339 | break;
|
||
3340 | case FORCE_TX_PLL:
|
||
3341 | { |
||
3342 | reg[0] = 0x20 | (reg[0] & 0xcf); |
||
3343 | } |
||
3344 | break;
|
||
3345 | case FORCE_LDE:
|
||
3346 | { |
||
3347 | reg[0] = 0x01; |
||
3348 | reg[1] = 0x03; |
||
3349 | } |
||
3350 | break;
|
||
3351 | default:
|
||
3352 | break;
|
||
3353 | } |
||
3354 | |||
3355 | |||
3356 | // Need to write lower byte separately before setting the higher byte(s)
|
||
3357 | dwt_writetodevice(PMSC_ID, PMSC_CTRL0_OFFSET, 1, ®[0]); |
||
3358 | dwt_writetodevice(PMSC_ID, 0x1, 1, ®[1]); |
||
3359 | |||
3360 | } // end _dwt_enableclocks()
|
||
3361 | |||
3362 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3363 | * @fn _dwt_disablesequencing()
|
||
3364 | *
|
||
3365 | * @brief This function disables the TX blocks sequencing, it disables PMSC control of RF blocks, system clock is also set to XTAL
|
||
3366 | *
|
||
3367 | * input parameters none
|
||
3368 | *
|
||
3369 | * output parameters none
|
||
3370 | *
|
||
3371 | * no return value
|
||
3372 | */
|
||
3373 | void _dwt_disablesequencing(void) // Disable sequencing and go to state "INIT" |
||
3374 | { |
||
3375 | _dwt_enableclocks(FORCE_SYS_XTI); // Set system clock to XTI
|
||
3376 | |||
3377 | dwt_write16bitoffsetreg(PMSC_ID, PMSC_CTRL1_OFFSET, PMSC_CTRL1_PKTSEQ_DISABLE); // Disable PMSC ctrl of RF and RX clk blocks
|
||
3378 | } |
||
3379 | |||
3380 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3381 | * @fn dwt_setdelayedtrxtime()
|
||
3382 | *
|
||
3383 | * @brief This API function configures the delayed transmit time or the delayed RX on time
|
||
3384 | *
|
||
3385 | * input parameters
|
||
3386 | * @param starttime - the TX/RX start time (the 32 bits should be the high 32 bits of the system time at which to send the message,
|
||
3387 | * or at which to turn on the receiver)
|
||
3388 | *
|
||
3389 | * output parameters none
|
||
3390 | *
|
||
3391 | * no return value
|
||
3392 | */
|
||
3393 | void dwt_setdelayedtrxtime(uint32_t starttime)
|
||
3394 | { |
||
3395 | dwt_write32bitoffsetreg(DX_TIME_ID, 1, starttime); // Write at offset 1 as the lower 9 bits of this register are ignored |
||
3396 | |||
3397 | } // end dwt_setdelayedtrxtime()
|
||
3398 | |||
3399 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3400 | * @fn dwt_starttx()
|
||
3401 | *
|
||
3402 | * @brief This call initiates the transmission, input parameter indicates which TX mode is used see below
|
||
3403 | *
|
||
3404 | * input parameters:
|
||
3405 | * @param mode - if 0 immediate TX (no response expected)
|
||
3406 | * if 1 delayed TX (no response expected)
|
||
3407 | * if 2 immediate TX (response expected - so the receiver will be automatically turned on after TX is done)
|
||
3408 | * if 3 delayed TX (response expected - so the receiver will be automatically turned on after TX is done)
|
||
3409 | *
|
||
3410 | * output parameters
|
||
3411 | *
|
||
3412 | * returns DWT_SUCCESS for success, or DWT_ERROR for error (e.g. a delayed transmission will fail if the delayed time has passed)
|
||
3413 | */
|
||
3414 | int dwt_starttx(uint8_t mode)
|
||
3415 | { |
||
3416 | int retval = DWT_SUCCESS ;
|
||
3417 | uint8_t temp = 0x00;
|
||
3418 | uint16_t checkTxOK = 0 ;
|
||
3419 | |||
3420 | if(mode & DWT_RESPONSE_EXPECTED)
|
||
3421 | { |
||
3422 | temp = (uint8_t)SYS_CTRL_WAIT4RESP ; // Set wait4response bit
|
||
3423 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp); |
||
3424 | pdw1000local->wait4resp = 1;
|
||
3425 | } |
||
3426 | |||
3427 | if (mode & DWT_START_TX_DELAYED)
|
||
3428 | { |
||
3429 | // Both SYS_CTRL_TXSTRT and SYS_CTRL_TXDLYS to correctly enable TX
|
||
3430 | temp |= (uint8_t)(SYS_CTRL_TXDLYS | SYS_CTRL_TXSTRT) ; |
||
3431 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp); |
||
3432 | checkTxOK = dwt_read16bitoffsetreg(SYS_STATUS_ID, 3); // Read at offset 3 to get the upper 2 bytes out of 5 |
||
3433 | if ((checkTxOK & SYS_STATUS_TXERR) == 0) // Transmit Delayed Send set over Half a Period away or Power Up error (there is enough time to send but not to power up individual blocks). |
||
3434 | { |
||
3435 | retval = DWT_SUCCESS ; // All okay
|
||
3436 | } |
||
3437 | else
|
||
3438 | { |
||
3439 | // I am taking DSHP set to Indicate that the TXDLYS was set too late for the specified DX_TIME.
|
||
3440 | // Remedial Action - (a) cancel delayed send
|
||
3441 | temp = (uint8_t)SYS_CTRL_TRXOFF; // This assumes the bit is in the lowest byte
|
||
3442 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp); |
||
3443 | // Note event Delayed TX Time too Late
|
||
3444 | // Could fall through to start a normal send (below) just sending late.....
|
||
3445 | // ... instead return and assume return value of 1 will be used to detect and recover from the issue.
|
||
3446 | pdw1000local->wait4resp = 0;
|
||
3447 | retval = DWT_ERROR ; // Failed !
|
||
3448 | } |
||
3449 | } |
||
3450 | else
|
||
3451 | { |
||
3452 | temp |= (uint8_t)SYS_CTRL_TXSTRT ; |
||
3453 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, temp); |
||
3454 | } |
||
3455 | |||
3456 | return retval;
|
||
3457 | |||
3458 | } // end dwt_starttx()
|
||
3459 | |||
3460 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3461 | * @fn dwt_forcetrxoff()
|
||
3462 | *
|
||
3463 | * @brief This is used to turn off the transceiver
|
||
3464 | *
|
||
3465 | * input parameters
|
||
3466 | *
|
||
3467 | * output parameters
|
||
3468 | *
|
||
3469 | * no return value
|
||
3470 | */
|
||
3471 | void dwt_forcetrxoff(void) |
||
3472 | { |
||
3473 | decaIrqStatus_t stat ; |
||
3474 | uint32_t mask; |
||
3475 | |||
3476 | mask = dwt_read32bitreg(SYS_MASK_ID) ; // Read set interrupt mask
|
||
3477 | |||
3478 | // Need to beware of interrupts occurring in the middle of following read modify write cycle
|
||
3479 | // We can disable the radio, but before the status is cleared an interrupt can be set (e.g. the
|
||
3480 | // event has just happened before the radio was disabled)
|
||
3481 | // thus we need to disable interrupt during this operation
|
||
3482 | stat = decamutexon() ; |
||
3483 | |||
3484 | dwt_write32bitreg(SYS_MASK_ID, 0) ; // Clear interrupt mask - so we don't get any unwanted events |
||
3485 | |||
3486 | dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_OFFSET, (uint8_t)SYS_CTRL_TRXOFF) ; // Disable the radio
|
||
3487 | |||
3488 | // Forcing Transceiver off - so we do not want to see any new events that may have happened
|
||
3489 | dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD)); |
||
3490 | |||
3491 | dwt_syncrxbufptrs(); |
||
3492 | |||
3493 | dwt_write32bitreg(SYS_MASK_ID, mask) ; // Set interrupt mask to what it was
|
||
3494 | |||
3495 | // Enable/restore interrupts again...
|
||
3496 | decamutexoff(stat) ; |
||
3497 | pdw1000local->wait4resp = 0;
|
||
3498 | |||
3499 | } // end deviceforcetrxoff()
|
||
3500 | |||
3501 | /*! ------------------------------------------------------------------------------------------------------------------
|
||
3502 | * @fn dwt_syncrxbufptrs()
|
||
3503 | *
|
||
3504 | * @brief this function synchronizes rx buffer pointers
|
||
3505 | * need to make sure that the host/IC buffer pointers are aligned before starting RX
|
||
3506 | *
|
||
3507 | * input parameters:
|
||
3508 | *
|
||
3509 | * output parameters
|
||
3510 | *
|
||
3511 | * no return value
|
||
3512 | */
|
||
3513 | void dwt_syncrxbufptrs(void) |
||
3514 | { |