Statistics
| Branch: | Tag: | Revision:

amiro-lld / include / alld_mpr121.h @ 8c47f14b

History | View | Annotate | Download (7.63 KB)

1
/*
2
AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU Lesser General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU Lesser General Public License for more details.
14

15
You should have received a copy of the GNU Lesser General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

    
19
/**
20
 * @file    alld_mpr121.h
21
 * @brief   Touch Sensor macros and structures.
22
 *
23
 * @addtogroup lld_touch
24
 * @{
25
 */
26

    
27
#ifndef AMIROLLD_MPR121_H
28
#define AMIROLLD_MPR121_H
29

    
30
#include <amiro-lld.h>
31

    
32
#if defined(AMIROLLD_CFG_USE_MPR121) || defined(__DOXYGEN__)
33

    
34
/**
35
 * @brief Maximum I2C frequency.
36
 */
37
#define MPR121_LLD_I2C_MAXFREQUENCY   400000
38

    
39
/**
40
 * @brief A falling edge indicates an interrupt.
41
 */
42
#define MPR121_LLD_INT_EDGE           APAL_GPIO_EDGE_FALLING
43

    
44
/**
45
 * @brief The MPR121 driver struct
46
 */
47
typedef struct {
48
  apalI2CDriver_t* i2cd;        /**< @brief The I2C Driver */
49
} MPR121Driver;
50

    
51
enum {
52
  MPR121_LLD_I2C_ADDR_FIXED   = 0x5Au,
53
  MPR121_LLD_I2C_ADDR_VSS     = 0x00u,
54
  MPR121_LLD_I2C_ADDR_VDD     = 0x01u,
55
  MPR121_LLD_I2C_ADDR_SDA     = 0x04u,
56
  MPR121_LLD_I2C_SOFTRESET    = 0x63,
57
};
58

    
59
/**
60
 * @brief Registers of the mpr121.
61
 */
62
typedef enum {
63
  MPR121_LLD_REGISTER_TOUCH_STATUS  = 0x00,
64
  MPR121_LLD_REGISTER_OOR_STATUS    = 0x02,
65
  MPR121_LLD_REGISTER_FILTERED_DATA = 0x04,
66
  MPR121_LLD_REGISTER_BASELINE      = 0x1E,
67

    
68
  MPR121_LLD_REGISTER_MHD_RISING    = 0x2B,
69
  MPR121_LLD_REGISTER_NHD_RISING    = 0x2C,
70
  MPR121_LLD_REGISTER_NCL_RISING    = 0x2D,
71
  MPR121_LLD_REGISTER_FDL_RISING    = 0x2E,
72
  MPR121_LLD_REGISTER_MHD_FALLING   = 0x2F,
73
  MPR121_LLD_REGISTER_NHD_FALLING   = 0x30,
74
  MPR121_LLD_REGISTER_NCL_FALLING   = 0x31,
75
  MPR121_LLD_REGISTER_FDL_FALLING   = 0x32,
76
  MPR121_LLD_REGISTER_NHD_TOUCHED   = 0x33,
77
  MPR121_LLD_REGISTER_NCL_TOUCHED   = 0x34,
78
  MPR121_LLD_REGISTER_FDL_TOUCHED   = 0x35,
79

    
80
  MPR121_LLD_REGISTER_ELEPROX_MHD_RISING    = 0x36,
81
  MPR121_LLD_REGISTER_ELEPROX_NHD_RISING    = 0x37,
82
  MPR121_LLD_REGISTER_ELEPROX_NCL_RISING    = 0x38,
83
  MPR121_LLD_REGISTER_ELEPROX_FDL_RISING    = 0x39,
84
  MPR121_LLD_REGISTER_ELEPROX_MHD_FALLING   = 0x3A,
85
  MPR121_LLD_REGISTER_ELEPROX_NHD_FALLING   = 0x3B,
86
  MPR121_LLD_REGISTER_ELEPROX_NCL_FALLING   = 0x3C,
87
  MPR121_LLD_REGISTER_ELEPROX_FDL_FALLING   = 0x3D,
88
  MPR121_LLD_REGISTER_ELEPROX_NHD_TOUCHED   = 0x3E,
89
  MPR121_LLD_REGISTER_ELEPROX_NCL_TOUCHED   = 0x3F,
90
  MPR121_LLD_REGISTER_ELEPROX_FDL_TOUCHED   = 0x40,
91

    
92
  MPR121_LLD_REGISTER_THRESHOLDS  = 0x41,
93
  MPR121_LLD_REGISTER_DEBOUNCE    = 0x5B,
94
  MPR121_LLD_REGISTER_CONFIG_1    = 0x5C,
95
  MPR121_LLD_REGISTER_CONFIG_2    = 0x5D,
96
  MPR121_LLD_REGISTER_CONFIG_ECR  = 0x5E,
97
  MPR121_LLD_REGISTER_ELE_CURRENT = 0x5F,
98
  MPR121_LLD_REGISTER_CHARGE_TIME = 0x6C,
99

    
100
  MPR121_LLD_REGISTER_GPIO_CTRL_0         = 0x73,
101
  MPR121_LLD_REGISTER_GPIO_CTRL_1         = 0x74,
102
  MPR121_LLD_REGISTER_GPIO_DATA           = 0x75,
103
  MPR121_LLD_REGISTER_GPIO_DIRECTION_CTRL = 0x76,
104
  MPR121_LLD_REGISTER_GPIO_ENABLE         = 0x77,
105
  MPR121_LLD_REGISTER_GPIO_DATA_SET       = 0x78,
106
  MPR121_LLD_REGISTER_GPIO_DATA_CLEAR     = 0x79,
107
  MPR121_LLD_REGISTER_GPIO_DATA_TOGGLE    = 0x7A,
108

    
109
  MPR121_LLD_REGISTER_AUTOCFG_CTRL_0       = 0x7B,
110
  MPR121_LLD_REGISTER_AUTOCFG_CTRL_1       = 0x7C,
111
  MPR121_LLD_REGISTER_AUTOCFG_USL          = 0x7D,
112
  MPR121_LLD_REGISTER_AUTOCFG_LSL          = 0x7E,
113
  MPR121_LLD_REGISTER_AUTOCFG_TARGET_LEVEL = 0x7F,
114

    
115
  MPR121_LLD_REGISTER_SOFT_RESET           = 0x80
116
} mpr121_lld_register_t;
117

    
118
/**
119
 * @brief Configuration data type.
120
 */
121
typedef union {
122
  uint8_t values[8];
123
  struct {
124
    uint8_t auto_config_1;
125
    uint8_t auto_config_2;
126
    uint8_t up_side_limit;
127
    uint8_t low_side_limit;
128
    uint8_t target_level;
129
    uint8_t config_1;
130
    uint8_t config_2;
131
    uint8_t ele_config;
132
  } registers;
133
} mpr121_lld_config_t;
134

    
135
/**
136
 * €brief Configutation register 1 masks.
137
 */
138
typedef enum {
139
  MPR121_LLD_FFI_6     = 0x00u,
140
  MPR121_LLD_FFI_10    = 0x40u,
141
  MPR121_LLD_FFI_18    = 0x80u,
142
  MPR121_LLD_FFI_34    = 0xC0u,
143
} mpr121_lld_config1_t;
144

    
145
/**
146
 * @brief Configuration register 2 masks.
147
 */
148
typedef enum {
149
  MPR121_LLD_CDT_OFF   = 0x00u,
150
  MPR121_LLD_CDT_0_5   = 0x20u,
151
  MPR121_LLD_CDT_1     = 0x40u,
152
  MPR121_LLD_CDT_2     = 0x60u,
153
  MPR121_LLD_CDT_4     = 0x80u,
154
  MPR121_LLD_CDT_8     = 0xA0u,
155
  MPR121_LLD_CDT_16    = 0xC0u,
156
  MPR121_LLD_CDT_32    = 0xE0u,
157
  MPR121_LLD_SFI_4     = 0x00u,
158
  MPR121_LLD_SFI_6     = 0x08u,
159
  MPR121_LLD_SFI_10    = 0x10u,
160
  MPR121_LLD_SFI_18    = 0x18u,
161
  MPR121_LLD_ESI_1     = 0x00u,
162
  MPR121_LLD_ESI_2     = 0x01u,
163
  MPR121_LLD_ESI_4     = 0x02u,
164
  MPR121_LLD_ESI_8     = 0x03u,
165
  MPR121_LLD_ESI_16    = 0x04u,
166
  MPR121_LLD_ESI_32    = 0x05u,
167
  MPR121_LLD_ESI_64    = 0x06u,
168
  MPR121_LLD_ESI_128   = 0x07u,
169
} mpr121_lld_config2_t;
170

    
171
/**
172
 * @brief Ele configuration register masks.
173
 */
174
typedef enum {
175
  MPR121_LLD_CL_ON_CURRENT  = 0x00u,
176
  MPR121_LLD_CL_OFF         = 0x40u,
177
  MPR121_LLD_CL_ON_HIGH5    = 0x80u,
178
  MPR121_LLD_CL_ON_ALL      = 0xC0u,
179
  MPR121_LLD_ELEPROX_0      = 0x00u,
180
  MPR121_LLD_ELEPROX_2      = 0x10u,
181
  MPR121_LLD_ELEPROX_4      = 0x20u,
182
  MPR121_LLD_ELEPROX_12     = 0x30u,
183
} mpr121_lld_ele_config_t;
184

    
185
/**
186
 * @brief Auto configuration register 0 masks.
187
 */
188
typedef enum {
189
  MPR121_LLD_AC_ENABLE      = 0x01u,
190
  MPR121_LLD_AC_RECONF_EN   = 0x02u,
191
  MPR121_LLD_BVA_ON_CURRENT = 0x00u,
192
  MPR121_LLD_BVA_OFF        = 0x04u,
193
  MPR121_LLD_BVA_ON_HIGH5   = 0x08u,
194
  MPR121_LLD_BVA_ON_ALL     = 0x0Cu,
195
  MPR121_LLD_RETRY_OFF      = 0x00u,
196
  MPR121_LLD_RETRY_2        = 0x10u,
197
  MPR121_LLD_RETRY_4        = 0x20u,
198
  MPR121_LLD_RETRY_8        = 0x30u,
199
  /* skip FFI */
200
} mpr121_lld_auto_config0_t;
201

    
202
/**
203
 * @brief Auto configuration register 1 masks.
204
 */
205
typedef enum {
206
  MPR121_LLD_AC_FAIL_INT_EN         = 0x01u,
207
  MPR121_LLD_AC_RECONF_FAIL_INT_EN  = 0x02u,
208
  MPR121_LLD_AC_OUT_OF_RANGE_INT_EN = 0x04u,
209
  MPR121_LLD_AC_SKIP_CHRG_TIME_SRCH = 0x80u,
210
} mpr121_lld_auto_config1_t;
211

    
212
#ifdef __cplusplus
213
extern "C" {
214
#endif
215
  apalExitStatus_t mpr121_lld_read_register(const MPR121Driver* const mprd, const mpr121_lld_register_t regaddr, const uint8_t offset, const uint8_t size, uint8_t* const data, const apalTime_t timeout);
216
  apalExitStatus_t mpr121_lld_write_register(const MPR121Driver* const mprd, const mpr121_lld_register_t regaddr, const uint8_t offset, const uint8_t size, const uint8_t* const data, const apalTime_t timeout);
217
  apalExitStatus_t mpr121_lld_soft_reset(const MPR121Driver* const mprd, const apalTime_t timeout);
218
  apalExitStatus_t mpr121_lld_read_filtered_data(const MPR121Driver* const mprd, const uint8_t index, const uint8_t num, uint16_t* const data, const apalTime_t timeout);
219
  apalExitStatus_t mpr121_lld_read_baseline_data(const MPR121Driver* const mprd, const uint8_t index, const uint8_t num, uint8_t* const data, const apalTime_t timeout);
220
  apalExitStatus_t mpr121_lld_read_electrode_data(const MPR121Driver* const mprd, const uint8_t index, const uint8_t num, uint8_t* const data, const apalTime_t timeout);
221
  apalExitStatus_t mpr121_lld_write_config(const MPR121Driver* const mprd, const mpr121_lld_config_t cfg, const apalTime_t timeout);
222
  apalExitStatus_t mpr121_lld_read_config(const MPR121Driver* const mprd, mpr121_lld_config_t* const cfg, const apalTime_t timeout);
223
#ifdef __cplusplus
224
}
225
#endif
226

    
227
#endif /* defined(AMIROLLD_CFG_USE_MPR121) */
228

    
229
#endif /* AMIROLLD_MPR121_H */
230

    
231
/** @} */