AMiRo-OS

/*! ------------------------------------------------------------------------------------------------------------------

 * @file    deca_regs.h

 * @brief   DW1000 Register Definitions

 *          This file supports assembler and C development for DW1000 enabled devices

 *

 * @attention

 *

 * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.

 *

 * All rights reserved.

 *

 */

#ifndef DECA_REGS_H

#define DECA_REGS_H

#ifdef __cplusplus

extern "C" {

#endif

#include <amiro-lld.h>

/****************************************************************************//**

 * @brief Bit definitions for register DEV_ID

**/

#define DEV_ID_ID               0x00            /* Device ID register, includes revision info (0xDECA0130) */

#define DEV_ID_LEN              (4)

/* mask and shift */

#define DEV_ID_REV_MASK         0x0000000FUL    /* Revision */

#define DEV_ID_VER_MASK         0x000000F0UL    /* Version */

#define DEV_ID_MODEL_MASK       0x0000FF00UL    /* The MODEL identifies the device. The DW1000 is device type 0x01 */

#define DEV_ID_RIDTAG_MASK      0xFFFF0000UL    /* Register Identification Tag 0XDECA */

/****************************************************************************//**

 * @brief Bit definitions for register EUI_64

**/

#define EUI_64_ID               0x01            /* IEEE Extended Unique Identifier (63:0) */

#define EUI_64_OFFSET           0x00

#define EUI_64_LEN              (8)

/****************************************************************************//**

 * @brief Bit definitions for register PANADR

**/

#define PANADR_ID               0x03            /* PAN ID (31:16) and Short Address (15:0) */

#define PANADR_LEN              (4)

/*mask and shift */

#define PANADR_SHORT_ADDR_OFFSET 0              /* In bytes */

#define PANADR_SHORT_ADDR_MASK  0x0000FFFFUL    /* Short Address */

#define PANADR_PAN_ID_OFFSET     2              /* In bytes */

#define PANADR_PAN_ID_MASK      0xFFFF00F0UL    /* PAN Identifier */

/****************************************************************************//**

 * @brief Bit definitions for register 0x05

**/

#define REG_05_ID_RESERVED      0x05

/****************************************************************************//**

 * @brief Bit definitions for register SYS_CFG

**/

#define SYS_CFG_ID              0x04            /* System Configuration (31:0) */

#define SYS_CFG_LEN             (4)

/*mask and shift */

#define SYS_CFG_MASK            0xF047FFFFUL    /* access mask to SYS_CFG_ID */

#define SYS_CFG_FF_ALL_EN       0x000001FEUL    /* Frame filtering options all frames allowed */

/*offset 0 */

#define SYS_CFG_FFE             0x00000001UL    /* Frame Filtering Enable. This bit enables the frame filtering functionality */

#define SYS_CFG_FFBC            0x00000002UL    /* Frame Filtering Behave as a Co-ordinator */

#define SYS_CFG_FFAB            0x00000004UL    /* Frame Filtering Allow Beacon frame reception */

#define SYS_CFG_FFAD            0x00000008UL    /* Frame Filtering Allow Data frame reception */

#define SYS_CFG_FFAA            0x00000010UL    /* Frame Filtering Allow Acknowledgment frame reception */

#define SYS_CFG_FFAM            0x00000020UL    /* Frame Filtering Allow MAC command frame reception */

#define SYS_CFG_FFAR            0x00000040UL    /* Frame Filtering Allow Reserved frame types */

#define SYS_CFG_FFA4            0x00000080UL    /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */

/*offset 8 */

#define SYS_CFG_FFA5            0x00000100UL    /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */

#define SYS_CFG_HIRQ_POL        0x00000200UL    /* Host interrupt polarity */

#define SYS_CFG_SPI_EDGE        0x00000400UL    /* SPI data launch edge */

#define SYS_CFG_DIS_FCE         0x00000800UL    /* Disable frame check error handling */

#define SYS_CFG_DIS_DRXB        0x00001000UL    /* Disable Double RX Buffer */

#define SYS_CFG_DIS_PHE         0x00002000UL    /* Disable receiver abort on PHR error */

#define SYS_CFG_DIS_RSDE        0x00004000UL    /* Disable Receiver Abort on RSD error */

#define SYS_CFG_FCS_INIT2F      0x00008000UL    /* initial seed value for the FCS generation and checking function */

/*offset 16 */

#define SYS_CFG_PHR_MODE_SHFT   16

#define SYS_CFG_PHR_MODE_00     0x00000000UL    /* Standard Frame mode */

#define SYS_CFG_PHR_MODE_11     0x00030000UL    /* Long Frames mode */

#define SYS_CFG_DIS_STXP        0x00040000UL    /* Disable Smart TX Power control */

#define SYS_CFG_RXM110K         0x00400000UL    /* Receiver Mode 110 kbps data rate */

/*offset 24 */

#define SYS_CFG_RXWTOE          0x10000000UL    /* Receive Wait Timeout Enable. */

#define SYS_CFG_RXAUTR          0x20000000UL    /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */

#define SYS_CFG_AUTOACK         0x40000000UL    /* Automatic Acknowledgement Enable */

#define SYS_CFG_AACKPEND        0x80000000UL    /* Automatic Acknowledgement Pending bit control */

/****************************************************************************//**

 * @brief Bit definitions for register SYS_TIME

**/

#define SYS_TIME_ID             0x06            /* System Time Counter (40-bit) */

#define SYS_TIME_OFFSET         0x00

#define SYS_TIME_LEN            (5)             /* Note 40 bit register */

/****************************************************************************//**

 * @brief Bit definitions for register  0x07

**/

#define REG_07_ID_RESERVED      0x07

/****************************************************************************//**

 * @brief Bit definitions for register TX_FCTRL

**/

#define TX_FCTRL_ID             0x08            /* Transmit Frame Control */

#define TX_FCTRL_LEN            (5)             /* Note 40 bit register */

/*masks (low 32 bit) */

#define TX_FCTRL_TFLEN_MASK     0x0000007FUL    /* bit mask to access Transmit Frame Length */

#define TX_FCTRL_TFLE_MASK      0x00000380UL    /* bit mask to access Transmit Frame Length Extension */

#define TX_FCTRL_FLE_MASK       0x000003FFUL    /* bit mask to access Frame Length field */

#define TX_FCTRL_TXBR_MASK      0x00006000UL    /* bit mask to access Transmit Bit Rate */

#define TX_FCTRL_TXPRF_MASK     0x00030000UL    /* bit mask to access Transmit Pulse Repetition Frequency */

#define TX_FCTRL_TXPSR_MASK     0x000C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */

#define TX_FCTRL_PE_MASK        0x00300000UL    /* bit mask to access Preamble Extension */

#define TX_FCTRL_TXPSR_PE_MASK  0x003C0000UL    /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */

#define TX_FCTRL_SAFE_MASK_32   0xFFFFE3FFUL    /* FSCTRL has fields which should always be writen zero */

/*offset 0 */

/*offset 8 */

#define TX_FCTRL_TXBR_110k      0x00000000UL    /* Transmit Bit Rate = 110k */

#define TX_FCTRL_TXBR_850k      0x00002000UL    /* Transmit Bit Rate = 850k */

#define TX_FCTRL_TXBR_6M        0x00004000UL    /* Transmit Bit Rate = 6.8M */

#define TX_FCTRL_TXBR_SHFT      (13)            /* shift to access Data Rate field */

#define TX_FCTRL_TR             0x00008000UL    /* Transmit Ranging enable */

#define TX_FCTRL_TR_SHFT        (15)            /* shift to access Ranging bit */

/*offset 16 */

#define TX_FCTRL_TXPRF_SHFT     (16)            /* shift to access Pulse Repetition Frequency field */

#define TX_FCTRL_TXPRF_4M       0x00000000UL    /* Transmit Pulse Repetition Frequency = 4 Mhz */

#define TX_FCTRL_TXPRF_16M      0x00010000UL    /* Transmit Pulse Repetition Frequency = 16 Mhz */

#define TX_FCTRL_TXPRF_64M      0x00020000UL    /* Transmit Pulse Repetition Frequency = 64 Mhz */

#define TX_FCTRL_TXPSR_SHFT     (18)            /* shift to access Preamble Symbol Repetitions field */

#define TX_FCTRL_PE_SHFT        (20)            /* shift to access Preamble length Extension to allow specification of non-standard values */

#define TX_FCTRL_TXPSR_PE_16    0x00000000UL    /* bit mask to access Preamble Extension = 16 */

#define TX_FCTRL_TXPSR_PE_64    0x00040000UL    /* bit mask to access Preamble Extension = 64 */

#define TX_FCTRL_TXPSR_PE_128   0x00140000UL    /* bit mask to access Preamble Extension = 128 */

#define TX_FCTRL_TXPSR_PE_256   0x00240000UL    /* bit mask to access Preamble Extension = 256 */

#define TX_FCTRL_TXPSR_PE_512   0x00340000UL    /* bit mask to access Preamble Extension = 512 */

#define TX_FCTRL_TXPSR_PE_1024  0x00080000UL    /* bit mask to access Preamble Extension = 1024 */

#define TX_FCTRL_TXPSR_PE_1536  0x00180000UL    /* bit mask to access Preamble Extension = 1536 */

#define TX_FCTRL_TXPSR_PE_2048  0x00280000UL    /* bit mask to access Preamble Extension = 2048 */

#define TX_FCTRL_TXPSR_PE_4096  0x000C0000UL    /* bit mask to access Preamble Extension = 4096 */

/*offset 22 */

#define TX_FCTRL_TXBOFFS_SHFT   (22)            /* Shift to access transmit buffer index offset */

#define TX_FCTRL_TXBOFFS_MASK   0xFFC00000UL    /* bit mask to access Transmit buffer index offset 10-bit field */

/*offset 32 */

#define TX_FCTRL_IFSDELAY_MASK  0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */

/****************************************************************************//**

 * @brief Bit definitions for register TX_BUFFER

**/

#define TX_BUFFER_ID            0x09            /* Transmit Data Buffer */

#define TX_BUFFER_LEN           (1024)

/****************************************************************************//**

 * @brief Bit definitions for register  DX_TIME

**/

#define DX_TIME_ID              0x0A            /* Delayed Send or Receive Time (40-bit) */

#define DX_TIME_LEN             (5)

/****************************************************************************//**

 * @brief Bit definitions for register 0x08

**/

#define REG_0B_ID_RESERVED      0x0B

/****************************************************************************//**

 * @brief Bit definitions for register RX_FWTO

**/

#define RX_FWTO_ID              0x0C            /* Receive Frame Wait Timeout Period */

#define RX_FWTO_OFFSET          0x00

#define RX_FWTO_LEN             (2)             /* doc bug*/

/*mask and shift */

#define RX_FWTO_MASK            0xFFFF

/****************************************************************************//**

 * @brief Bit definitions for register SYS_CTRL

**/

#define SYS_CTRL_ID             0x0D            /* System Control Register */

#define SYS_CTRL_OFFSET         0x00

#define SYS_CTRL_LEN            (4)

/*masks */

#define SYS_CTRL_MASK_32        0x010003CFUL    /* System Control Register access mask (all unused fields should always be writen as zero) */

/*offset 0 */

#define SYS_CTRL_SFCST          0x00000001UL    /* Suppress Auto-FCS Transmission (on this frame) */

#define SYS_CTRL_TXSTRT         0x00000002UL    /* Start Transmitting Now */

#define SYS_CTRL_TXDLYS         0x00000004UL    /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */

#define SYS_CTRL_CANSFCS        0x00000008UL    /* Cancel Suppression of auto-FCS transmission (on the current frame) */

#define SYS_CTRL_TRXOFF         0x00000040UL    /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */

#define SYS_CTRL_WAIT4RESP      0x00000080UL    /* Wait for Response */

/*offset 8 */

#define SYS_CTRL_RXENAB         0x00000100UL    /* Enable Receiver Now */

#define SYS_CTRL_RXDLYE         0x00000200UL    /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/

/*offset 16 */

/*offset 24 */

#define SYS_CTRL_HSRBTOGGLE     0x01000000UL    /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */

#define SYS_CTRL_HRBT           (SYS_CTRL_HSRBTOGGLE)

#define SYS_CTRL_HRBT_OFFSET    (3)

/****************************************************************************//**

 * @brief Bit definitions for register  SYS_MASK

**/

#define SYS_MASK_ID             0x0E            /* System Event Mask Register */

#define SYS_MASK_LEN            (4)

/*masks */

#define SYS_MASK_MASK_32        0x3FF7FFFEUL    /* System Event Mask Register access mask (a