AMiRo-OS

/*

AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.

Copyright (C) 2016..2019  Thomas Schöpping et al.

This program is free software: you can redistribute it and/or modify

it under the terms of the GNU Lesser General Public License as published by

the Free Software Foundation, either version 3 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU Lesser General Public License for more details.

You should have received a copy of the GNU Lesser General Public License

along with this program.  If not, see <http://www.gnu.org/licenses/>.

*/

/*! ------------------------------------------------------------------------------------------------------------------

 * @file    deca_device.c

 * @brief   Decawave device configuration and control functions

 *

 * @attention

 *

 * Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.

 *

 * All rights reserved.

 *

 */

#include <alld_DW1000.h>

#if (defined(AMIROLLD_CFG_DW1000) && (AMIROLLD_CFG_DW1000 == 0)) || defined(__DOXYGEN__)

#include <aos_thread.h>

#include <assert.h>

#include <string.h>

#include <stdlib.h>

#include <math.h>

// HW dependent implementation (see bottom of file)

static int _alld_dw1000_writespi(uint16_t headerLength,

               const        uint8_t *headerBuffer,

               uint32_t bodyLength,

               const        uint8_t *bodyBuffer);

static int _alld_dw1000_readspi(uint16_t headerLength,

                const uint8_t *headerBuffer,

                uint32_t readlength,

                uint8_t *readBuffer);

// Defines for enable_clocks function

#define FORCE_SYS_XTI  0

#define ENABLE_ALL_SEQ 1

#define FORCE_SYS_PLL  2

#define READ_ACC_ON    7

#define READ_ACC_OFF   8

#define FORCE_OTP_ON   11

#define FORCE_OTP_OFF  12

#define FORCE_TX_PLL   13

#define FORCE_LDE      14

// Defines for ACK request bitmask in DATA and MAC COMMAND frame control (first byte) - Used to detect AAT bit wrongly set.

#define FCTRL_ACK_REQ_MASK 0x20

// Frame control maximum length in bytes.

#define FCTRL_LEN_MAX 2

#define NUM_BR 3

#define NUM_PRF 2

#define NUM_PACS 4

#define NUM_BW 2            //2 bandwidths are supported

#define NUM_SFD 2           //supported number of SFDs - standard = 0, non-standard = 1

#define NUM_CH 6            //supported channels are 1, 2, 3, 4, 5, 7

#define NUM_CH_SUPPORTED 8  //supported channels are '0', 1, 2, 3, 4, 5, '6', 7

#define PCODES 25           //supported preamble codes

typedef struct {

    uint32_t lo32;

    uint16_t target[NUM_PRF];

} agc_cfg_struct ;

extern const agc_cfg_struct agc_config ;

//SFD threshold settings for 110k, 850k, 6.8Mb standard and non-standard

extern const uint16_t sftsh[NUM_BR][NUM_SFD];

extern const uint16_t dtune1[NUM_PRF];

#define XMLPARAMS_VERSION   (1.17f)

extern const uint32_t fs_pll_cfg[NUM_CH];

extern const uint8_t fs_pll_tune[NUM_CH];

extern const uint8_t rx_config[NUM_BW];

extern const uint32_t tx_config[NUM_CH];

extern const uint8_t dwnsSFDlen[NUM_BR]; //length of SFD for each of the bitrates

extern const uint32_t digital_bb_config[NUM_PRF][NUM_PACS];

extern const uint8_t chan_idx[NUM_CH_SUPPORTED];

extern const double txpwr_compensation[NUM_CH];

#define PEAK_MULTPLIER  (0x60) //3 -> (0x3 * 32) & 0x00E0

#define N_STD_FACTOR    (13)

#define LDE_PARAM1      (PEAK_MULTPLIER | N_STD_FACTOR)

#define LDE_PARAM3_16 (0x1607)

#define LDE_PARAM3_64 (0x0607)

#define MIXER_GAIN_STEP (0.5)

#define DA_ATTN_STEP    (2.5)

// #define DWT_API_ERROR_CHECK     // define so API checks config input parameters

//-----------------------------------------

// map the channel number to the index in the configuration arrays below

// 0th element is chan 1, 1st is chan 2, 2nd is chan 3, 3rd is chan 4, 4th is chan 5, 5th is chan 7

const uint8_t chan_idx[NUM_CH_SUPPORTED] = {0, 0, 1, 2, 3, 4, 0, 5};

//-----------------------------------------

const uint32_t tx_config[NUM_CH] =

{

    RF_TXCTRL_CH1,

    RF_TXCTRL_CH2,

    RF_TXCTRL_CH3,

    RF_TXCTRL_CH4,

    RF_TXCTRL_CH5,

    RF_TXCTRL_CH7,

};

//Frequency Synthesiser - PLL configuration

const uint32_t fs_pll_cfg[NUM_CH] =

{

    FS_PLLCFG_CH1,

    FS_PLLCFG_CH2,

    FS_PLLCFG_CH3,

    FS_PLLCFG_CH4,

    FS_PLLCFG_CH5,

    FS_PLLCFG_CH7

};

//Frequency Synthesiser - PLL tuning

const uint8_t fs_pll_tune[NUM_CH] =

{

    FS_PLLTUNE_CH1,

    FS_PLLTUNE_CH2,

    FS_PLLTUNE_CH3,

    FS_PLLTUNE_CH4,

    FS_PLLTUNE_CH5,

    FS_PLLTUNE_CH7

};

//bandwidth configuration

const uint8_t rx_config[NUM_BW] =

{

    RF_RXCTRLH_NBW,

    RF_RXCTRLH_WBW

};

const agc_cfg_struct agc_config =

{

    AGC_TUNE2_VAL,

    { AGC_TUNE1_16M , AGC_TUNE1_64M }  //adc target

};

//DW non-standard SFD length for 110k, 850k and 6.81M

const uint8_t dwnsSFDlen[NUM_BR] =

{

    DW_NS_SFD_LEN_110K,

    DW_NS_SFD_LEN_850K,

    DW_NS_SFD_LEN_6M8

};

// SFD Threshold

const uint16_t sftsh[NUM_BR][NUM_SFD] =

{

    {

        DRX_TUNE0b_110K_STD,

        DRX_TUNE0b_110K_NSTD

    },

    {

        DRX_TUNE0b_850K_STD,

        DRX_TUNE0b_850K_NSTD

    },

    {

        DRX_TUNE0b_6M8_STD,

        DRX_TUNE0b_6M8_NSTD

    }

};

const uint16_t dtune1[NUM_PRF] =

{

    DRX_TUNE1a_PRF16,

    DRX_TUNE1a_PRF64

};

const uint32_t digital_bb_config[NUM_PRF][NUM_PACS] =

{

    {

        DRX_TUNE2_PRF16_PAC8,

        DRX_TUNE2_PRF16_PAC16,

        DRX_TUNE2_PRF16_PAC32,

        DRX_TUNE2_PRF16_PAC64

    },

    {

        DRX_TUNE2_PRF64_PAC8,

        DRX_TUNE2_PRF64_PAC16,

        DRX_TUNE2_PRF64_PAC32,

        DRX_TUNE2_PRF64_PAC64

    }

};

const uint16_t lde_replicaCoeff[PCODES] =

{

    0, // No preamble code 0

    LDE_REPC_PCODE_1,

    LDE_REPC_PCODE_2,

    LDE_REPC_PCODE_3,

    LDE_REPC_PCODE_4,

    LDE_REPC_PCODE_5,

    LDE_REPC_PCODE_6,

    LDE_REPC_PCODE_7,

    LDE_REPC_PCODE_8,

    LDE_REPC_PCODE_9,

    LDE_REPC_PCODE_10,

    LDE_REPC_PCODE_11,

    LDE_REPC_PCODE_12,

    LDE_REPC_PCODE_13,

    LDE_REPC_PCODE_14,

    LDE_REPC_PCODE_15,

    LDE_REPC_PCODE_16,

    LDE_REPC_PCODE_17,

    LDE_REPC_PCODE_18,

    LDE_REPC_PCODE_19,

    LDE_REPC_PCODE_20,

    LDE_REPC_PCODE_21,

    LDE_REPC_PCODE_22,

    LDE_REPC_PCODE_23,

    LDE_REPC_PCODE_24

};

const double txpwr_compensation[NUM_CH] = {

    0.0,

    0.035,

    0.0,

    0.0,

    0.065,

    0.0

};

#define NUM_16M_OFFSET  (37)

#define NUM_16M_OFFSETWB  (68)

#define NUM_64M_OFFSET  (26)

#define NUM_64M_OFFSETWB  (59)