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amiro-lld / include / alld_l3g4200d.h @ d6728c5b

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1 d6728c5b Thomas Schöpping
/*
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AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2018  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _AMIROLLD_L3G4200D_H_
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#define _AMIROLLD_L3G4200D_H_
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#include <amiro-lld.h>
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#if defined(AMIROLLD_CFG_USE_L3G4200D) || defined(__DOXYGEN__)
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/**
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 * @brief A rising edge indicates an interrupt.
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 */
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#define L3G4200D_LLD_INT_EDGE   APAL_GPIO_EDGE_RISING
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/**
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 * @brief The L3G4200D driver struct
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 */
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typedef struct {
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  apalSPIDriver_t* spid;        /**< @brief The SPI Driver */
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} L3G4200DDriver;
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/**
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 * @brief SPI access modes.
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 */
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typedef enum {
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  L3G4200D_LLD_SPI_MULT  = 0x40u,
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  L3G4200D_LLD_SPI_READ  = 0x80u,
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  L3G4200D_LLD_SPI_WRITE = 0x00u,
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} l3g4200d_lld_SPI_mode_t;
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/**
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 * @brief Registers.
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 */
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typedef enum {
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  L3G4200D_LLD_REGISTER_WHO_AM_I = 0x0F,
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  L3G4200D_LLD_REGISTER_CTRL_REG1 = 0x20,
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  L3G4200D_LLD_REGISTER_CTRL_REG2 = 0x21,
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  L3G4200D_LLD_REGISTER_CTRL_REG3 = 0x22,
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  L3G4200D_LLD_REGISTER_CTRL_REG4 = 0x23,
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  L3G4200D_LLD_REGISTER_CTRL_REG5 = 0x24,
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  L3G4200D_LLD_REGISTER_REFERECE = 0x25,
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  L3G4200D_LLD_REGISTER_OUT_TEMP = 0x26,
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  L3G4200D_LLD_REGISTER_STATUS_REG = 0x27,
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  L3G4200D_LLD_REGISTER_OUT_X_L = 0x28,
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  L3G4200D_LLD_REGISTER_OUT_X_H = 0x29,
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  L3G4200D_LLD_REGISTER_OUT_Y_L = 0x2A,
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  L3G4200D_LLD_REGISTER_OUT_Y_H = 0x2B,
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  L3G4200D_LLD_REGISTER_OUT_Z_L = 0x2C,
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  L3G4200D_LLD_REGISTER_OUT_Z_H = 0x2D,
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  L3G4200D_LLD_REGISTER_FIFO_CTRL_REG = 0x2E,
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  L3G4200D_LLD_REGISTER_FIFO_SRC_REG = 0x2F,
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  L3G4200D_LLD_REGISTER_INT1_CFG = 0x30,
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  L3G4200D_LLD_REGISTER_INT1_SRC = 0x31,
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  L3G4200D_LLD_REGISTER_INT1_TSH_XH = 0x32,
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  L3G4200D_LLD_REGISTER_INT1_TSH_XL = 0x33,
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  L3G4200D_LLD_REGISTER_INT1_TSH_YH = 0x34,
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  L3G4200D_LLD_REGISTER_INT1_TSH_YL = 0x35,
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  L3G4200D_LLD_REGISTER_INT1_TSH_ZH = 0x36,
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  L3G4200D_LLD_REGISTER_INT1_TSH_ZL = 0x37,
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  L3G4200D_LLD_REGISTER_INT1_DURATION = 0x38,
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} l3g4200d_lld_register_t;
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/**
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 * @brief WHO_AM_I register constant content.
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 */
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typedef enum {
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  L3G4200D_LLD_WHO_AM_I = 0xD3,
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} l3g4200d_lld_whoami_t;
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/**
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 * @brief Control register 1 flags.
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 */
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typedef enum {
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  L3G4200D_LLD_DR_100_HZ   = 0x00,
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  L3G4200D_LLD_DR_200_HZ   = 0x40,
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  L3G4200D_LLD_DR_400_HZ   = 0x80,
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  L3G4200D_LLD_DR_800_HZ   = 0xC0,
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  L3G4200D_LLD_BW_12_5  = 0x00,
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  L3G4200D_LLD_BW_20    = 0x00,
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  L3G4200D_LLD_BW_25    = 0x10,
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  L3G4200D_LLD_BW_30    = 0x00,
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  L3G4200D_LLD_BW_35    = 0x10,
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  L3G4200D_LLD_BW_50    = 0x20,
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  L3G4200D_LLD_BW_70    = 0x30,
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  L3G4200D_LLD_BW_110   = 0x30,
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  L3G4200D_LLD_PD  = 0x08,
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  L3G4200D_LLD_ZEN = 0x04,
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  L3G4200D_LLD_YEN = 0x02,
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  L3G4200D_LLD_XEN = 0x01,
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} l3g4200d_lld_ctrl_reg1_t;
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/**
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 * @brief Control register 2 flags.
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 */
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typedef enum {
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  L3G4200D_LLD_HPM_NORMAL_RST = 0x00,
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  L3G4200D_LLD_HPM_REFERENCE  = 0x10,
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  L3G4200D_LLD_HPM_NORMAL     = 0x20,
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  L3G4200D_LLD_HPM_AUTO_RST   = 0x30,
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  L3G4200D_LLD_HPCF_2    = 0x00,
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  L3G4200D_LLD_HPCF_4    = 0x01,
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  L3G4200D_LLD_HPCF_8    = 0x02,
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  L3G4200D_LLD_HPCF_16   = 0x03,
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  L3G4200D_LLD_HPCF_32   = 0x04,
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  L3G4200D_LLD_HPCF_64   = 0x05,
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  L3G4200D_LLD_HPCF_128  = 0x06,
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  L3G4200D_LLD_HPCF_256  = 0x07,
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  L3G4200D_LLD_HPCF_512  = 0x08,
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  L3G4200D_LLD_HPCF_1024 = 0x09,
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} l3g4200d_lld_ctrl_reg2_t;
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/**
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 * @brief Control register 3 flags.
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 */
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typedef enum {
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  L3G4200D_LLD_I1_INT1   = 0x80,
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  L3G4200D_LLD_I1_BOOT   = 0x40,
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  L3G4200D_LLD_H_IACTIVE = 0x20,
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  L3G4200D_LLD_PP_OD     = 0x10,
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  L3G4200D_LLD_I2_DRDY   = 0x08,
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  L3G4200D_LLD_I2_WTM    = 0x04,
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  L3G4200D_LLD_I2_ORUN   = 0x02,
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  L3G4200D_LLD_I2_EMPTY  = 0x01,
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} l3g4200d_lld_ctrl_reg3_t;
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/**
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 * @brief Control register 4 flags.
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 */
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typedef enum {
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  L3G4200D_LLD_BDU_CONT    = 0x00,
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  L3G4200D_LLD_BDU_SINGLE  = 0x80,
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  L3G4200D_LLD_BLE_MSB     = 0x40,
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  L3G4200D_LLD_BLE_LSB     = 0x00,
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  L3G4200D_LLD_FS_250_DPS  = 0x00,
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  L3G4200D_LLD_FS_500_DPS  = 0x10,
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  L3G4200D_LLD_FS_2000_DPS = 0x20,
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  L3G4200D_LLD_ST_SIGN_M   = 0x04,
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  L3G4200D_LLD_ST_SIGN_P   = 0x00,
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  L3G4200D_LLD_ST_EN       = 0x02,
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  L3G4200D_LLD_SIM_3W      = 0x01,
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  L3G4200D_LLD_SIM_4W      = 0x00,
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} l3g4200d_lld_ctrl_reg4_t;
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/**
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 * @brief Control register 5 flags.
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 */
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typedef enum {
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  L3G4200D_LLD_BOOT          = 0x80,
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  L3G4200D_LLD_FIFO_EN       = 0x40,
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  L3G4200D_LLD_HP_EN         = 0x10,
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  L3G4200D_LLD_INT1_SEL_NOHP = 0x00,
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  L3G4200D_LLD_INT1_SEL_HP   = 0x04,
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  L3G4200D_LLD_INT1_SEL_LP   = 0x08,
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  L3G4200D_LLD_OUT_SEL_NOHP  = 0x00,
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  L3G4200D_LLD_OUT_SEL_HP    = 0x01,
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  L3G4200D_LLD_OUT_SEL_LP    = 0x02,
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} l3g4200d_lld_ctrl_reg5_t;
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/**
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 * @brief Status register flags.
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 */
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typedef enum {
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  L3G4200D_LLD_ZYXOR = 0x80,
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  L3G4200D_LLD_ZOR   = 0x40,
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  L3G4200D_LLD_YOR   = 0x20,
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  L3G4200D_LLD_XOR   = 0x10,
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  L3G4200D_LLD_ZYXDA = 0x08,
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  L3G4200D_LLD_ZDA   = 0x04,
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  L3G4200D_LLD_YDA   = 0x02,
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  L3G4200D_LLD_XDA   = 0x01,
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} l3g4200d_lld_status_reg_t;
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/**
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 * @brief Fifo control register masks.
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 */
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typedef enum {
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  L3G4200D_LLD_FM_BYPASS        = 0x00,
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  L3G4200D_LLD_FM_FMMODE        = 0x20,
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  L3G4200D_LLD_FM_STREAM        = 0x40,
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  L3G4200D_LLD_FM_STREAM2FIFO   = 0x60,
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  L3G4200D_LLD_FM_BYPASS2STREAM = 0x80,
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  L3G4200D_LLD_WTM_MASK         = 0x1F,
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} l3g4200d_lld_fifo_ctrl_reg_t;
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/**
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 * @brief  FIFO source register masks.
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 */
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typedef enum {
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  L3G4200D_LLD_WTM      = 0x80,
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  L3G4200D_LLD_OVRN     = 0x40,
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  L3G4200D_LLD_EMPTY    = 0x20,
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  L3G4200D_LLD_FSS_MASK = 0x1F,
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} l3g4200d_lld_fifo_src_reg_t;
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/**
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 * @brief Interrupt 1 config register flags.
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 */
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typedef enum {
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  L3G4200D_LLD_ANDOR = 0x80,
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  L3G4200D_LLD_LIR   = 0x40,
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  L3G4200D_LLD_ZHIE  = 0x20,
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  L3G4200D_LLD_ZLIE  = 0x10,
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  L3G4200D_LLD_YHIE  = 0x08,
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  L3G4200D_LLD_YLIE  = 0x04,
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  L3G4200D_LLD_XHIE  = 0x02,
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  L3G4200D_LLD_XLIE  = 0x01,
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} l3g4200d_lld_int1_cfg_reg_t;
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/**
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 * @brief Interrupt 1 source register flags.
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 */
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typedef enum {
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  L3G4200D_LLD_IA = 0x40,
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  L3G4200D_LLD_ZH = 0x20,
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  L3G4200D_LLD_ZL = 0x10,
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  L3G4200D_LLD_YH = 0x08,
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  L3G4200D_LLD_YL = 0x04,
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  L3G4200D_LLD_XH = 0x02,
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  L3G4200D_LLD_XL = 0x01,
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} l3g4200d_lld_int1_src_t;
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/**
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 * @brief Threshold mask.
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 */
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enum {
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  L3G4200D_LLD_THS_L_MASK = 0x7F
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};
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/**
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 * @brief Interrupt duration register masks.
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 */
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typedef enum {
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  L3G4200D_LLD_INT1_WAIT          = 0x80,
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  L3G4200D_LLD_INT1_DURATION_MASK = 0x7F,
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} l3g4200d_lld_int1_duration_reg_t;
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/**
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 * @brief Axis enum.
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 */
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typedef enum {
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  L3G4200D_LLD_X_AXIS = 0x00,
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  L3G4200D_LLD_Y_AXIS = 0x01,
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  L3G4200D_LLD_Z_AXIS = 0x02,
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} l3g4200d_lld_axis_t;
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/**
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 * @brief Config register struct.
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 */
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typedef union {
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  uint8_t data[5];
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  struct {
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    uint8_t ctrl_reg1;
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    uint8_t ctrl_reg2;
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    uint8_t ctrl_reg3;
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    uint8_t ctrl_reg4;
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    uint8_t ctrl_reg5;
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  } registers;
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} l3g4200d_lld_cfg_t;
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/**
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 * @brief Interrupt config struct.
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 */
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typedef union {
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  uint8_t data[9];
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  struct {
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    uint8_t int1_cfg;
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    uint8_t int1_src;
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    uint8_t int1_tsh_xh;
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    uint8_t int1_tsh_xl;
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    uint8_t int1_tsh_yh;
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    uint8_t int1_tsh_yl;
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    uint8_t int1_tsh_zh;
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    uint8_t int1_tsh_zl;
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    uint8_t int1_duration;
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  } registers;
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} l3g4200d_lld_int_cfg_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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  apalExitStatus_t l3g4200d_lld_read_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, uint8_t* const data, const uint8_t length);
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  apalExitStatus_t l3g4200d_lld_write_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, const uint8_t* const data, const uint8_t length);
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  apalExitStatus_t l3g4200d_lld_read_all_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_cfg_t* const cfg);
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  apalExitStatus_t l3g4200d_lld_read_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_axis_t axis, const l3g4200d_lld_cfg_t* const cfg);
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  apalExitStatus_t l3g4200d_lld_read_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_cfg_t* const cfg);
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  apalExitStatus_t l3g4200d_lld_write_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_cfg_t cfg);
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  apalExitStatus_t l3g4200d_lld_read_int_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_int_cfg_t* const cfg);
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  apalExitStatus_t l3g4200d_lld_write_int_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_int_cfg_t cfg);
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  apalExitStatus_t l3g4200d_lld_read_int_src(const L3G4200DDriver* const l3gd, uint8_t* const cfg);
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  apalExitStatus_t l3g4200d_lld_read_status_register(const L3G4200DDriver* const l3gd, uint8_t* const status);
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  apalExitStatus_t l3g4200d_lld_read_fifo_ctrl_register(const L3G4200DDriver* const l3gd, uint8_t* const fifo);
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  apalExitStatus_t l3g4200d_lld_write_fifo_ctrl_register(const L3G4200DDriver* const l3gd, const uint8_t fifo);
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  apalExitStatus_t l3g4200d_lld_read_fifo_src_register(const L3G4200DDriver* const l3gdd, uint8_t* const fifo);
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#ifdef __cplusplus
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}
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#endif
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#endif /* defined(AMIROLLD_CFG_USE_L3G4200D) */
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#endif /* _AMIROLLD_L3G4200D_H_ */