Revision 0128be0f os/hal/ports/STM32/LLD/QEIv1/hal_qei_lld.c
| os/hal/ports/STM32/LLD/QEIv1/hal_qei_lld.c | ||
|---|---|---|
| 156 | 156 |
/* Clock activation and timer reset.*/ |
| 157 | 157 |
#if STM32_QEI_USE_TIM1 |
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if (&QEID1 == qeip) {
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rccEnableTIM1(FALSE);
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rccEnableTIM1(); |
|
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rccResetTIM1(); |
| 161 | 161 |
} |
| 162 | 162 |
#endif |
| 163 | 163 |
#if STM32_QEI_USE_TIM2 |
| 164 | 164 |
if (&QEID2 == qeip) {
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rccEnableTIM2(FALSE);
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rccEnableTIM2(); |
|
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rccResetTIM2(); |
| 167 | 167 |
} |
| 168 | 168 |
#endif |
| 169 | 169 |
#if STM32_QEI_USE_TIM3 |
| 170 | 170 |
if (&QEID3 == qeip) {
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rccEnableTIM3(FALSE);
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rccEnableTIM3(); |
|
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rccResetTIM3(); |
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} |
| 174 | 174 |
#endif |
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#if STM32_QEI_USE_TIM4 |
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if (&QEID4 == qeip) {
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rccEnableTIM4(FALSE);
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rccEnableTIM4(); |
|
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rccResetTIM4(); |
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} |
| 180 | 180 |
#endif |
| 181 | 181 |
|
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#if STM32_QEI_USE_TIM5 |
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if (&QEID5 == qeip) {
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rccEnableTIM5(FALSE);
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rccEnableTIM5(); |
|
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rccResetTIM5(); |
| 186 | 186 |
} |
| 187 | 187 |
#endif |
| 188 | 188 |
#if STM32_QEI_USE_TIM8 |
| 189 | 189 |
if (&QEID8 == qeip) {
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rccEnableTIM8(FALSE);
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rccEnableTIM8(); |
|
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rccResetTIM8(); |
| 192 | 192 |
} |
| 193 | 193 |
#endif |
| ... | ... | |
| 242 | 242 |
|
| 243 | 243 |
#if STM32_QEI_USE_TIM1 |
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if (&QEID1 == qeip) {
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rccDisableTIM1(FALSE);
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rccDisableTIM1(); |
|
| 246 | 246 |
} |
| 247 | 247 |
#endif |
| 248 | 248 |
#if STM32_QEI_USE_TIM2 |
| 249 | 249 |
if (&QEID2 == qeip) {
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rccDisableTIM2(FALSE);
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rccDisableTIM2(); |
|
| 251 | 251 |
} |
| 252 | 252 |
#endif |
| 253 | 253 |
#if STM32_QEI_USE_TIM3 |
| 254 | 254 |
if (&QEID3 == qeip) {
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rccDisableTIM3(FALSE);
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rccDisableTIM3(); |
|
| 256 | 256 |
} |
| 257 | 257 |
#endif |
| 258 | 258 |
#if STM32_QEI_USE_TIM4 |
| 259 | 259 |
if (&QEID4 == qeip) {
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rccDisableTIM4(FALSE);
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rccDisableTIM4(); |
|
| 261 | 261 |
} |
| 262 | 262 |
#endif |
| 263 | 263 |
#if STM32_QEI_USE_TIM5 |
| 264 | 264 |
if (&QEID5 == qeip) {
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rccDisableTIM5(FALSE);
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rccDisableTIM5(); |
|
| 266 | 266 |
} |
| 267 | 267 |
#endif |
| 268 | 268 |
} |
| 269 | 269 |
#if STM32_QEI_USE_TIM8 |
| 270 | 270 |
if (&QEID8 == qeip) {
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rccDisableTIM8(FALSE);
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rccDisableTIM8(); |
|
| 272 | 272 |
} |
| 273 | 273 |
#endif |
| 274 | 274 |
} |
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