amiro-os / modules / NUCLEO-L476RG / board.c @ 0f60c8ad
History | View | Annotate | Download (8.57 KB)
1 |
/*
|
---|---|
2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
|
3 |
Copyright (C) 2016..2019 Thomas Schöpping et al.
|
4 |
|
5 |
This program is free software: you can redistribute it and/or modify
|
6 |
it under the terms of the GNU General Public License as published by
|
7 |
the Free Software Foundation, either version 3 of the License, or
|
8 |
(at your option) any later version.
|
9 |
|
10 |
This program is distributed in the hope that it will be useful,
|
11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
GNU General Public License for more details.
|
14 |
|
15 |
You should have received a copy of the GNU General Public License
|
16 |
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
17 |
*/
|
18 |
|
19 |
#include "hal.h" |
20 |
#include "stm32_gpio.h" |
21 |
|
22 |
/*===========================================================================*/
|
23 |
/* Driver local definitions. */
|
24 |
/*===========================================================================*/
|
25 |
|
26 |
/*===========================================================================*/
|
27 |
/* Driver exported variables. */
|
28 |
/*===========================================================================*/
|
29 |
|
30 |
/*===========================================================================*/
|
31 |
/* Driver local variables and types. */
|
32 |
/*===========================================================================*/
|
33 |
|
34 |
/**
|
35 |
* @brief Type of STM32 GPIO port setup.
|
36 |
*/
|
37 |
typedef struct { |
38 |
uint32_t moder; |
39 |
uint32_t otyper; |
40 |
uint32_t ospeedr; |
41 |
uint32_t pupdr; |
42 |
uint32_t odr; |
43 |
uint32_t afrl; |
44 |
uint32_t afrh; |
45 |
uint32_t ascr; |
46 |
uint32_t lockr; |
47 |
} gpio_setup_t; |
48 |
|
49 |
/**
|
50 |
* @brief Type of STM32 GPIO initialization data.
|
51 |
*/
|
52 |
typedef struct { |
53 |
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
54 |
gpio_setup_t PAData; |
55 |
#endif
|
56 |
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
57 |
gpio_setup_t PBData; |
58 |
#endif
|
59 |
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
60 |
gpio_setup_t PCData; |
61 |
#endif
|
62 |
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
63 |
gpio_setup_t PDData; |
64 |
#endif
|
65 |
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
66 |
gpio_setup_t PEData; |
67 |
#endif
|
68 |
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
69 |
gpio_setup_t PFData; |
70 |
#endif
|
71 |
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
72 |
gpio_setup_t PGData; |
73 |
#endif
|
74 |
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
75 |
gpio_setup_t PHData; |
76 |
#endif
|
77 |
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
78 |
gpio_setup_t PIData; |
79 |
#endif
|
80 |
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
81 |
gpio_setup_t PJData; |
82 |
#endif
|
83 |
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
84 |
gpio_setup_t PKData; |
85 |
#endif
|
86 |
} gpio_config_t; |
87 |
|
88 |
/**
|
89 |
* @brief STM32 GPIO static initialization data.
|
90 |
*/
|
91 |
static const gpio_config_t gpio_default_config = { |
92 |
#if STM32_HAS_GPIOA
|
93 |
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
94 |
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, |
95 |
VAL_GPIOA_LOCKR}, |
96 |
#endif
|
97 |
#if STM32_HAS_GPIOB
|
98 |
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
99 |
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, |
100 |
VAL_GPIOB_LOCKR}, |
101 |
#endif
|
102 |
#if STM32_HAS_GPIOC
|
103 |
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
104 |
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, |
105 |
VAL_GPIOC_LOCKR}, |
106 |
#endif
|
107 |
#if STM32_HAS_GPIOD
|
108 |
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
109 |
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, |
110 |
VAL_GPIOD_LOCKR}, |
111 |
#endif
|
112 |
#if STM32_HAS_GPIOE
|
113 |
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
114 |
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, |
115 |
VAL_GPIOE_LOCKR}, |
116 |
#endif
|
117 |
#if STM32_HAS_GPIOF
|
118 |
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
119 |
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, |
120 |
VAL_GPIOF_LOCKR}, |
121 |
#endif
|
122 |
#if STM32_HAS_GPIOG
|
123 |
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
124 |
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, |
125 |
VAL_GPIOG_LOCKR}, |
126 |
#endif
|
127 |
#if STM32_HAS_GPIOH
|
128 |
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
129 |
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, |
130 |
VAL_GPIOH_LOCKR}, |
131 |
#endif
|
132 |
#if STM32_HAS_GPIOI
|
133 |
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
134 |
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, |
135 |
VAL_GPIOI_LOCKR}, |
136 |
#endif
|
137 |
#if STM32_HAS_GPIOJ
|
138 |
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, |
139 |
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, |
140 |
VAL_GPIOJ_LOCKR}, |
141 |
#endif
|
142 |
#if STM32_HAS_GPIOK
|
143 |
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, |
144 |
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, |
145 |
VAL_GPIOK_LOCKR} |
146 |
#endif
|
147 |
}; |
148 |
|
149 |
/*===========================================================================*/
|
150 |
/* Driver local functions. */
|
151 |
/*===========================================================================*/
|
152 |
|
153 |
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { |
154 |
|
155 |
gpiop->OTYPER = config->otyper; |
156 |
gpiop->ASCR = config->ascr; |
157 |
gpiop->OSPEEDR = config->ospeedr; |
158 |
gpiop->PUPDR = config->pupdr; |
159 |
gpiop->ODR = config->odr; |
160 |
gpiop->AFRL = config->afrl; |
161 |
gpiop->AFRH = config->afrh; |
162 |
gpiop->MODER = config->moder; |
163 |
gpiop->LOCKR = config->lockr; |
164 |
} |
165 |
|
166 |
static void stm32_gpio_init(void) { |
167 |
|
168 |
/* Enabling GPIO-related clocks, the mask comes from the
|
169 |
registry header file.*/
|
170 |
rccResetAHB2(STM32_GPIO_EN_MASK); |
171 |
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
|
172 |
|
173 |
/* Initializing all the defined GPIO ports.*/
|
174 |
#if STM32_HAS_GPIOA
|
175 |
gpio_init(GPIOA, &gpio_default_config.PAData); |
176 |
#endif
|
177 |
#if STM32_HAS_GPIOB
|
178 |
gpio_init(GPIOB, &gpio_default_config.PBData); |
179 |
#endif
|
180 |
#if STM32_HAS_GPIOC
|
181 |
gpio_init(GPIOC, &gpio_default_config.PCData); |
182 |
#endif
|
183 |
#if STM32_HAS_GPIOD
|
184 |
gpio_init(GPIOD, &gpio_default_config.PDData); |
185 |
#endif
|
186 |
#if STM32_HAS_GPIOE
|
187 |
gpio_init(GPIOE, &gpio_default_config.PEData); |
188 |
#endif
|
189 |
#if STM32_HAS_GPIOF
|
190 |
gpio_init(GPIOF, &gpio_default_config.PFData); |
191 |
#endif
|
192 |
#if STM32_HAS_GPIOG
|
193 |
gpio_init(GPIOG, &gpio_default_config.PGData); |
194 |
#endif
|
195 |
#if STM32_HAS_GPIOH
|
196 |
gpio_init(GPIOH, &gpio_default_config.PHData); |
197 |
#endif
|
198 |
#if STM32_HAS_GPIOI
|
199 |
gpio_init(GPIOI, &gpio_default_config.PIData); |
200 |
#endif
|
201 |
#if STM32_HAS_GPIOJ
|
202 |
gpio_init(GPIOJ, &gpio_default_config.PJData); |
203 |
#endif
|
204 |
#if STM32_HAS_GPIOK
|
205 |
gpio_init(GPIOK, &gpio_default_config.PKData); |
206 |
#endif
|
207 |
} |
208 |
|
209 |
/*===========================================================================*/
|
210 |
/* Driver interrupt handlers. */
|
211 |
/*===========================================================================*/
|
212 |
|
213 |
/*===========================================================================*/
|
214 |
/* Driver exported functions. */
|
215 |
/*===========================================================================*/
|
216 |
|
217 |
/**
|
218 |
* @brief Early initialization code.
|
219 |
* @details GPIO ports and system clocks are initialized before everything
|
220 |
* else.
|
221 |
*/
|
222 |
void __early_init(void) { |
223 |
|
224 |
stm32_gpio_init(); |
225 |
stm32_clock_init(); |
226 |
} |
227 |
|
228 |
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
229 |
/**
|
230 |
* @brief SDC card detection.
|
231 |
*/
|
232 |
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
233 |
|
234 |
(void)sdcp;
|
235 |
/* TODO: Fill the implementation.*/
|
236 |
return true; |
237 |
} |
238 |
|
239 |
/**
|
240 |
* @brief SDC card write protection detection.
|
241 |
*/
|
242 |
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
243 |
|
244 |
(void)sdcp;
|
245 |
/* TODO: Fill the implementation.*/
|
246 |
return false; |
247 |
} |
248 |
#endif /* HAL_USE_SDC */ |
249 |
|
250 |
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
251 |
/**
|
252 |
* @brief MMC_SPI card detection.
|
253 |
*/
|
254 |
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
255 |
|
256 |
(void)mmcp;
|
257 |
/* TODO: Fill the implementation.*/
|
258 |
return true; |
259 |
} |
260 |
|
261 |
/**
|
262 |
* @brief MMC_SPI card write protection detection.
|
263 |
*/
|
264 |
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
265 |
|
266 |
(void)mmcp;
|
267 |
/* TODO: Fill the implementation.*/
|
268 |
return false; |
269 |
} |
270 |
#endif
|
271 |
|
272 |
/**
|
273 |
* @brief Board-specific initialization code.
|
274 |
* @todo Add your board-specific code, if any.
|
275 |
*/
|
276 |
void boardInit(void) { |
277 |
|
278 |
} |