Revision 10853947
| modules/BI-Vital_5-1/Makefile | ||
|---|---|---|
| 1 |
################################################################################ |
|
| 2 |
# AMiRo-OS is an operating system designed for the Autonomous Mini Robot # |
|
| 3 |
# (AMiRo) platform. # |
|
| 4 |
# Copyright (C) 2016..2020 Thomas Schöpping et al. # |
|
| 5 |
# # |
|
| 6 |
# This program is free software: you can redistribute it and/or modify # |
|
| 7 |
# it under the terms of the GNU General Public License as published by # |
|
| 8 |
# the Free Software Foundation, either version 3 of the License, or # |
|
| 9 |
# (at your option) any later version. # |
|
| 10 |
# # |
|
| 11 |
# This program is distributed in the hope that it will be useful, # |
|
| 12 |
# but WITHOUT ANY WARRANTY; without even the implied warranty of # |
|
| 13 |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # |
|
| 14 |
# GNU General Public License for more details. # |
|
| 15 |
# # |
|
| 16 |
# You should have received a copy of the GNU General Public License # |
|
| 17 |
# along with this program. If not, see <http://www.gnu.org/licenses/>. # |
|
| 18 |
# # |
|
| 19 |
# This research/work was supported by the Cluster of Excellence Cognitive # |
|
| 20 |
# Interaction Technology 'CITEC' (EXC 277) at Bielefeld University, which is # |
|
| 21 |
# funded by the German Research Foundation (DFG). # |
|
| 22 |
################################################################################ |
|
| 23 |
|
|
| 24 |
|
|
| 25 |
|
|
| 26 |
################################################################################ |
|
| 27 |
# Build global options # |
|
| 28 |
# NOTE: Can be overridden externally. # |
|
| 29 |
# # |
|
| 30 |
|
|
| 31 |
# Compiler options here. |
|
| 32 |
ifeq ($(USE_OPT),) |
|
| 33 |
USE_OPT = -O2 -fstack-usage |
|
| 34 |
endif |
|
| 35 |
|
|
| 36 |
# C specific options here (added to USE_OPT). |
|
| 37 |
ifeq ($(USE_COPT),) |
|
| 38 |
USE_COPT = -std=c99 -fshort-enums |
|
| 39 |
endif |
|
| 40 |
|
|
| 41 |
# C++ specific options here (added to USE_OPT). |
|
| 42 |
ifeq ($(USE_CPPOPT),) |
|
| 43 |
USE_CPPOPT = -fno-rtti -std=c++17 |
|
| 44 |
endif |
|
| 45 |
|
|
| 46 |
# Enable this if you want the linker to remove unused code and data. |
|
| 47 |
ifeq ($(USE_LINK_GC),) |
|
| 48 |
USE_LINK_GC = yes |
|
| 49 |
endif |
|
| 50 |
|
|
| 51 |
# Linker extra options here. |
|
| 52 |
ifeq ($(USE_LDOPT),) |
|
| 53 |
USE_LDOPT = |
|
| 54 |
endif |
|
| 55 |
|
|
| 56 |
# Enable this if you want link time optimizations (LTO). |
|
| 57 |
ifeq ($(USE_LTO),) |
|
| 58 |
USE_LTO = yes |
|
| 59 |
endif |
|
| 60 |
|
|
| 61 |
# Enable this if you want to see the full log while compiling. |
|
| 62 |
ifeq ($(USE_VERBOSE_COMPILE),) |
|
| 63 |
USE_VERBOSE_COMPILE = no |
|
| 64 |
endif |
|
| 65 |
|
|
| 66 |
# If enabled, this option makes the build process faster by not compiling |
|
| 67 |
# modules not used in the current configuration. |
|
| 68 |
ifeq ($(USE_SMART_BUILD),) |
|
| 69 |
USE_SMART_BUILD = no |
|
| 70 |
endif |
|
| 71 |
|
|
| 72 |
# # |
|
| 73 |
# Build global options # |
|
| 74 |
################################################################################ |
|
| 75 |
|
|
| 76 |
################################################################################ |
|
| 77 |
# Architecture or project specific options # |
|
| 78 |
# # |
|
| 79 |
|
|
| 80 |
# Stack size to be allocated to the Cortex-M process stack. This stack is |
|
| 81 |
# the stack used by the main() thread. |
|
| 82 |
ifeq ($(USE_PROCESS_STACKSIZE),) |
|
| 83 |
USE_PROCESS_STACKSIZE = 0x400 |
|
| 84 |
endif |
|
| 85 |
|
|
| 86 |
# Stack size to the allocated to the Cortex-M main/exceptions stack. This |
|
| 87 |
# stack is used for processing interrupts and exceptions. |
|
| 88 |
ifeq ($(USE_EXCEPTIONS_STACKSIZE),) |
|
| 89 |
USE_EXCEPTIONS_STACKSIZE = 0x400 |
|
| 90 |
endif |
|
| 91 |
|
|
| 92 |
# Enables the use of FPU. |
|
| 93 |
# Possible selections are: |
|
| 94 |
# no - no FPU is used (probably equals 'soft') |
|
| 95 |
# soft - does not use the FPU, thus all floating point operations are emulated |
|
| 96 |
# softfp - uses the FPU, but uses the integer registers only |
|
| 97 |
# hard - uses the FPU and passes data via the FPU registers |
|
| 98 |
ifeq ($(USE_FPU),) |
|
| 99 |
USE_FPU = softfp |
|
| 100 |
endif |
|
| 101 |
|
|
| 102 |
# FPU-related options. |
|
| 103 |
ifeq ($(USE_FPU_OPT),) |
|
| 104 |
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 |
|
| 105 |
endif |
|
| 106 |
|
|
| 107 |
# # |
|
| 108 |
# Architecture or project specific options # |
|
| 109 |
################################################################################ |
|
| 110 |
|
|
| 111 |
################################################################################ |
|
| 112 |
# Project, target, sources and paths # |
|
| 113 |
# # |
|
| 114 |
|
|
| 115 |
# Absolute path to the project. |
|
| 116 |
PROJECT_PATH := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) |
|
| 117 |
|
|
| 118 |
# Project name. |
|
| 119 |
PROJECT := $(notdir $(PROJECT_PATH)) |
|
| 120 |
|
|
| 121 |
# Target settings. |
|
| 122 |
MCU := cortex-m4 |
|
| 123 |
|
|
| 124 |
# Module specific paths and directories. |
|
| 125 |
MODULE_DIR := . |
|
| 126 |
CONFIG_DIR := $(MODULEDIR) |
|
| 127 |
ifeq ($(BUILDDIR),) |
|
| 128 |
BUILDDIR := $(PROJECT_PATH)/build |
|
| 129 |
endif |
|
| 130 |
DEPDIR := $(dir $(BUILDDIR)).dep |
|
| 131 |
|
|
| 132 |
# Linker script. |
|
| 133 |
LDSCRIPT := $(MODULE_DIR)/STM32L476xG.ld |
|
| 134 |
|
|
| 135 |
# General AMiRo-OS files. |
|
| 136 |
include ../../amiro-os.mk |
|
| 137 |
|
|
| 138 |
# Module specific ChibiOS files. |
|
| 139 |
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk |
|
| 140 |
include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk |
|
| 141 |
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk |
|
| 142 |
|
|
| 143 |
# Module specific periphery LLDs. |
|
| 144 |
|
|
| 145 |
# Module specific inclusion directories |
|
| 146 |
MODULE_INC = $(MODULE_DIR) |
|
| 147 |
|
|
| 148 |
# Module specific C source files. |
|
| 149 |
MODULE_CSRC = $(MODULE_DIR)/board.c \ |
|
| 150 |
$(MODULE_DIR)/module.c |
|
| 151 |
|
|
| 152 |
# Module specific tests. |
|
| 153 |
|
|
| 154 |
# C warning options. |
|
| 155 |
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes |
|
| 156 |
|
|
| 157 |
# C++ warning options. |
|
| 158 |
CPPWARN = -Wall -Wextra -Wundef |
|
| 159 |
|
|
| 160 |
# # |
|
| 161 |
# Project, target, sources and paths # |
|
| 162 |
################################################################################ |
|
| 163 |
|
|
| 164 |
################################################################################ |
|
| 165 |
# Start of user section # |
|
| 166 |
# # |
|
| 167 |
|
|
| 168 |
# List all user C define here, like -D_DEBUG=1 |
|
| 169 |
UDEFS += |
|
| 170 |
|
|
| 171 |
# Define ASM defines here |
|
| 172 |
UADEFS += |
|
| 173 |
|
|
| 174 |
# List all user directories here |
|
| 175 |
UINCDIR += |
|
| 176 |
|
|
| 177 |
# List the user directory to look for the libraries here |
|
| 178 |
ULIBDIR += |
|
| 179 |
|
|
| 180 |
# List all user libraries here |
|
| 181 |
ULIBS += |
|
| 182 |
|
|
| 183 |
# # |
|
| 184 |
# End of user section # |
|
| 185 |
################################################################################ |
|
| 186 |
|
|
| 187 |
################################################################################ |
|
| 188 |
# Common rules # |
|
| 189 |
# # |
|
| 190 |
|
|
| 191 |
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk |
|
| 192 |
include $(RULESPATH)/arm-none-eabi.mk |
|
| 193 |
include $(RULESPATH)/rules.mk |
|
| 194 |
|
|
| 195 |
# # |
|
| 196 |
# Common rules # |
|
| 197 |
################################################################################ |
|
| 198 |
|
|
| 199 |
################################################################################ |
|
| 200 |
# Custom rules # |
|
| 201 |
# # |
|
| 202 |
|
|
| 203 |
flash: $(BUILDDIR)/$(PROJECT).elf |
|
| 204 |
openocd -f interface/jlink.cfg -c "transport select swd" -c "set WORKAREASIZE 0x2000" -f target/stm32l4x.cfg -c "program $(BUILDDIR)/$(PROJECT).elf verify reset exit" |
|
| 205 |
|
|
| 206 |
# # |
|
| 207 |
# Custom rules # |
|
| 208 |
################################################################################ |
|
| 209 |
|
|
| modules/BI-Vital_5-1/STM32L476xJ.ld | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2020 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/* |
|
| 20 |
* STM32L476xJ memory setup. |
|
| 21 |
*/ |
|
| 22 |
MEMORY |
|
| 23 |
{
|
|
| 24 |
flash0 : org = 0x08000000, len = 512K |
|
| 25 |
flash1 : org = 0x00000000, len = 0 |
|
| 26 |
flash2 : org = 0x00000000, len = 0 |
|
| 27 |
flash3 : org = 0x00000000, len = 0 |
|
| 28 |
flash4 : org = 0x00000000, len = 0 |
|
| 29 |
flash5 : org = 0x00000000, len = 0 |
|
| 30 |
flash6 : org = 0x00000000, len = 0 |
|
| 31 |
flash7 : org = 0x00000000, len = 0 |
|
| 32 |
ram0 : org = 0x20000000, len = 96k |
|
| 33 |
ram1 : org = 0x00000000, len = 0 |
|
| 34 |
ram2 : org = 0x00000000, len = 0 |
|
| 35 |
ram3 : org = 0x00000000, len = 0 |
|
| 36 |
ram4 : org = 0x10000000, len = 32k |
|
| 37 |
ram5 : org = 0x00000000, len = 0 |
|
| 38 |
ram6 : org = 0x00000000, len = 0 |
|
| 39 |
ram7 : org = 0x00000000, len = 0 |
|
| 40 |
} |
|
| 41 |
|
|
| 42 |
/* For each data/text section two region are defined, a virtual region |
|
| 43 |
and a load region (_LMA suffix).*/ |
|
| 44 |
|
|
| 45 |
/* Flash region to be used for exception vectors.*/ |
|
| 46 |
REGION_ALIAS("VECTORS_FLASH", flash0);
|
|
| 47 |
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
|
| 48 |
|
|
| 49 |
/* Flash region to be used for constructors and destructors.*/ |
|
| 50 |
REGION_ALIAS("XTORS_FLASH", flash0);
|
|
| 51 |
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
|
| 52 |
|
|
| 53 |
/* Flash region to be used for code text.*/ |
|
| 54 |
REGION_ALIAS("TEXT_FLASH", flash0);
|
|
| 55 |
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
|
| 56 |
|
|
| 57 |
/* Flash region to be used for read only data.*/ |
|
| 58 |
REGION_ALIAS("RODATA_FLASH", flash0);
|
|
| 59 |
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
|
| 60 |
|
|
| 61 |
/* Flash region to be used for various.*/ |
|
| 62 |
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
|
| 63 |
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
|
| 64 |
|
|
| 65 |
/* Flash region to be used for RAM(n) initialization data.*/ |
|
| 66 |
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
|
| 67 |
|
|
| 68 |
/* RAM region to be used for Main stack. This stack accommodates the processing |
|
| 69 |
of all exceptions and interrupts.*/ |
|
| 70 |
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
|
| 71 |
|
|
| 72 |
/* RAM region to be used for the process stack. This is the stack used by |
|
| 73 |
the main() function.*/ |
|
| 74 |
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
|
| 75 |
|
|
| 76 |
/* RAM region to be used for data segment.*/ |
|
| 77 |
REGION_ALIAS("DATA_RAM", ram0);
|
|
| 78 |
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
|
| 79 |
|
|
| 80 |
/* RAM region to be used for BSS segment.*/ |
|
| 81 |
REGION_ALIAS("BSS_RAM", ram0);
|
|
| 82 |
|
|
| 83 |
/* RAM region to be used for the default heap.*/ |
|
| 84 |
REGION_ALIAS("HEAP_RAM", ram0);
|
|
| 85 |
|
|
| 86 |
/* RAM region with parity check. */ |
|
| 87 |
REGION_ALIAS("PARCHECK_RAM", ram4);
|
|
| 88 |
|
|
| 89 |
/* RAM region retainable in Standby mode. */ |
|
| 90 |
REGION_ALIAS("TANDBY_RAM", ram4);
|
|
| 91 |
|
|
| 92 |
/* RAM region that is write-protectable. */ |
|
| 93 |
REGION_ALIAS("WPROTECTED_RAM", ram4);
|
|
| 94 |
|
|
| 95 |
/* Generic rules inclusion.*/ |
|
| 96 |
INCLUDE rules.ld |
|
| modules/BI-Vital_5-1/alldconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2020 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief AMiRo-LLD configuration file for the BI-Vital (BGv5.1) module. |
|
| 22 |
* @details Contains the application specific AMiRo-LLD settings. |
|
| 23 |
* |
|
| 24 |
* @addtogroup BI-Vital_5.1_config |
|
| 25 |
* @{
|
|
| 26 |
*/ |
|
| 27 |
|
|
| 28 |
#ifndef ALLDCONF_H |
|
| 29 |
#define ALLDCONF_H |
|
| 30 |
|
|
| 31 |
/* |
|
| 32 |
* common configuration |
|
| 33 |
*/ |
|
| 34 |
#include <aos_alldconf.h> |
|
| 35 |
|
|
| 36 |
#endif /* ALLDCONF_H */ |
|
| 37 |
|
|
| 38 |
/** @} */ |
|
| modules/BI-Vital_5-1/aosconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2020 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief AMiRo-OS Configuration file for the BI-Vital (BGv5.1) module. |
|
| 22 |
* @details Contains the application specific AMiRo-OS settings. |
|
| 23 |
* |
|
| 24 |
* @addtogroup BI-Vital_5.1_aos_config |
|
| 25 |
* @{
|
|
| 26 |
*/ |
|
| 27 |
|
|
| 28 |
#ifndef AOSCONF_H |
|
| 29 |
#define AOSCONF_H |
|
| 30 |
|
|
| 31 |
/* |
|
| 32 |
* compatibility guards |
|
| 33 |
*/ |
|
| 34 |
#define _AMIRO_OS_CFG_ |
|
| 35 |
#define AMIRO_OS_CFG_VERSION_MAJOR 2 |
|
| 36 |
#define AMIRO_OS_CFG_VERSION_MINOR 1 |
|
| 37 |
|
|
| 38 |
#include <stdbool.h> |
|
| 39 |
|
|
| 40 |
/* |
|
| 41 |
* Include an external configuration file to override the following default settings only if required. |
|
| 42 |
*/ |
|
| 43 |
#if defined(AMIRO_APPS) && (AMIRO_APPS == true) |
|
| 44 |
#include <osconf.h> |
|
| 45 |
#endif /* defined(AMIRO_APPS) && (AMIRO_APPS == true) */ |
|
| 46 |
|
|
| 47 |
/*===========================================================================*/ |
|
| 48 |
/** |
|
| 49 |
* @name Kernel parameters and options |
|
| 50 |
* @{
|
|
| 51 |
*/ |
|
| 52 |
/*===========================================================================*/ |
|
| 53 |
|
|
| 54 |
/** |
|
| 55 |
* @brief Flag to enable/disable debug API and logic. |
|
| 56 |
*/ |
|
| 57 |
#if !defined(OS_CFG_DBG) |
|
| 58 |
#define AMIROOS_CFG_DBG true |
|
| 59 |
#else /* !defined(OS_CFG_DBG) */ |
|
| 60 |
#define AMIROOS_CFG_DBG OS_CFG_DBG |
|
| 61 |
#endif /* !defined(OS_CFG_DBG) */ |
|
| 62 |
|
|
| 63 |
/** |
|
| 64 |
* @brief Flag to enable/disable unit tests. |
|
| 65 |
* @note Setting this flag will implicitely enable the shell. |
|
| 66 |
*/ |
|
| 67 |
#if !defined(OS_CFG_TESTS_ENABLE) |
|
| 68 |
#define AMIROOS_CFG_TESTS_ENABLE true |
|
| 69 |
#else /* !defined(OS_CFG_TESTS_ENABLE) */ |
|
| 70 |
#define AMIROOS_CFG_TESTS_ENABLE OS_CFG_TESTS_ENABLE |
|
| 71 |
#endif /* !defined(OS_CFG_TESTS_ENABLE) */ |
|
| 72 |
|
|
| 73 |
/** |
|
| 74 |
* @brief Flag to enable/disable profiling API and logic. |
|
| 75 |
*/ |
|
| 76 |
#if !defined(OS_CFG_PROFILE) |
|
| 77 |
#define AMIROOS_CFG_PROFILE true |
|
| 78 |
#else /* !defined(OS_CFG_PROFILE) */ |
|
| 79 |
#define AMIROOS_CFG_PROFILE OS_CFG_PROFILE |
|
| 80 |
#endif /* !defined(OS_CFG_PROFILE) */ |
|
| 81 |
|
|
| 82 |
/** |
|
| 83 |
* @brief Mask for the control thread to listen to certain GPIO events. |
|
| 84 |
* @note Any mandatory events (e.g. for SSSP) are enabled implicitely despite this configuration. |
|
| 85 |
*/ |
|
| 86 |
#if !defined(OS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK) |
|
| 87 |
#define AMIROOS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK 0 |
|
| 88 |
#else /* !defined(OS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK) */ |
|
| 89 |
#define AMIROOS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK OS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK |
|
| 90 |
#endif /* !defined(OS_CFG_MAIN_LOOP_GPIOEVENT_FLAGSMASK) */ |
|
| 91 |
|
|
| 92 |
/** |
|
| 93 |
* @brief Timeout value when waiting for events in the main loop in microseconds. |
|
| 94 |
* @details A value of 0 deactivates the timeout. |
|
| 95 |
*/ |
|
| 96 |
#if !defined(OS_CFG_MAIN_LOOP_TIMEOUT) |
|
| 97 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT 0 |
|
| 98 |
#else /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */ |
|
| 99 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT OS_CFG_MAIN_LOOP_TIMEOUT |
|
| 100 |
#endif /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */ |
|
| 101 |
|
|
| 102 |
/** @} */ |
|
| 103 |
|
|
| 104 |
/*===========================================================================*/ |
|
| 105 |
/** |
|
| 106 |
* @name Bootloader configuration |
|
| 107 |
* @{
|
|
| 108 |
*/ |
|
| 109 |
/*===========================================================================*/ |
|
| 110 |
|
|
| 111 |
/** |
|
| 112 |
* @brief Identifier of the instaled bootloader (if any). |
|
| 113 |
* @note See aos_bootloader.h file for a list of available settings. |
|
| 114 |
*/ |
|
| 115 |
#if !defined(OS_CFG_BOOTLOADER) |
|
| 116 |
#define AMIROOS_CFG_BOOTLOADER AOS_BOOTLOADER_NONE |
|
| 117 |
#else /* !defined(OS_CFG_BOOTLOADER) */ |
|
| 118 |
#define AMIROOS_CFG_BOOTLOADER OS_CFG_BOOTLOADER |
|
| 119 |
#endif /* !defined(OS_CFG_BOOTLOADER) */ |
|
| 120 |
|
|
| 121 |
/** @} */ |
|
| 122 |
|
|
| 123 |
/*===========================================================================*/ |
|
| 124 |
/** |
|
| 125 |
* @name SSSP (Startup Shutdown Synchronization Protocol) configuration. |
|
| 126 |
* @{
|
|
| 127 |
*/ |
|
| 128 |
/*===========================================================================*/ |
|
| 129 |
|
|
| 130 |
/** |
|
| 131 |
* @brief Flag to enable SSSP. |
|
| 132 |
*/ |
|
| 133 |
#if !defined(OS_CFG_SSSP_ENABLE) |
|
| 134 |
#define AMIROOS_CFG_SSSP_ENABLE false |
|
| 135 |
#else /* !defined(OS_CFG_SSSP_ENABLE) */ |
|
| 136 |
#define AMIROOS_CFG_SSSP_ENABLE OS_CFG_SSSP_ENABLE |
|
| 137 |
#endif /* !defined(OS_CFG_SSSP_ENABLE) */ |
|
| 138 |
|
|
| 139 |
/** |
|
| 140 |
* @brief Flag to indicate, whether the SSSP startup sequence shall be executed by AMiRo-OS. |
|
| 141 |
* @details This setting must be false in case another software (e.g. a bootloader) handles the initial stages of the SSSP startup phase. |
|
| 142 |
*/ |
|
| 143 |
#if !defined(OS_CFG_SSSP_STARTUP) |
|
| 144 |
#define AMIROOS_CFG_SSSP_STARTUP false |
|
| 145 |
#else |
|
| 146 |
#define AMIROOS_CFG_SSSP_STARTUP OS_CFG_SSSP_STARTUP |
|
| 147 |
#endif |
|
| 148 |
|
|
| 149 |
/** |
|
| 150 |
* @brief Flag to indicate, whether the SSSP shutdown sequence shall be executed by AMiRo-OS. |
|
| 151 |
* @details This setting should be false in case another software (e.g. a bootloader) handles the final stages of the SSSP shutdown phase. |
|
| 152 |
*/ |
|
| 153 |
#if !defined(OS_CFG_SSSP_SHUTDOWN) |
|
| 154 |
#define AMIROOS_CFG_SSSP_SHUTDOWN false |
|
| 155 |
#else |
|
| 156 |
#define AMIROOS_CFG_SSSP_SHUTDOWN OS_CFG_SSSP_SHUTDOWN |
|
| 157 |
#endif |
|
| 158 |
|
|
| 159 |
/** |
|
| 160 |
* @brief Flag to indicate, whether the module stack initialization (MSI; stage 3 of the SSSP startup phase) shall be executed. |
|
| 161 |
* @brief In order to execute MSI, a broadcast bus (BCB) and according interfaces must be defined. |
|
| 162 |
*/ |
|
| 163 |
#if !defined(OS_CFG_SSSP_MSI) |
|
| 164 |
#define AMIROOS_CFG_SSSP_MSI false |
|
| 165 |
#else |
|
| 166 |
#define AMIROOS_CFG_SSSP_MSI OS_CFG_SSSP_MSI |
|
| 167 |
#endif |
|
| 168 |
|
|
| 169 |
/** |
|
| 170 |
* @brief Width of the @p aos_sssp_moduleid_t type. |
|
| 171 |
* @details Possible settings are 8, 16, 32 and 64. |
|
| 172 |
*/ |
|
| 173 |
#if !defined(OS_CFG_SSSP_MODULEIDWIDTH) |
|
| 174 |
#define AMIROOS_CFG_SSSP_MODULEIDWIDTH 16 |
|
| 175 |
#else |
|
| 176 |
#define AMIROOS_CFG_SSSP_MODULEIDWIDTH OS_CFG_SSSP_MODULEIDWIDTH |
|
| 177 |
#endif |
|
| 178 |
|
|
| 179 |
/** |
|
| 180 |
* @brief Flag to set the module as SSSP master. |
|
| 181 |
* @details There must be only one module with this flag set to true in a system. |
|
| 182 |
*/ |
|
| 183 |
#if !defined(OS_CFG_SSSP_MASTER) |
|
| 184 |
#define AMIROOS_CFG_SSSP_MASTER false |
|
| 185 |
#else /* !defined(OS_CFG_SSSP_MASTER) */ |
|
| 186 |
#define AMIROOS_CFG_SSSP_MASTER OS_CFG_SSSP_MASTER |
|
| 187 |
#endif /* !defined(OS_CFG_SSSP_MASTER) */ |
|
| 188 |
|
|
| 189 |
/** |
|
| 190 |
* @brief Flag to set the module to be the first in the stack. |
|
| 191 |
* @details There must be only one module with this flag set to true in a system. |
|
| 192 |
*/ |
|
| 193 |
#if !defined(OS_CFG_SSSP_STACK_START) |
|
| 194 |
#define AMIROOS_CFG_SSSP_STACK_START false |
|
| 195 |
#else /* !defined(OS_CFG_SSSP_STACK_START) */ |
|
| 196 |
#define AMIROOS_CFG_SSSP_STACK_START OS_CFG_SSSP_STACK_START |
|
| 197 |
#endif /* !defined(OS_CFG_SSSP_STACK_START) */ |
|
| 198 |
|
|
| 199 |
/** |
|
| 200 |
* @brief Flag to set the module to be the last in the stack. |
|
| 201 |
* @details There must be only one module with this flag set to true in a system. |
|
| 202 |
*/ |
|
| 203 |
#if !defined(OS_CFG_SSSP_STACK_END) |
|
| 204 |
#define AMIROOS_CFG_SSSP_STACK_END false |
|
| 205 |
#else /* !defined(OS_CFG_SSSP_STACK_END) */ |
|
| 206 |
#define AMIROOS_CFG_SSSP_STACK_END OS_CFG_SSSP_STACK_END |
|
| 207 |
#endif /* !defined(OS_CFG_SSSP_STACK_END) */ |
|
| 208 |
|
|
| 209 |
/** |
|
| 210 |
* @brief Delay time (in microseconds) how long a SSSP signal must be active. |
|
| 211 |
*/ |
|
| 212 |
#if !defined(OS_CFG_SSSP_SIGNALDELAY) |
|
| 213 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY 1000 |
|
| 214 |
#else /* !defined(OS_CFG_SSSP_SIGNALDELAY) */ |
|
| 215 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY OS_CFG_SSSP_SIGNALDELAY |
|
| 216 |
#endif /* !defined(OS_CFG_SSSP_SIGNALDELAY) */ |
|
| 217 |
|
|
| 218 |
/** |
|
| 219 |
* @brief Time boundary for robot wide clock synchronization in microseconds. |
|
| 220 |
* @details Whenever the SSSP S (snychronization) signal gets logically deactivated, |
|
| 221 |
* All modules need to align their local uptime to the nearest multiple of this value. |
|
| 222 |
*/ |
|
| 223 |
#if !defined(OS_CFG_SSSP_SYSSYNCPERIOD) |
|
| 224 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD 1000000 |
|
| 225 |
#else /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */ |
|
| 226 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD OS_CFG_SSSP_SYSSYNCPERIOD |
|
| 227 |
#endif /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */ |
|
| 228 |
|
|
| 229 |
/** @} */ |
|
| 230 |
|
|
| 231 |
/*===========================================================================*/ |
|
| 232 |
/** |
|
| 233 |
* @name System shell options |
|
| 234 |
* @{
|
|
| 235 |
*/ |
|
| 236 |
/*===========================================================================*/ |
|
| 237 |
|
|
| 238 |
/** |
|
| 239 |
* @brief Shell enable flag. |
|
| 240 |
*/ |
|
| 241 |
#if !defined(OS_CFG_SHELL_ENABLE) |
|
| 242 |
#define AMIROOS_CFG_SHELL_ENABLE true |
|
| 243 |
#else /* !defined(OS_CFG_SHELL_ENABLE) */ |
|
| 244 |
#define AMIROOS_CFG_SHELL_ENABLE OS_CFG_SHELL_ENABLE |
|
| 245 |
#endif /* !defined(OS_CFG_SHELL_ENABLE) */ |
|
| 246 |
|
|
| 247 |
/** |
|
| 248 |
* @brief Shell thread stack size. |
|
| 249 |
*/ |
|
| 250 |
#if !defined(OS_CFG_SHELL_STACKSIZE) |
|
| 251 |
#define AMIROOS_CFG_SHELL_STACKSIZE 1024 |
|
| 252 |
#else /* !defined(OS_CFG_SHELL_STACKSIZE) */ |
|
| 253 |
#define AMIROOS_CFG_SHELL_STACKSIZE OS_CFG_SHELL_STACKSIZE |
|
| 254 |
#endif /* !defined(OS_CFG_SHELL_STACKSIZE) */ |
|
| 255 |
|
|
| 256 |
/** |
|
| 257 |
* @brief Shell thread priority. |
|
| 258 |
* @details Thread priorities are specified as an integer value. |
|
| 259 |
* Predefined ranges are: |
|
| 260 |
* lowest ┌ THD_LOWPRIO_MIN |
|
| 261 |
* │ ... |
|
| 262 |
* └ THD_LOWPRIO_MAX |
|
| 263 |
* ┌ THD_NORMALPRIO_MIN |
|
| 264 |
* │ ... |
|
| 265 |
* └ THD_NORMALPRIO_MAX |
|
| 266 |
* ┌ THD_HIGHPRIO_MIN |
|
| 267 |
* │ ... |
|
| 268 |
* └ THD_HIGHPRIO_MAX |
|
| 269 |
* ┌ THD_RTPRIO_MIN |
|
| 270 |
* │ ... |
|
| 271 |
* highest └ THD_RTPRIO_MAX |
|
| 272 |
*/ |
|
| 273 |
#if !defined(OS_CFG_SHELL_THREADPRIO) |
|
| 274 |
#define AMIROOS_CFG_SHELL_THREADPRIO AOS_THD_NORMALPRIO_MIN |
|
| 275 |
#else /* !defined(OS_CFG_SHELL_THREADPRIO) */ |
|
| 276 |
#define AMIROOS_CFG_SHELL_THREADPRIO OS_CFG_SHELL_THREADPRIO |
|
| 277 |
#endif /* !defined(OS_CFG_SHELL_THREADPRIO) */ |
|
| 278 |
|
|
| 279 |
/** |
|
| 280 |
* @brief Shell maximum input line length. |
|
| 281 |
*/ |
|
| 282 |
#if !defined(OS_CFG_SHELL_LINEWIDTH) |
|
| 283 |
#define AMIROOS_CFG_SHELL_LINEWIDTH 64 |
|
| 284 |
#else /* !defined(OS_CFG_SHELL_LINEWIDTH) */ |
|
| 285 |
#define AMIROOS_CFG_SHELL_LINEWIDTH OS_CFG_SHELL_LINEWIDTH |
|
| 286 |
#endif /* !defined(OS_CFG_SHELL_LINEWIDTH) */ |
|
| 287 |
|
|
| 288 |
/** |
|
| 289 |
* @brief Shell maximum number of arguments. |
|
| 290 |
*/ |
|
| 291 |
#if !defined(OS_CFG_SHELL_MAXARGS) |
|
| 292 |
#define AMIROOS_CFG_SHELL_MAXARGS 8 |
|
| 293 |
#else /* !defined(OS_CFG_SHELL_MAXARGS) */ |
|
| 294 |
#define AMIROOS_CFG_SHELL_MAXARGS OS_CFG_SHELL_MAXARGS |
|
| 295 |
#endif /* !defined(OS_CFG_SHELL_MAXARGS) */ |
|
| 296 |
|
|
| 297 |
/** |
|
| 298 |
* @brief Shell number of history entries. |
|
| 299 |
* @details A value of 0 disables shell history. |
|
| 300 |
*/ |
|
| 301 |
#if !defined(OS_CFG_SHELL_HISTLENGTH) |
|
| 302 |
#define AMIROOS_CFG_SHELL_HISTLENGTH 3 |
|
| 303 |
#else /* !defined(OS_CFG_SHELL_HISTLENGTH) */ |
|
| 304 |
#define AMIROOS_CFG_SHELL_HISTLENGTH OS_CFG_SHELL_HISTLENGTH |
|
| 305 |
#endif /* !defined(OS_CFG_SHELL_HISTLENGTH) */ |
|
| 306 |
|
|
| 307 |
/** @} */ |
|
| 308 |
|
|
| 309 |
#endif /* AOSCONF_H */ |
|
| 310 |
|
|
| 311 |
/** @} */ |
|
| modules/BI-Vital_5-1/board.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2020 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
#include "hal.h" |
|
| 20 |
#include "stm32_gpio.h" |
|
| 21 |
|
|
| 22 |
/*===========================================================================*/ |
|
| 23 |
/* Driver local definitions. */ |
|
| 24 |
/*===========================================================================*/ |
|
| 25 |
|
|
| 26 |
/*===========================================================================*/ |
|
| 27 |
/* Driver exported variables. */ |
|
| 28 |
/*===========================================================================*/ |
|
| 29 |
|
|
| 30 |
/*===========================================================================*/ |
|
| 31 |
/* Driver local variables and types. */ |
|
| 32 |
/*===========================================================================*/ |
|
| 33 |
|
|
| 34 |
/** |
|
| 35 |
* @brief Type of STM32 GPIO port setup. |
|
| 36 |
*/ |
|
| 37 |
typedef struct {
|
|
| 38 |
uint32_t moder; |
|
| 39 |
uint32_t otyper; |
|
| 40 |
uint32_t ospeedr; |
|
| 41 |
uint32_t pupdr; |
|
| 42 |
uint32_t odr; |
|
| 43 |
uint32_t afrl; |
|
| 44 |
uint32_t afrh; |
|
| 45 |
uint32_t ascr; |
|
| 46 |
uint32_t lockr; |
|
| 47 |
} gpio_setup_t; |
|
| 48 |
|
|
| 49 |
/** |
|
| 50 |
* @brief Type of STM32 GPIO initialization data. |
|
| 51 |
*/ |
|
| 52 |
typedef struct {
|
|
| 53 |
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) |
|
| 54 |
gpio_setup_t PAData; |
|
| 55 |
#endif |
|
| 56 |
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) |
|
| 57 |
gpio_setup_t PBData; |
|
| 58 |
#endif |
|
| 59 |
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) |
|
| 60 |
gpio_setup_t PCData; |
|
| 61 |
#endif |
|
| 62 |
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) |
|
| 63 |
gpio_setup_t PDData; |
|
| 64 |
#endif |
|
| 65 |
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) |
|
| 66 |
gpio_setup_t PEData; |
|
| 67 |
#endif |
|
| 68 |
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) |
|
| 69 |
gpio_setup_t PFData; |
|
| 70 |
#endif |
|
| 71 |
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) |
|
| 72 |
gpio_setup_t PGData; |
|
| 73 |
#endif |
|
| 74 |
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) |
|
| 75 |
gpio_setup_t PHData; |
|
| 76 |
#endif |
|
| 77 |
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) |
|
| 78 |
gpio_setup_t PIData; |
|
| 79 |
#endif |
|
| 80 |
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) |
|
| 81 |
gpio_setup_t PJData; |
|
| 82 |
#endif |
|
| 83 |
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) |
|
| 84 |
gpio_setup_t PKData; |
|
| 85 |
#endif |
|
| 86 |
} gpio_config_t; |
|
| 87 |
|
|
| 88 |
/** |
|
| 89 |
* @brief STM32 GPIO static initialization data. |
|
| 90 |
*/ |
|
| 91 |
static const gpio_config_t gpio_default_config = {
|
|
| 92 |
#if STM32_HAS_GPIOA |
|
| 93 |
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
|
| 94 |
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, |
|
| 95 |
VAL_GPIOA_LOCKR}, |
|
| 96 |
#endif |
|
| 97 |
#if STM32_HAS_GPIOB |
|
| 98 |
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
|
| 99 |
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, |
|
| 100 |
VAL_GPIOB_LOCKR}, |
|
| 101 |
#endif |
|
| 102 |
#if STM32_HAS_GPIOC |
|
| 103 |
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
|
| 104 |
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, |
|
| 105 |
VAL_GPIOC_LOCKR}, |
|
| 106 |
#endif |
|
| 107 |
#if STM32_HAS_GPIOD |
|
| 108 |
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
|
| 109 |
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, |
|
| 110 |
VAL_GPIOD_LOCKR}, |
|
| 111 |
#endif |
|
| 112 |
#if STM32_HAS_GPIOE |
|
| 113 |
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
|
| 114 |
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, |
|
| 115 |
VAL_GPIOE_LOCKR}, |
|
| 116 |
#endif |
|
| 117 |
#if STM32_HAS_GPIOF |
|
| 118 |
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
|
| 119 |
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, |
|
| 120 |
VAL_GPIOF_LOCKR}, |
|
| 121 |
#endif |
|
| 122 |
#if STM32_HAS_GPIOG |
|
| 123 |
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
|
| 124 |
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, |
|
| 125 |
VAL_GPIOG_LOCKR}, |
|
| 126 |
#endif |
|
| 127 |
#if STM32_HAS_GPIOH |
|
| 128 |
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
|
| 129 |
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, |
|
| 130 |
VAL_GPIOH_LOCKR}, |
|
| 131 |
#endif |
|
| 132 |
#if STM32_HAS_GPIOI |
|
| 133 |
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
|
| 134 |
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, |
|
| 135 |
VAL_GPIOI_LOCKR}, |
|
| 136 |
#endif |
|
| 137 |
#if STM32_HAS_GPIOJ |
|
| 138 |
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
|
| 139 |
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, |
|
| 140 |
VAL_GPIOJ_LOCKR}, |
|
| 141 |
#endif |
|
| 142 |
#if STM32_HAS_GPIOK |
|
| 143 |
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
|
| 144 |
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, |
|
| 145 |
VAL_GPIOK_LOCKR} |
|
| 146 |
#endif |
|
| 147 |
}; |
|
| 148 |
|
|
| 149 |
/*===========================================================================*/ |
|
| 150 |
/* Driver local functions. */ |
|
| 151 |
/*===========================================================================*/ |
|
| 152 |
|
|
| 153 |
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
|
| 154 |
|
|
| 155 |
gpiop->OTYPER = config->otyper; |
|
| 156 |
gpiop->ASCR = config->ascr; |
|
| 157 |
gpiop->OSPEEDR = config->ospeedr; |
|
| 158 |
gpiop->PUPDR = config->pupdr; |
|
| 159 |
gpiop->ODR = config->odr; |
|
| 160 |
gpiop->AFRL = config->afrl; |
|
| 161 |
gpiop->AFRH = config->afrh; |
|
| 162 |
gpiop->MODER = config->moder; |
|
| 163 |
gpiop->LOCKR = config->lockr; |
|
| 164 |
} |
|
| 165 |
|
|
| 166 |
static void stm32_gpio_init(void) {
|
|
| 167 |
|
|
| 168 |
/* Enabling GPIO-related clocks, the mask comes from the |
|
| 169 |
registry header file.*/ |
|
| 170 |
rccResetAHB2(STM32_GPIO_EN_MASK); |
|
| 171 |
rccEnableAHB2(STM32_GPIO_EN_MASK, true); |
|
| 172 |
|
|
| 173 |
/* Initializing all the defined GPIO ports.*/ |
|
| 174 |
#if STM32_HAS_GPIOA |
|
| 175 |
gpio_init(GPIOA, &gpio_default_config.PAData); |
|
| 176 |
#endif |
|
| 177 |
#if STM32_HAS_GPIOB |
|
| 178 |
gpio_init(GPIOB, &gpio_default_config.PBData); |
|
| 179 |
#endif |
|
| 180 |
#if STM32_HAS_GPIOC |
|
| 181 |
gpio_init(GPIOC, &gpio_default_config.PCData); |
|
| 182 |
#endif |
|
| 183 |
#if STM32_HAS_GPIOD |
|
| 184 |
gpio_init(GPIOD, &gpio_default_config.PDData); |
|
| 185 |
#endif |
|
| 186 |
#if STM32_HAS_GPIOE |
|
| 187 |
gpio_init(GPIOE, &gpio_default_config.PEData); |
|
| 188 |
#endif |
|
| 189 |
#if STM32_HAS_GPIOF |
|
| 190 |
gpio_init(GPIOF, &gpio_default_config.PFData); |
|
| 191 |
#endif |
|
| 192 |
#if STM32_HAS_GPIOG |
|
| 193 |
gpio_init(GPIOG, &gpio_default_config.PGData); |
|
| 194 |
#endif |
|
| 195 |
#if STM32_HAS_GPIOH |
|
| 196 |
gpio_init(GPIOH, &gpio_default_config.PHData); |
|
| 197 |
#endif |
|
| 198 |
#if STM32_HAS_GPIOI |
|
| 199 |
gpio_init(GPIOI, &gpio_default_config.PIData); |
|
| 200 |
#endif |
|
| 201 |
#if STM32_HAS_GPIOJ |
|
| 202 |
gpio_init(GPIOJ, &gpio_default_config.PJData); |
|
| 203 |
#endif |
|
| 204 |
#if STM32_HAS_GPIOK |
|
| 205 |
gpio_init(GPIOK, &gpio_default_config.PKData); |
|
| 206 |
#endif |
|
| 207 |
} |
|
| 208 |
|
|
| 209 |
/*===========================================================================*/ |
|
| 210 |
/* Driver interrupt handlers. */ |
|
| 211 |
/*===========================================================================*/ |
|
| 212 |
|
|
| 213 |
/*===========================================================================*/ |
|
| 214 |
/* Driver exported functions. */ |
|
| 215 |
/*===========================================================================*/ |
|
| 216 |
|
|
| 217 |
/** |
|
| 218 |
* @brief Early initialization code. |
|
| 219 |
* @details GPIO ports and system clocks are initialized before everything |
|
| 220 |
* else. |
|
| 221 |
*/ |
|
| 222 |
void __early_init(void) {
|
|
| 223 |
|
|
| 224 |
stm32_gpio_init(); |
|
| 225 |
stm32_clock_init(); |
|
| 226 |
} |
|
| 227 |
|
|
| 228 |
#if HAL_USE_SDC || defined(__DOXYGEN__) |
|
| 229 |
/** |
|
| 230 |
* @brief SDC card detection. |
|
| 231 |
*/ |
|
| 232 |
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
|
| 233 |
|
|
| 234 |
(void)sdcp; |
|
| 235 |
/* TODO: Fill the implementation.*/ |
|
| 236 |
return true; |
|
| 237 |
} |
|
| 238 |
|
|
| 239 |
/** |
|
| 240 |
* @brief SDC card write protection detection. |
|
| 241 |
*/ |
|
| 242 |
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
|
| 243 |
|
|
| 244 |
(void)sdcp; |
|
| 245 |
/* TODO: Fill the implementation.*/ |
|
| 246 |
return false; |
|
| 247 |
} |
|
| 248 |
#endif /* HAL_USE_SDC */ |
|
| 249 |
|
|
| 250 |
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) |
|
| 251 |
/** |
|
| 252 |
* @brief MMC_SPI card detection. |
|
| 253 |
*/ |
|
| 254 |
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
|
| 255 |
|
|
| 256 |
(void)mmcp; |
|
| 257 |
/* TODO: Fill the implementation.*/ |
|
| 258 |
return true; |
|
| 259 |
} |
|
| 260 |
|
|
| 261 |
/** |
|
| 262 |
* @brief MMC_SPI card write protection detection. |
|
| 263 |
*/ |
|
| 264 |
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
|
| 265 |
|
|
| 266 |
(void)mmcp; |
|
| 267 |
/* TODO: Fill the implementation.*/ |
|
| 268 |
return false; |
|
| 269 |
} |
|
| 270 |
#endif |
|
| 271 |
|
|
| 272 |
/** |
|
| 273 |
* @brief Board-specific initialization code. |
|
| 274 |
* @todo Add your board-specific code, if any. |
|
| 275 |
*/ |
|
| 276 |
void boardInit(void) {
|
|
| 277 |
|
|
| 278 |
} |
|
| modules/BI-Vital_5-1/board.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2020 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
#ifndef BOARD_H |
|
| 20 |
#define BOARD_H |
|
| 21 |
|
|
| 22 |
/*===========================================================================*/ |
|
| 23 |
/* Driver constants. */ |
|
| 24 |
/*===========================================================================*/ |
|
| 25 |
|
|
| 26 |
/* |
|
| 27 |
* Setup for BI-Vital (BGv5.1) board. |
|
| 28 |
*/ |
|
| 29 |
|
|
| 30 |
/* |
|
| 31 |
* Board identifier. |
|
| 32 |
*/ |
|
| 33 |
#define BOARD_BIVITAL_BG51 |
|
| 34 |
#define BOARD_NAME "BI-Vital (BGv5.1)" |
|
| 35 |
|
|
| 36 |
/* |
|
| 37 |
* Board oscillators-related settings. |
|
| 38 |
*/ |
|
| 39 |
#if !defined(STM32_LSECLK) |
|
| 40 |
#define STM32_LSECLK 32768U |
|
| 41 |
#endif |
|
| 42 |
|
|
| 43 |
#define STM32_LSEDRV (3U << 3U) |
|
| 44 |
|
|
| 45 |
#if !defined(STM32_HSECLK) |
|
| 46 |
#define STM32_HSECLK 16000000U |
|
| 47 |
#endif |
|
| 48 |
|
|
| 49 |
#define STM32_HSE_BYPASS |
|
| 50 |
|
|
| 51 |
/* |
|
| 52 |
* Board voltages. |
|
| 53 |
* Required for performance limits calculation. |
|
| 54 |
*/ |
|
| 55 |
#define STM32_VDD 180U |
|
| 56 |
|
|
| 57 |
/* |
|
| 58 |
* MCU type as defined in the ST header. |
|
| 59 |
*/ |
|
| 60 |
#define STM32L476xx |
|
| 61 |
|
|
| 62 |
/* |
|
| 63 |
* IO pins assignments. |
|
| 64 |
*/ |
|
| 65 |
#define GPIOA_RESP_IN 0U |
|
| 66 |
#define GPIOA_ECG_IN 1U |
|
| 67 |
#define GPIOA_PIN2 2U |
|
| 68 |
#define GPIOA_PIN3 3U |
|
| 69 |
#define GPIOA_RESP_REF 4U |
|
| 70 |
#define GPIOA_ECG_REF 5U |
|
| 71 |
#define GPIOA_QSPI_IO3 6U |
|
| 72 |
#define GPIOA_QSPI_IO2 7U |
|
| 73 |
#define GPIOA_PIN8 8U |
|
| 74 |
#define GPIOA_VCC_USB 9U |
|
| 75 |
#define GPIOA_PWR_USB_ID 10U |
|
| 76 |
#define GPIOA_PWR_USB_DM 11U |
|
| 77 |
#define GPIOA_PWR_USB_DP 12U |
|
| 78 |
#define GPIOA_SWDIO 13U |
|
| 79 |
#define GPIOA_SWCLK 14U |
|
| 80 |
#define GPIOA_UART_RTS 15U |
|
| 81 |
|
|
| 82 |
#define GPIOB_QSPI_IO1 0U |
|
| 83 |
#define GPIOB_QSPI_IO0 1U |
|
| 84 |
#define GPIOB_MIC_EN 2U |
|
| 85 |
#define GPIOB_SWO 3U |
|
| 86 |
#define GPIOB_RESET 4U |
|
| 87 |
#define GPIOB_PIN5 5U |
|
| 88 |
#define GPIOB_PIN6 6U |
|
| 89 |
#define GPIOB_UART_CTS 7U |
|
| 90 |
#define GPIOB_MIC_IN 8U |
|
| 91 |
#define GPIOB_PIN9 9U |
|
| 92 |
#define GPIOB_QSPI_CLK 10U |
|
| 93 |
#define GPIOB_QSPI_NCS 11U |
|
| 94 |
#define GPIOB_PWR_CD 12U |
|
| 95 |
#define GPIOB_SCL 13U |
|
| 96 |
#define GPIOB_SDA 14U |
|
| 97 |
#define GPIOB_PIN15 15U |
|
| 98 |
|
|
| 99 |
#define GPIOC_PIN0 0U |
|
| 100 |
#define GPIOC_PIN1 1U |
|
| 101 |
#define GPIOC_MIC_CLK 2U |
|
| 102 |
#define GPIOC_PIN3 3U |
|
| 103 |
#define GPIOC_QSPI_EN 4U |
|
| 104 |
#define GPIOC_MCU_WKUP 5U |
|
| 105 |
#define GPIOC_PIN6 6U |
|
| 106 |
#define GPIOC_BUZZ_OUT 7U |
|
| 107 |
#define GPIOC_PC8 8U |
|
| 108 |
#define GPIOC_VIB_OUT 9U |
|
| 109 |
#define GPIOC_UART_TX 10U |
|
| 110 |
#define GPIOC_UART_RX 11U |
|
| 111 |
#define GPIOC_PIN12 12U |
|
| 112 |
#define GPIOC_PIN13 13U |
|
| 113 |
#define GPIOC_OSC32_IN 14U |
|
| 114 |
#define GPIOC_OSC32_OUT 15U |
|
| 115 |
|
|
| 116 |
#define GPIOD_PIN0 0U |
|
| 117 |
#define GPIOD_PIN1 1U |
|
| 118 |
#define GPIOD_BUTTON 2U |
|
| 119 |
#define GPIOD_PIN3 3U |
|
| 120 |
#define GPIOD_PIN4 4U |
|
| 121 |
#define GPIOD_PIN5 5U |
|
| 122 |
#define GPIOD_PIN6 6U |
|
| 123 |
#define GPIOD_PIN7 7U |
|
| 124 |
#define GPIOD_PIN8 8U |
|
| 125 |
#define GPIOD_PIN9 9U |
|
| 126 |
#define GPIOD_PIN10 10U |
|
| 127 |
#define GPIOD_PIN11 11U |
|
| 128 |
#define GPIOD_PIN12 12U |
|
| 129 |
#define GPIOD_PIN13 13U |
|
| 130 |
#define GPIOD_PIN14 14U |
|
| 131 |
#define GPIOD_PIN15 15U |
|
| 132 |
|
|
| 133 |
#define GPIOE_PIN0 0U |
|
| 134 |
#define GPIOE_PIN1 1U |
|
| 135 |
#define GPIOE_PIN2 2U |
|
| 136 |
#define GPIOE_PIN3 3U |
|
| 137 |
#define GPIOE_PIN4 4U |
|
| 138 |
#define GPIOE_PIN5 5U |
|
| 139 |
#define GPIOE_PIN6 6U |
|
| 140 |
#define GPIOE_PIN7 7U |
|
| 141 |
#define GPIOE_PIN8 8U |
|
| 142 |
#define GPIOE_PIN9 9U |
|
| 143 |
#define GPIOE_PIN10 10U |
|
| 144 |
#define GPIOE_PIN11 11U |
|
| 145 |
#define GPIOE_PIN12 12U |
|
| 146 |
#define GPIOE_PIN13 13U |
|
| 147 |
#define GPIOE_PIN14 14U |
|
| 148 |
#define GPIOE_PIN15 15U |
|
| 149 |
|
|
| 150 |
#define GPIOF_PIN0 0U |
|
| 151 |
#define GPIOF_PIN1 1U |
|
| 152 |
#define GPIOF_PIN2 2U |
|
| 153 |
#define GPIOF_PIN3 3U |
|
| 154 |
#define GPIOF_PIN4 4U |
|
| 155 |
#define GPIOF_PIN5 5U |
|
| 156 |
#define GPIOF_PIN6 6U |
|
| 157 |
#define GPIOF_PIN7 7U |
|
| 158 |
#define GPIOF_PIN8 8U |
|
| 159 |
#define GPIOF_PIN9 9U |
|
| 160 |
#define GPIOF_PIN10 10U |
|
| 161 |
#define GPIOF_PIN11 11U |
|
| 162 |
#define GPIOF_PIN12 12U |
|
| 163 |
#define GPIOF_PIN13 13U |
|
| 164 |
#define GPIOF_PIN14 14U |
|
| 165 |
#define GPIOF_PIN15 15U |
|
| 166 |
|
|
| 167 |
#define GPIOG_PIN0 0U |
|
| 168 |
#define GPIOG_PIN1 1U |
|
| 169 |
#define GPIOG_PIN2 2U |
|
| 170 |
#define GPIOG_PIN3 3U |
|
| 171 |
#define GPIOG_PIN4 4U |
|
| 172 |
#define GPIOG_PIN5 5U |
|
| 173 |
#define GPIOG_PIN6 6U |
|
| 174 |
#define GPIOG_PIN7 7U |
|
| 175 |
#define GPIOG_PIN8 8U |
|
| 176 |
#define GPIOG_LED_R 9U |
|
| 177 |
#define GPIOG_LED_G 10U |
|
| 178 |
#define GPIOG_PIN11 11U |
|
| 179 |
#define GPIOG_PIN12 12U |
|
| 180 |
#define GPIOG_PIN13 13U |
|
| 181 |
#define GPIOG_LED_B 14U |
|
| 182 |
#define GPIOG_PIN15 15U |
|
| 183 |
|
|
| 184 |
#define GPIOH_OSC_IN 0U |
|
| 185 |
#define GPIOH_OSC_OUT 1U |
|
| 186 |
#define GPIOH_PIN2 2U |
|
| 187 |
#define GPIOH_PIN3 3U |
|
| 188 |
#define GPIOH_PIN4 4U |
|
| 189 |
#define GPIOH_PIN5 5U |
|
| 190 |
#define GPIOH_PIN6 6U |
|
| 191 |
#define GPIOH_PIN7 7U |
|
| 192 |
#define GPIOH_PIN8 8U |
|
| 193 |
#define GPIOH_PIN9 9U |
|
| 194 |
#define GPIOH_PIN10 10U |
|
| 195 |
#define GPIOH_PIN11 11U |
|
| 196 |
#define GPIOH_PIN12 12U |
|
| 197 |
#define GPIOH_PIN13 13U |
|
| 198 |
#define GPIOH_PIN14 14U |
|
| 199 |
#define GPIOH_PIN15 15U |
|
| 200 |
|
|
| 201 |
/* |
|
| 202 |
* IO lines assignments. |
|
| 203 |
*/ |
|
| 204 |
#define LINE_RESP_IN PAL_LINE(GPIOA, GPIOA_RESP_IN) |
|
| 205 |
#define LINE_ECG_IN PAL_LINE(GPIOA, GPIOA_ECG_IN) |
|
| 206 |
#define LINE_RESP_REF PAL_LINE(GPIOA, GPIOA_RESP_REF) |
|
| 207 |
#define LINE_ECG_REF PAL_LINE(GPIOA, GPIOA_ECG_REF) |
|
| 208 |
#define LINE_QSPI_IO3 PAL_LINE(GPIOA, GPIOA_QSPI_IO3) |
|
| 209 |
#define LINE_QSPI_IO2 PAL_LINE(GPIOA, GPIOA_QSPI_IO2) |
|
| 210 |
#define LINE_VCC_USB PAL_LINE(GPIOA, GPIOA_VCC_USB) |
|
| 211 |
#define LINE_PWR_USB_ID PAL_LINE(GPIOA, GPIOA_PWR_USB_ID) |
|
| 212 |
#define LINE_PWR_USB_DM PAL_LINE(GPIOA, GPIOA_PWR_USB_DM) |
|
| 213 |
#define LINE_PWR_USB_DP PAL_LINE(GPIOA, GPIOA_PWR_USB_DP) |
|
| 214 |
#define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO) |
|
| 215 |
#define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK) |
|
| 216 |
#define LINE_UART_RTS PAL_LINE(GPIOA, GPIOA_UART_RTS) |
|
| 217 |
|
|
| 218 |
#define LINE_QSPI_IO1 PAL_LINE(GPIOB, GPIOB_QSPI_IO1) |
|
| 219 |
#define LINE_QSPI_IO0 PAL_LINE(GPIOB, GPIOB_QSPI_IO0) |
|
| 220 |
#define LINE_MIC_EN PAL_LINE(GPIOB, GPIOB_MIC_EN) |
|
| 221 |
#define LINE_SWO PAL_LINE(GPIOB, GPIOB_SWO) |
|
| 222 |
#define LINE_RESET PAL_LINE(GPIOB, GPIOB_RESET) |
|
| 223 |
#define LINE_UART_CTS PAL_LINE(GPIOB, GPIOB_UART_CTS) |
|
| 224 |
#define LINE_MIC_IN PAL_LINE(GPIOB, GPIOB_MIC_IN) |
|
| 225 |
#define LINE_QSPI_CLK PAL_LINE(GPIOB, GPIOB_QSPI_CLK) |
|
| 226 |
#define LINE_QSPI_NCS PAL_LINE(GPIOB, GPIOB_QSPI_NCS) |
|
| 227 |
#define LINE_PWR_CD PAL_LINE(GPIOB, GPIOB_PWR_CD) |
|
| 228 |
#define LINE_SCL PAL_LINE(GPIOB, GPIOB_SCL) |
|
| 229 |
#define LINE_SDA PAL_LINE(GPIOB, GPIOB_SDA) |
|
| 230 |
|
|
| 231 |
#define LINE_MIC_CLK PAL_LINE(GPIOC, GPIOC_MIC_CLK) |
|
| 232 |
#define LINE_QSPI_EN PAL_LINE(GPIOC, GPIOC_QSPI_EN) |
|
| 233 |
#define LINE_MCU_WKUP PAL_LINE(GPIOC, GPIOC_MCU_WKUP) |
|
| 234 |
#define LINE_BUZZ_OUT PAL_LINE(GPIOC, GPIOC_BUZZ_OUT) |
|
| 235 |
#define LINE_VIB_OUT PAL_LINE(GPIOC, GPIOC_VIB_OUT) |
|
| 236 |
#define LINE_UART_TX PAL_LINE(GPIOC, GPIOC_UART_TX) |
|
| 237 |
#define LINE_UART_RX PAL_LINE(GPIOC, GPIOC_UART_RX) |
|
| 238 |
#define LINE_OSC32_IN PAL_LINE(GPIOC, GPIOC_OSC32_IN) |
|
| 239 |
#define LINE_OSC32_OUT PAL_LINE(GPIOC, GPIOC_OSC32_OUT) |
|
| 240 |
|
|
| 241 |
#define LINE_BUTTON PAL_LINE(GPIOD, GPIOD_BUTTON) |
|
| 242 |
|
|
| 243 |
#define LINE_LED_R PAL_LINE(GPIOG, GPIOG_LED_R) |
|
| 244 |
#define LINE_LED_G PAL_LINE(GPIOG, GPIOG_LED_G) |
|
| 245 |
#define LINE_LED_B PAL_LINE(GPIOG, GPIOG_LED_B) |
|
| 246 |
|
|
| 247 |
#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_OSC_IN) |
|
| 248 |
#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_OSC_OUT) |
|
| 249 |
|
|
| 250 |
/*===========================================================================*/ |
|
| 251 |
/* Driver pre-compile time settings. */ |
|
| 252 |
/*===========================================================================*/ |
|
| 253 |
|
|
| 254 |
/*===========================================================================*/ |
|
| 255 |
/* Derived constants and error checks. */ |
|
| 256 |
/*===========================================================================*/ |
|
| 257 |
|
|
| 258 |
/*===========================================================================*/ |
|
| 259 |
/* Driver data structures and types. */ |
|
| 260 |
/*===========================================================================*/ |
|
| 261 |
|
|
| 262 |
/*===========================================================================*/ |
|
| 263 |
/* Driver macros. */ |
|
| 264 |
/*===========================================================================*/ |
|
| 265 |
|
|
| 266 |
/* |
|
| 267 |
* I/O ports initial setup, this configuration is established soon after reset |
|
| 268 |
* in the initialization code. |
|
| 269 |
* Please refer to the STM32 Reference Manual for details. |
|
| 270 |
*/ |
|
| 271 |
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
|
| 272 |
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
|
| 273 |
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
|
| 274 |
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) |
|
| 275 |
#define PIN_ODR_LOW(n) (0U << (n)) |
|
| 276 |
#define PIN_ODR_HIGH(n) (1U << (n)) |
|
| 277 |
#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
|
| 278 |
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
|
| 279 |
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) |
|
| 280 |
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) |
|
| 281 |
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) |
|
| 282 |
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) |
|
| 283 |
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) |
|
| 284 |
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) |
|
| 285 |
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) |
|
| 286 |
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) |
|
| 287 |
#define PIN_ASCR_DISABLED(n) (0U << (n)) |
|
| 288 |
#define PIN_ASCR_ENABLED(n) (1U << (n)) |
|
| 289 |
#define PIN_LOCKR_DISABLED(n) (0U << (n)) |
|
| 290 |
#define PIN_LOCKR_ENABLED(n) (1U << (n)) |
|
| 291 |
|
|
| 292 |
/* |
|
| 293 |
* GPIOA setup: |
|
| 294 |
* |
|
| 295 |
* PA0 - RESP_IN (analog). |
|
| 296 |
* PA1 - ECG_IN (analog). |
|
| 297 |
* PA2 - PIN2 (analog). |
|
| 298 |
* PA3 - PIN3 (analog). |
|
| 299 |
* PA4 - RESP_REF (analog). |
|
| 300 |
* PA5 - ECG_REF (analog). |
|
| 301 |
* PA6 - QSPI_IO3 (analog). |
|
| 302 |
* PA7 - QSPI_IO2 (analog). |
|
| 303 |
* PA8 - PIN8 (analog). |
|
| 304 |
* PA9 - VCC_USB (analog). |
|
| 305 |
* PA10 - PWR_USB_ID (analog). |
|
| 306 |
* PA11 - PWR_USB_DM (analog). |
|
| 307 |
* PA12 - PWR_USB_DP (analog). |
|
| 308 |
* PA13 - SWDIO (analog). |
|
| 309 |
* PA14 - SWCLK (analog). |
|
| 310 |
* PA15 - UART_RTS (analog). |
|
| 311 |
*/ |
|
| 312 |
#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_RESP_IN) | \ |
|
| 313 |
PIN_MODE_ANALOG(GPIOA_ECG_IN | \ |
|
| 314 |
PIN_MODE_ANALOG(GPIOA_PIN2) | \ |
|
| 315 |
PIN_MODE_ANALOG(GPIOA_PIN3) | \ |
|
| 316 |
PIN_MODE_ANALOG(GPIOA_RESP_REF) | \ |
|
| 317 |
PIN_MODE_ANALOG(GPIOA_ECG_REF) | \ |
|
| 318 |
PIN_MODE_ANALOG(GPIOA_QSPI_IO3) | \ |
|
| 319 |
PIN_MODE_ANALOG(GPIOA_QSPI_IO2) | \ |
|
| 320 |
PIN_MODE_ANALOG(GPIOA_PIN8) | \ |
|
| 321 |
PIN_MODE_ANALOG(GPIOA_VCC_USB) | \ |
|
| 322 |
PIN_MODE_ANALOG(GPIOA_PWR_USB_ID) | \ |
|
| 323 |
PIN_MODE_ANALOG(GPIOA_PWR_USB_DM) | \ |
|
| 324 |
PIN_MODE_ANALOG(GPIOA_PWR_USB_DP) | \ |
|
| 325 |
PIN_MODE_ANALOG(GPIOA_SWDIO) | \ |
|
| 326 |
PIN_MODE_ANALOG(GPIOA_SWCLK) | \ |
|
| 327 |
PIN_MODE_ANALOG(GPIOA_UART_RTS)) |
|
| 328 |
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_RESP_IN) | \ |
|
| 329 |
PIN_OTYPE_PUSHPULL(GPIOA_ECG_IN | \ |
|
| 330 |
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ |
|
| 331 |
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ |
|
| 332 |
PIN_OTYPE_PUSHPULL(GPIOA_RESP_REF) | \ |
|
| 333 |
PIN_OTYPE_PUSHPULL(GPIOA_ECG_REF) | \ |
|
| 334 |
PIN_OTYPE_PUSHPULL(GPIOA_QSPI_IO3) | \ |
|
| 335 |
PIN_OTYPE_PUSHPULL(GPIOA_QSPI_IO2) | \ |
|
| 336 |
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ |
|
| 337 |
PIN_OTYPE_PUSHPULL(GPIOA_VCC_USB) | \ |
|
| 338 |
PIN_OTYPE_PUSHPULL(GPIOA_PWR_USB_ID) | \ |
|
| 339 |
PIN_OTYPE_PUSHPULL(GPIOA_PWR_USB_DM) | \ |
|
| 340 |
PIN_OTYPE_PUSHPULL(GPIOA_PWR_USB_DP) | \ |
|
| 341 |
PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ |
|
| 342 |
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ |
|
| 343 |
PIN_OTYPE_PUSHPULL(GPIOA_UART_RTS)) |
|
| 344 |
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_RESP_IN) | \ |
|
| 345 |
PIN_OSPEED_HIGH(GPIOA_ECG_IN | \ |
|
| 346 |
PIN_OSPEED_HIGH(GPIOA_PIN2) | \ |
|
| 347 |
PIN_OSPEED_HIGH(GPIOA_PIN3) | \ |
|
| 348 |
PIN_OSPEED_HIGH(GPIOA_RESP_REF) | \ |
|
| 349 |
PIN_OSPEED_HIGH(GPIOA_ECG_REF) | \ |
|
| 350 |
PIN_OSPEED_HIGH(GPIOA_QSPI_IO3) | \ |
|
| 351 |
PIN_OSPEED_HIGH(GPIOA_QSPI_IO2) | \ |
|
| 352 |
PIN_OSPEED_HIGH(GPIOA_PIN8) | \ |
|
| 353 |
PIN_OSPEED_HIGH(GPIOA_VCC_USB) | \ |
|
| 354 |
PIN_OSPEED_HIGH(GPIOA_PWR_USB_ID) | \ |
|
| 355 |
PIN_OSPEED_HIGH(GPIOA_PWR_USB_DM) | \ |
|
| 356 |
PIN_OSPEED_HIGH(GPIOA_PWR_USB_DP) | \ |
|
| 357 |
PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ |
|
| 358 |
PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ |
|
| 359 |
PIN_OSPEED_HIGH(GPIOA_UART_RTS)) |
|
| 360 |
#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_RESP_IN) | \ |
|
| 361 |
PIN_PUPDR_FLOATING(GPIOA_ECG_IN | \ |
|
| 362 |
PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ |
|
| 363 |
PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ |
|
| 364 |
PIN_PUPDR_FLOATING(GPIOA_RESP_REF) | \ |
|
| 365 |
PIN_PUPDR_FLOATING(GPIOA_ECG_REF) | \ |
|
| 366 |
PIN_PUPDR_FLOATING(GPIOA_QSPI_IO3) | \ |
|
| 367 |
PIN_PUPDR_FLOATING(GPIOA_QSPI_IO2) | \ |
|
| 368 |
PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ |
|
| 369 |
PIN_PUPDR_FLOATING(GPIOA_VCC_USB) | \ |
|
| 370 |
PIN_PUPDR_FLOATING(GPIOA_PWR_USB_ID) | \ |
|
| 371 |
PIN_PUPDR_FLOATING(GPIOA_PWR_USB_DM) | \ |
|
| 372 |
PIN_PUPDR_FLOATING(GPIOA_PWR_USB_DP) | \ |
|
| 373 |
PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ |
|
| 374 |
PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ |
|
| 375 |
PIN_PUPDR_FLOATING(GPIOA_UART_RTS)) |
|
| 376 |
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_RESP_IN) | \ |
|
| 377 |
PIN_ODR_HIGH(GPIOA_ECG_IN | \ |
|
| 378 |
PIN_ODR_HIGH(GPIOA_PIN2) | \ |
|
| 379 |
PIN_ODR_HIGH(GPIOA_PIN3) | \ |
|
| 380 |
PIN_ODR_HIGH(GPIOA_RESP_REF) | \ |
|
| 381 |
PIN_ODR_HIGH(GPIOA_ECG_REF) | \ |
|
| 382 |
PIN_ODR_HIGH(GPIOA_QSPI_IO3) | \ |
|
| 383 |
PIN_ODR_HIGH(GPIOA_QSPI_IO2) | \ |
|
| 384 |
PIN_ODR_HIGH(GPIOA_PIN8) | \ |
|
| 385 |
PIN_ODR_HIGH(GPIOA_VCC_USB) | \ |
|
| 386 |
PIN_ODR_HIGH(GPIOA_PWR_USB_ID) | \ |
|
| 387 |
PIN_ODR_HIGH(GPIOA_PWR_USB_DM) | \ |
|
| 388 |
PIN_ODR_HIGH(GPIOA_PWR_USB_DP) | \ |
|
| 389 |
PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
|
| 390 |
PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
|
| 391 |
PIN_ODR_HIGH(GPIOA_UART_RTS)) |
|
| 392 |
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_RESP_IN, 0U) | \ |
|
| 393 |
PIN_AFIO_AF(GPIOA_ECG_IN 0U) | \ |
|
| 394 |
PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ |
|
| 395 |
PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ |
|
| 396 |
PIN_AFIO_AF(GPIOA_RESP_REF, 0U) | \ |
|
| 397 |
PIN_AFIO_AF(GPIOA_ECG_REF, 0U) | \ |
|
| 398 |
PIN_AFIO_AF(GPIOA_QSPI_IO3, 0U) | \ |
|
| 399 |
PIN_AFIO_AF(GPIOA_QSPI_IO2, 0U)) |
|
| 400 |
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ |
|
| 401 |
PIN_AFIO_AF(GPIOA_VCC_USB, 0U) | \ |
|
| 402 |
PIN_AFIO_AF(GPIOA_PWR_USB_ID, 0U) | \ |
|
| 403 |
PIN_AFIO_AF(GPIOA_PWR_USB_DM, 0U) | \ |
|
| 404 |
PIN_AFIO_AF(GPIOA_PWR_USB_DP, 0U) | \ |
|
| 405 |
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ |
|
| 406 |
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ |
|
| 407 |
PIN_AFIO_AF(GPIOA_UART_RTS, 0U)) |
|
| 408 |
#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_RESP_IN) | \ |
|
| 409 |
PIN_ASCR_DISABLED(GPIOA_ECG_IN | \ |
|
| 410 |
PIN_ASCR_DISABLED(GPIOA_PIN2) | \ |
|
| 411 |
PIN_ASCR_DISABLED(GPIOA_PIN3) | \ |
|
| 412 |
PIN_ASCR_DISABLED(GPIOA_RESP_REF) | \ |
|
| 413 |
PIN_ASCR_DISABLED(GPIOA_ECG_REF) | \ |
|
| 414 |
PIN_ASCR_DISABLED(GPIOA_QSPI_IO3) | \ |
|
| 415 |
PIN_ASCR_DISABLED(GPIOA_QSPI_IO2) | \ |
|
| 416 |
PIN_ASCR_DISABLED(GPIOA_PIN8) | \ |
|
| 417 |
PIN_ASCR_DISABLED(GPIOA_VCC_USB) | \ |
|
| 418 |
PIN_ASCR_DISABLED(GPIOA_PWR_USB_ID) | \ |
|
| 419 |
PIN_ASCR_DISABLED(GPIOA_PWR_USB_DM) | \ |
|
| 420 |
PIN_ASCR_DISABLED(GPIOA_PWR_USB_DP) | \ |
|
| 421 |
PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ |
|
| 422 |
PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ |
|
| 423 |
PIN_ASCR_DISABLED(GPIOA_UART_RTS)) |
|
| 424 |
#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_RESP_IN) | \ |
|
| 425 |
PIN_LOCKR_DISABLED(GPIOA_ECG_IN | \ |
|
| 426 |
PIN_LOCKR_DISABLED(GPIOA_PIN2) | \ |
|
| 427 |
PIN_LOCKR_DISABLED(GPIOA_PIN3) | \ |
|
| 428 |
PIN_LOCKR_DISABLED(GPIOA_RESP_REF) | \ |
|
| 429 |
PIN_LOCKR_DISABLED(GPIOA_ECG_REF) | \ |
|
| 430 |
PIN_LOCKR_DISABLED(GPIOA_QSPI_IO3) | \ |
|
| 431 |
PIN_LOCKR_DISABLED(GPIOA_QSPI_IO2) | \ |
|
| 432 |
PIN_LOCKR_DISABLED(GPIOA_PIN8) | \ |
|
| 433 |
PIN_LOCKR_DISABLED(GPIOA_VCC_USB) | \ |
|
| 434 |
PIN_LOCKR_DISABLED(GPIOA_PWR_USB_ID) | \ |
|
| 435 |
PIN_LOCKR_DISABLED(GPIOA_PWR_USB_DM) | \ |
|
| 436 |
PIN_LOCKR_DISABLED(GPIOA_PWR_USB_DP) | \ |
|
| 437 |
PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ |
|
| 438 |
PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ |
|
| 439 |
PIN_LOCKR_DISABLED(GPIOA_UART_RTS)) |
|
| 440 |
|
|
| 441 |
/* |
|
| 442 |
* GPIOB setup: |
|
| 443 |
* |
|
| 444 |
* PB0 - QSPI_IO1 (analog). |
|
| 445 |
* PB1 - QSPI_IO0 (analog). |
|
| 446 |
* PB2 - MIC_EN (analog). |
|
| 447 |
* PB3 - SWO (analog). |
|
| 448 |
* PB4 - RESET (analog). |
|
| 449 |
* PB5 - PIN5 (analog). |
|
| 450 |
* PB6 - PIN6 (analog). |
|
| 451 |
* PB7 - UART_CTS (analog). |
|
| 452 |
* PB8 - MIC_IN (analog). |
|
| 453 |
* PB9 - PIN9 (analog). |
|
| 454 |
* PB10 - QSPI_CLK (analog). |
|
| 455 |
* PB11 - QSP_NCS (analog). |
|
| 456 |
* PB12 - PWR_CD (analog). |
|
| 457 |
* PB13 - SCL (analog). |
|
| 458 |
* PB14 - SDA (analog). |
|
| 459 |
* PB15 - PIN15 (analog). |
|
| 460 |
*/ |
|
| 461 |
#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_QSPI_IO1) | \ |
|
| 462 |
PIN_MODE_ANALOG(GPIOB_QSPI_IO0) | \ |
|
| 463 |
PIN_MODE_ANALOG(GPIOB_MIC_EN) | \ |
|
| 464 |
PIN_MODE_ANALOG(GPIOB_SWO) | \ |
|
| 465 |
PIN_MODE_ANALOG(GPIOB_RESET) | \ |
|
| 466 |
PIN_MODE_ANALOG(GPIOB_PIN5) | \ |
|
| 467 |
PIN_MODE_ANALOG(GPIOB_PIN6) | \ |
|
| 468 |
PIN_MODE_ANALOG(GPIOB_UART_CTS) | \ |
|
| 469 |
PIN_MODE_ANALOG(GPIOB_MIC_IN) | \ |
|
| 470 |
PIN_MODE_ANALOG(GPIOB_PIN9) | \ |
|
| 471 |
PIN_MODE_ANALOG(GPIOB_QSPI_CLK) | \ |
|
| 472 |
PIN_MODE_ANALOG(GPIOB_QSPI_NCS) | \ |
|
| 473 |
PIN_MODE_ANALOG(GPIOB_PWR_CD) | \ |
|
| 474 |
PIN_MODE_ANALOG(GPIOB_SCL) | \ |
|
| 475 |
PIN_MODE_ANALOG(GPIOB_SDA) | \ |
|
| 476 |
PIN_MODE_ANALOG(GPIOB_PIN15)) |
|
| 477 |
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_QSPI_IO1) | \ |
|
| 478 |
PIN_OTYPE_PUSHPULL(GPIOB_QSPI_IO0) | \ |
|
| 479 |
PIN_OTYPE_PUSHPULL(GPIOB_MIC_EN) | \ |
|
| 480 |
PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ |
|
| 481 |
PIN_OTYPE_PUSHPULL(GPIOB_RESET) | \ |
|
| 482 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ |
|
| 483 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ |
|
| 484 |
PIN_OTYPE_PUSHPULL(GPIOB_UART_CTS) | \ |
|
| 485 |
PIN_OTYPE_PUSHPULL(GPIOB_MIC_IN) | \ |
|
| 486 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ |
|
| 487 |
PIN_OTYPE_PUSHPULL(GPIOB_QSPI_CLK) | \ |
|
| 488 |
PIN_OTYPE_PUSHPULL(GPIOB_QSPI_NCS) | \ |
|
| 489 |
PIN_OTYPE_PUSHPULL(GPIOB_PWR_CD) | \ |
|
| 490 |
PIN_OTYPE_PUSHPULL(GPIOB_SCL) | \ |
|
| 491 |
PIN_OTYPE_PUSHPULL(GPIOB_SDA) | \ |
|
| 492 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) |
|
| 493 |
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_QSPI_IO1) | \ |
|
| 494 |
PIN_OSPEED_HIGH(GPIOB_QSPI_IO0) | \ |
|
| 495 |
PIN_OSPEED_HIGH(GPIOB_MIC_EN) | \ |
|
| 496 |
PIN_OSPEED_HIGH(GPIOB_SWO) | \ |
|
| 497 |
PIN_OSPEED_HIGH(GPIOB_RESET) | \ |
|
| 498 |
PIN_OSPEED_HIGH(GPIOB_PIN5) | \ |
|
| 499 |
PIN_OSPEED_HIGH(GPIOB_PIN6) | \ |
|
| 500 |
PIN_OSPEED_HIGH(GPIOB_UART_CTS) | \ |
|
| 501 |
PIN_OSPEED_HIGH(GPIOB_MIC_IN) | \ |
|
| 502 |
PIN_OSPEED_HIGH(GPIOB_PIN9) | \ |
|
| 503 |
PIN_OSPEED_HIGH(GPIOB_QSPI_CLK) | \ |
|
| 504 |
PIN_OSPEED_HIGH(GPIOB_QSPI_NCS) | \ |
|
| 505 |
PIN_OSPEED_HIGH(GPIOB_PWR_CD) | \ |
|
| 506 |
PIN_OSPEED_HIGH(GPIOB_SCL) | \ |
|
| 507 |
PIN_OSPEED_HIGH(GPIOB_SDA) | \ |
|
| 508 |
PIN_OSPEED_HIGH(GPIOB_PIN15)) |
|
| 509 |
#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_QSPI_IO1) | \ |
|
| 510 |
PIN_PUPDR_FLOATING(GPIOB_QSPI_IO0) | \ |
|
| 511 |
PIN_PUPDR_FLOATING(GPIOB_MIC_EN) | \ |
|
| 512 |
PIN_PUPDR_FLOATING(GPIOB_SWO) | \ |
|
| 513 |
PIN_PUPDR_FLOATING(GPIOB_RESET) | \ |
|
| 514 |
PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ |
|
| 515 |
PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ |
|
| 516 |
PIN_PUPDR_FLOATING(GPIOB_UART_CTS) | \ |
|
| 517 |
PIN_PUPDR_FLOATING(GPIOB_MIC_IN) | \ |
|
| 518 |
PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ |
|
| 519 |
PIN_PUPDR_FLOATING(GPIOB_QSPI_CLK) | \ |
|
| 520 |
PIN_PUPDR_FLOATING(GPIOB_QSPI_NCS) | \ |
|
| 521 |
PIN_PUPDR_FLOATING(GPIOB_PWR_CD) | \ |
|
| 522 |
PIN_PUPDR_FLOATING(GPIOB_SCL) | \ |
|
| 523 |
PIN_PUPDR_FLOATING(GPIOB_SDA) | \ |
|
| 524 |
PIN_PUPDR_FLOATING(GPIOB_PIN15)) |
|
| 525 |
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_QSPI_IO1) | \ |
|
| 526 |
PIN_ODR_HIGH(GPIOB_QSPI_IO0) | \ |
|
| 527 |
PIN_ODR_HIGH(GPIOB_MIC_EN) | \ |
|
Also available in: Unified diff