amiro-os / kernel / patches / I2C-without-DMA.patch @ 10853947
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| 1 |
diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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--- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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+++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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@@ -34,6 +34,7 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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+#if STM32_I2C_I2C1_USE_DMA
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#define I2C1_RX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_CHN) |
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@@ -41,7 +42,9 @@
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#define I2C1_TX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_CHN) |
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+#endif
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+#if STM32_I2C_I2C2_USE_DMA
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#define I2C2_RX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_CHN) |
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@@ -49,7 +52,9 @@
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#define I2C2_TX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_CHN) |
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+#endif
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+#if STM32_I2C_I2C3_USE_DMA
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#define I2C3_RX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \
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STM32_I2C3_RX_DMA_CHN) |
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@@ -57,6 +62,7 @@
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#define I2C3_TX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_CHN) |
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+#endif
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|
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/*===========================================================================*/
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/* Driver constants. */
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@@ -75,6 +81,20 @@
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#define I2C_EV6_MASTER_REC_MODE_SELECTED \ |
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((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))
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+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_RXNE))
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+
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+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP \
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+ ((uint32_t)(I2C_SR1_RXNE))
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+
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+#define I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | \
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+ I2C_SR1_BTF | I2C_SR1_RXNE))
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+
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+#define I2C_EV8_MASTER_BYTE_TRANSMITTING \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)<< 16) | \
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+ I2C_SR1_TXE))
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+
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ |
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((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ |
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I2C_SR1_BTF | I2C_SR1_TXE)) |
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@@ -132,8 +152,24 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) { |
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dp->SR1 = 0;
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/* Stops the associated DMA streams.*/
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- dmaStreamDisable(i2cp->dmatx);
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- dmaStreamDisable(i2cp->dmarx);
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+#if STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA
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+ if (&I2CD1 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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+#if STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA
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+ if (&I2CD2 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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+#if STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA
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+ if (&I2CD3 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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} |
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/**
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@@ -238,14 +274,18 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) { |
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dp->CR1 = regCR1; |
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} |
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+#if (STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA) || \
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+ (STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA) || \
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+ (STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA) || \
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+ defined(__DOXYGEN__)
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/**
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- * @brief I2C shared ISR code.
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+ * @brief I2C shared ISR code for DMA access.
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* |
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* @param[in] i2cp pointer to the @p I2CDriver object |
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* |
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* @notapi
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*/ |
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-static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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+static void i2c_lld_serve_event_interrupt_dma(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->i2c; |
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uint32_t regSR2 = dp->SR2; |
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uint32_t event = dp->SR1; |
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@@ -303,7 +343,146 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { |
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dp->SR1 &= ~I2C_SR1_BERR; |
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} |
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} |
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+#endif /* any I2CDx uses DMA mode */
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+
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+#if (STM32_I2C_USE_I2C1 && !STM32_I2C_I2C1_USE_DMA) || \
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+ (STM32_I2C_USE_I2C2 && !STM32_I2C_I2C2_USE_DMA) || \
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+ (STM32_I2C_USE_I2C3 && !STM32_I2C_I2C3_USE_DMA) || \
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+ defined(__DOXYGEN__)
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+/**
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+ * @brief I2C shared ISR code for non-DMA access.
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+ *
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+ * @param[in] i2cp pointer to the @p I2CDriver object
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+ *
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+ * @notapi
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+ */
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+static void i2c_lld_serve_event_interrupt_isr(I2CDriver *i2cp) {
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+ I2C_TypeDef *dp = i2cp->i2c;
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+ uint32_t regSR2 = dp->SR2;
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+ uint32_t event = dp->SR1;
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+
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+ switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
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+ case I2C_EV5_MASTER_MODE_SELECT:
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+ dp->CR2 |= I2C_CR2_ITBUFEN;
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+ dp->DR = i2cp->addr;
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+ break;
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+ case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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+ (void)dp->SR2; // clear ADDR flag
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+ /* EV8_1 */
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+ dp->DR = *(i2cp->txbuf);
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+
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+ ++i2cp->txbuf;
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+ --i2cp->txbytes;
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+
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+ /* if N == 1, skip the I2C_EV8_MASTER_BYTE_TRANSMITTING event
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+ * but enter I2C_EV8_2_MASTER_BYTE_TRANSMITTED next */
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+ if (i2cp->txbytes == 0) {
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV6_MASTER_REC_MODE_SELECTED:
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+ switch (i2cp->rxbytes) {
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+ case 1:
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ (void)dp->SR2; // clear ADDR flag
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+ dp->CR1 |= I2C_CR1_STOP;
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+ break;
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+ case 2:
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+ (void)dp->SR2; // clear ADDR flag
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+ /* EV6_1 */
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+ dp->CR1 |= I2C_CR1_POS;
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ break;
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+ case 3: /* N == 3 is a very special case, since EV7 is completely skipped */
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+ (void)dp->SR2; // clear ADDR flag
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+ /* Disable the I2C_EV7_MASTER_REC_BYTE_RECEIVED event
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+ * but enter I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP next */
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ break;
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+ default: /* N > 2 */
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+ (void)dp->SR2; // clear ADDR flag
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+ break;
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+ }
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+ break;
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+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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+ if (i2cp->rxbytes > 3) {
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ --i2cp->rxbytes;
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+ }
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+ if (i2cp->rxbytes == 3) {
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+ /* Disable this event for DataN-2, but force into event
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+ * I2C_EV7_2_EV7_3_MASTER_REC_BYTE_RECEIVED_QUEUED by not reading dp->DR. */
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP:
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+ osalDbgAssert(i2cp->rxbytes == 1, "more than 1 byte to be received");
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+ *(i2cp->rxbuf) = dp->DR;
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+ --i2cp->rxbytes;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+ _i2c_wakeup_isr(i2cp);
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+ break;
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+ case I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED:
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+ if (i2cp->rxbytes == 3) {
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+ /* EV7_2 (N > 2) */
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ dp->CR1 |= I2C_CR1_STOP;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ i2cp->rxbytes -= 2;
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+ /* enable I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP event */
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+ dp->CR2 |= I2C_CR2_ITBUFEN;
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+ } else {
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+ /* EV7_3 (N == 2) */
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+ dp->CR1 |= I2C_CR1_STOP;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ *(i2cp->rxbuf) = dp->DR;
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+ i2cp->rxbytes -= 2;
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+
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+ dp->CR1 &= ~I2C_CR1_POS;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+
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+ _i2c_wakeup_isr(i2cp);
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+ }
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+ break;
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+ case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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+ dp->DR = *(i2cp->txbuf);
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+ ++i2cp->txbuf;
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+ --i2cp->txbytes;
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+
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+ /* if this was the last byte, ensure that this event is not entered again */
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+ if (i2cp->txbytes == 0) {
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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+ if (i2cp->rxbytes > 0) {
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+ /* start "read after write" operation (LSB of address = 1 => read) */
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+ i2cp->addr |= 0x01;
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+ dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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+ } else {
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+ dp->CR1 |= I2C_CR1_STOP;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+ _i2c_wakeup_isr(i2cp);
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+ }
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+ break;
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+ default:
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+ osalDbgAssert(i2cp->rxbytes != 1, "more than 1 byte to be received");
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+ break;
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+ }
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+}
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+#endif /* any I2CDx uses non-DMA mode */
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+
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+#if (STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA) || \
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+ (STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA) || \
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+ (STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA) || \
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+ defined(__DOXYGEN__)
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/**
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* @brief DMA RX end IRQ handler.
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* |
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@@ -357,6 +536,7 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { |
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of R/W transaction itself.*/ |
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dp->CR2 |= I2C_CR2_ITEVTEN; |
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} |
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+#endif /* any I2CDx uses DMA mode */
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|
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/**
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* @brief I2C error handler.
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@@ -369,8 +549,24 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { |
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static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { |
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|
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/* Clears interrupt flags just to be safe.*/
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- dmaStreamDisable(i2cp->dmatx);
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- dmaStreamDisable(i2cp->dmarx);
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+#if STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA
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+ if (&I2CD1 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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+#if STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA
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+ if (&I2CD2 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
|
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+#endif
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+#if STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA
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+ if (&I2CD3 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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|
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i2cp->errors = I2C_NO_ERROR; |
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|
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@@ -421,7 +617,11 @@ OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
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|
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OSAL_IRQ_PROLOGUE(); |
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|
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- i2c_lld_serve_event_interrupt(&I2CD1);
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+#if STM32_I2C_I2C1_USE_DMA
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+ i2c_lld_serve_event_interrupt_dma(&I2CD1);
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| 298 |
+#else
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+ i2c_lld_serve_event_interrupt_isr(&I2CD1);
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+#endif
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