Revision 21e5be0b

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modules/NUCLEO-F767ZI/Makefile
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################################################################################
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# AMiRo-OS is an operating system designed for the Autonomous Mini Robot       #
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# (AMiRo) platform.                                                            #
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# Copyright (C) 2016..2019  Thomas Schöpping et al.                            #
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#                                                                              #
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# This program is free software: you can redistribute it and/or modify         #
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# it under the terms of the GNU General Public License as published by         #
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# the Free Software Foundation, either version 3 of the License, or            #
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# (at your option) any later version.                                          #
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#                                                                              #
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# This program is distributed in the hope that it will be useful,              #
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# but WITHOUT ANY WARRANTY; without even the implied warranty of               #
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                #
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# GNU General Public License for more details.                                 #
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#                                                                              #
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# You should have received a copy of the GNU General Public License            #
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# along with this program.  If not, see <http://www.gnu.org/licenses/>.        #
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#                                                                              #
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# This research/work was supported by the Cluster of Excellence Cognitive      #
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# Interaction Technology 'CITEC' (EXC 277) at Bielefeld University, which is   #
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# funded by the German Research Foundation (DFG).                              #
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################################################################################
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################################################################################
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# Build global options                                                         #
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# NOTE: Can be overridden externally.                                          #
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#                                                                              #
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# Compiler options here.
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ifeq ($(USE_OPT),)
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  USE_OPT = -O2 -fstack-usage
34
endif
35

  
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# C specific options here (added to USE_OPT).
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ifeq ($(USE_COPT),)
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  USE_COPT = -std=c17
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endif
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# C++ specific options here (added to USE_OPT).
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ifeq ($(USE_CPPOPT),)
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  USE_CPPOPT = -fno-rtti -std=c++17
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endif
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# Enable this if you want the linker to remove unused code and data.
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ifeq ($(USE_LINK_GC),)
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  USE_LINK_GC = yes
49
endif
50

  
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# Linker extra options here.
52
ifeq ($(USE_LDOPT),)
53
  USE_LDOPT =
54
endif
55

  
56
# Enable this if you want link time optimizations (LTO).
57
ifeq ($(USE_LTO),)
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  USE_LTO = yes
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endif
60

  
61
# Enable this if you want to see the full log while compiling.
62
ifeq ($(USE_VERBOSE_COMPILE),)
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  USE_VERBOSE_COMPILE = no
64
endif
65

  
66
# If enabled, this option makes the build process faster by not compiling
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# modules not used in the current configuration.
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ifeq ($(USE_SMART_BUILD),)
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  USE_SMART_BUILD = no
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endif
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#                                                                              #
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# Build global options                                                         #
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################################################################################
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################################################################################
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# Architecture or project specific options                                     #
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#                                                                              #
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80
# Stack size to be allocated to the Cortex-M process stack. This stack is
81
# the stack used by the main() thread.
82
ifeq ($(USE_PROCESS_STACKSIZE),)
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  USE_PROCESS_STACKSIZE = 0x400
84
endif
85

  
86
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
87
# stack is used for processing interrupts and exceptions.
88
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
89
  USE_EXCEPTIONS_STACKSIZE = 0x400
90
endif
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92
# Enables the use of FPU.
93
# Possible selections are:
94
#   no     - no FPU is used (probably equals 'soft')
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#   soft   - does not use the FPU, thus all floating point operations are emulated
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#   softfp - uses the FPU, but uses the integer registers only
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#   hard   - uses the FPU and passes data via the FPU registers
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ifeq ($(USE_FPU),)
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  USE_FPU = softfp
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endif
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# FPU-related options.
103
ifeq ($(USE_FPU_OPT),)
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  USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16
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endif
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#                                                                              #
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# Architecture or project specific options                                     #
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################################################################################
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################################################################################
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# Project, target, sources and paths                                           #
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#                                                                              #
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# Absolute path to the project
116
PROJECT_PATH := $(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
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# Define project name here
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PROJECT := $(patsubst $(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST))))..)/%,%,$(PROJECT_PATH))
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# Target settings.
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MCU = cortex-m4
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124
# Imported source files and paths.
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include ../../kernel/kernel.mk
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CHIBIOS    := $(AMIROOS_KERNEL)
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CONFDIR    := .
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ifeq ($(BUILDDIR),)
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  BUILDDIR := $(PROJECT_PATH)/build
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endif
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DEPDIR     := $(dir $(BUILDDIR)).dep
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AMIROOS    := ../..
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# Licensing files.
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include $(CHIBIOS)/os/license/license.mk
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# Startup files.
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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include $(CHIBIOS)/os/hal/lib/streams/streams.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
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# Auto-build files in ./source recursively.
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include $(CHIBIOS)/tools/mk/autobuild.mk
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# Other files (optional).
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include $(CHIBIOS)/test/lib/test.mk
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include $(CHIBIOS)/test/rt/rt_test.mk
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include $(CHIBIOS)/test/oslib/oslib_test.mk
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# AMiRo-BLT files
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include ../../bootloader/bootloader.mk
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# AMiRo-LLD files
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include ../../periphery-lld/periphery-lld.mk
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# AMiRo-OS files
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include ../modules.mk
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include $(AMIROOS)/core/core.mk
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include $(AMIROOS)/unittests/unittests.mk
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# Define linker script file here
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LDSCRIPT= STM32F76xxI.ld
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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CSRC = $(ALLCSRC) \
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       $(CHIBIOS)/os/various/syscalls.c \
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       $(CHIBIOS)/os/various/evtimer.c \
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       $(TESTSRC) \
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       board.c \
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       $(PERIPHERYLLDCSRC) \
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       $(UNITTESTSCSRC) \
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       $(AMIROOSCORECSRC) \
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       $(MODULESCSRC) \
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       module.c \
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       $(APPSCSRC)
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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CPPSRC = $(ALLCPPSRC) \
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         $(CHIBIOS)/os/various/cpp_wrappers/syscalls_cpp.cpp \
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         $(AMIROOSCORECPPSRC) \
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         $(APPSCPPSRC)
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# List ASM source files here.
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ASMSRC = $(ALLASMSRC) \
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         $(APPSASMSRC)
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# List ASM with preprocessor source files here.
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ASMXSRC = $(ALLXASMSRC) \
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          $(APPSASMXSRC)
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# Inclusion directories.
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INCDIR = $(CONFDIR) \
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         $(ALLINC) \
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         $(TESTINC) \
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         $(CHIBIOS)/os/hal/lib/streams \
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         $(BOOTLOADERINC) \
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         $(PERIPHERYLLDINC) \
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         $(AMIROOS) \
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         $(UNITTESTSINC) \
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         $(AMIROOSCOREINC) \
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         $(MODULESINC) \
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         $(APPSINC)
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# Define C warning options here.
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CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
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# Define C++ warning options here.
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CPPWARN = -Wall -Wextra -Wundef
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#                                                                              #
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# Project, target, sources and paths                                           #
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################################################################################
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################################################################################
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# Start of user section                                                        #
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#                                                                              #
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# List all user C define here, like -D_DEBUG=1
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UDEFS +=
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# Define ASM defines here
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UADEFS +=
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# List all user directories here
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UINCDIR +=
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# List the user directory to look for the libraries here
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ULIBDIR +=
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# List all user libraries here
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ULIBS +=
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#                                                                              #
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# End of user section                                                          #
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################################################################################
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################################################################################
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# Common rules                                                                 #
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#                                                                              #
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RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
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include $(RULESPATH)/arm-none-eabi.mk
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include $(RULESPATH)/rules.mk
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#                                                                              #
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# Common rules                                                                 #
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################################################################################
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################################################################################
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# Custom rules                                                                 #
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#                                                                              #
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flash: $(BUILDDIR)/$(PROJECT).elf
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	openocd -f interface/stlink-v2-1.cfg -c "set WORKAREASIZE 0x2000" -f target/stm32f7x.cfg -c "program $(BUILDDIR)/$(PROJECT).elf verify reset exit"
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#                                                                              #
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# Custom rules                                                                 #
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################################################################################
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modules/NUCLEO-F767ZI/STM32F76xxI.ld
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/*
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    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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    Licensed under the Apache License, Version 2.0 (the "License");
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    you may not use this file except in compliance with the License.
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    You may obtain a copy of the License at
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        http://www.apache.org/licenses/LICENSE-2.0
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    Unless required by applicable law or agreed to in writing, software
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    distributed under the License is distributed on an "AS IS" BASIS,
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    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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    See the License for the specific language governing permissions and
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    limitations under the License.
15
*/
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/*
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 * STM32F76xxI generic setup.
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 * 
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 * RAM0 - Data, Heap.
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 * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
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 *
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 * Notes:
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 * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
25
 */
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MEMORY
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{
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    flash0  : org = 0x08000000, len = 2M        /* Flash as AXIM (writable) */
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    flash1  : org = 0x00200000, len = 2M        /* Flash as ITCM */
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    flash2  : org = 0x00000000, len = 0
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    flash3  : org = 0x00000000, len = 0
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    flash4  : org = 0x00000000, len = 0
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    flash5  : org = 0x00000000, len = 0
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    flash6  : org = 0x00000000, len = 0
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    flash7  : org = 0x00000000, len = 0
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    ram0    : org = 0x20020000, len = 384k      /* SRAM1 + SRAM2 */
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    ram1    : org = 0x20020000, len = 368k      /* SRAM1 */
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    ram2    : org = 0x2007C000, len = 16k       /* SRAM2 */
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    ram3    : org = 0x20000000, len = 128k      /* DTCM-RAM */
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    ram4    : org = 0x00000000, len = 16k       /* ITCM-RAM */
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    ram5    : org = 0x40024000, len = 4k        /* BCKP SRAM */
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    ram6    : org = 0x00000000, len = 0
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    ram7    : org = 0x00000000, len = 0
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}
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/* For each data/text section two region are defined, a virtual region
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   and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash1);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash1);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash1);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash1);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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   of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram3);
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/* RAM region to be used for the process stack. This is the stack used by
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   the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram3);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram3);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Stack rules inclusion.*/
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INCLUDE rules_stacks.ld
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/*===========================================================================*/
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/* Custom sections for STM32F7xx.                                            */
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/*===========================================================================*/
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/* RAM region to be used for nocache segment.*/
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REGION_ALIAS("NOCACHE_RAM", ram3);
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/* RAM region to be used for eth segment.*/
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REGION_ALIAS("ETH_RAM", ram3);
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SECTIONS
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{
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    /* Special section for non cache-able areas.*/
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    .nocache (NOLOAD) : ALIGN(4)
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    {
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        __nocache_base__ = .;
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        *(.nocache)
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        *(.nocache.*)
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        *(.bss.__nocache_*)
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        . = ALIGN(4);
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        __nocache_end__ = .;
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    } > NOCACHE_RAM
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    /* Special section for Ethernet DMA non cache-able areas.*/
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    .eth (NOLOAD) : ALIGN(4)
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    {
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        __eth_base__ = .;
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        *(.eth)
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        *(.eth.*)
122
        *(.bss.__eth_*)
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        . = ALIGN(4);
124
        __eth_end__ = .;
125
    } > ETH_RAM
126
}
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/* Code rules inclusion.*/
129
INCLUDE rules_code.ld
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/* Data rules inclusion.*/
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INCLUDE rules_data.ld
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/* Memory rules inclusion.*/
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INCLUDE rules_memory.ld
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modules/NUCLEO-F767ZI/alldconf.h
1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

  
5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

  
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

  
15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
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/**
20
 * @file
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 * @brief   AMiRo-LLD configuration file for the NUCLEO-F767ZI module.
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 * @details Contains the application specific AMiRo-LLD settings.
23
 *
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 * @addtogroup NUCLEO-F767ZI_config
25
 * @{
26
 */
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28
#ifndef ALLDCONF_H
29
#define ALLDCONF_H
30

  
31
/*
32
 * compatibility guards
33
 */
34
#define _AMIRO_LLD_CFG_
35
#define AMIRO_LLD_CFG_VERSION_MAJOR             1
36
#define AMIRO_LLD_CFG_VERSION_MINOR             1
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38
/**
39
 * @brief   Width of the apalTime_t data type.
40
 *
41
 * @details Possible values are 8, 16, 32, and 64 bits.
42
 *          By definition time is represented at microsecond precision.
43
 */
44
#define AMIROLLD_CFG_TIME_SIZE                  32
45

  
46
#endif /* ALLDCONF_H */
47

  
48
/** @} */
modules/NUCLEO-F767ZI/aosconf.h
1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

  
5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

  
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

  
15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

  
19
/**
20
 * @file
21
 * @brief   AMiRo-OS Configuration file for the NUCLEO-F767ZI module.
22
 * @details Contains the application specific AMiRo-OS settings.
23
 *
24
 * @addtogroup NUCLEO-F767ZI_aos_config
25
 * @{
26
 */
27

  
28
#ifndef AOSCONF_H
29
#define AOSCONF_H
30

  
31
/*
32
 * compatibility guards
33
 */
34
#define _AMIRO_OS_CFG_
35
#define AMIRO_OS_CFG_VERSION_MAJOR              2
36
#define AMIRO_OS_CFG_VERSION_MINOR              0
37

  
38
#include <stdbool.h>
39

  
40
/*
41
 * Include an external configuration file to override the following default settings only if required.
42
 */
43
#if defined(AMIRO_APPS) && (AMIRO_APPS == true)
44
  #include <osconf.h>
45
#endif /* defined(AMIRO_APPS) && (AMIRO_APPS == true) */
46

  
47
/*===========================================================================*/
48
/**
49
 * @name Kernel parameters and options
50
 * @{
51
 */
52
/*===========================================================================*/
53

  
54
/**
55
 * @brief   Flag to enable/disable debug API and logic.
56
 */
57
#if !defined(OS_CFG_DBG)
58
  #define AMIROOS_CFG_DBG                       true
59
#else /* !defined(OS_CFG_DBG) */
60
  #define AMIROOS_CFG_DBG                       OS_CFG_DBG
61
#endif /* !defined(OS_CFG_DBG) */
62

  
63
/**
64
 * @brief   Flag to enable/disable unit tests.
65
 * @note    Setting this flag will implicitely enable the shell.
66
 */
67
#if !defined(OS_CFG_TESTS_ENABLE)
68
  #define AMIROOS_CFG_TESTS_ENABLE              true
69
#else /* !defined(OS_CFG_TESTS_ENABLE) */
70
  #define AMIROOS_CFG_TESTS_ENABLE              OS_CFG_TESTS_ENABLE
71
#endif /* !defined(OS_CFG_TESTS_ENABLE) */
72

  
73
/**
74
 * @brief   Flag to enable/disable profiling API and logic.
75
 */
76
#if !defined(OS_CFG_PROFILE)
77
  #define AMIROOS_CFG_PROFILE                   true
78
#else /* !defined(OS_CFG_PROFILE) */
79
  #define AMIROOS_CFG_PROFILE                   OS_CFG_PROFILE
80
#endif /* !defined(OS_CFG_PROFILE) */
81

  
82
/**
83
 * @brief   Mask for the control thread to listen to certain IO events.
84
 * @note    Any mandatory events (e.g. for SSSP) are enabled implicitely despite this configuration.
85
 */
86
#if !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK)
87
  #define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK    MODULE_OS_IOEVENTFLAGS_USERBUTTON
88
#else /* !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) */
89
  #define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK    OS_CFG_MAIN_LOOP_IOEVENT_MASK
90
#endif /* !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) */
91

  
92
/**
93
 * @brief   Timeout value when waiting for events in the main loop in microseconds.
94
 * @details A value of 0 deactivates the timeout.
95
 */
96
#if !defined(OS_CFG_MAIN_LOOP_TIMEOUT)
97
  #define AMIROOS_CFG_MAIN_LOOP_TIMEOUT         0
98
#else /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */
99
  #define AMIROOS_CFG_MAIN_LOOP_TIMEOUT         OS_CFG_MAIN_LOOP_TIMEOUT
100
#endif /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */
101

  
102
/** @} */
103

  
104
/*===========================================================================*/
105
/**
106
 * @name SSSP (Startup Shutdown Synchronization Protocol) configuration.
107
 * @{
108
 */
109
/*===========================================================================*/
110

  
111
/**
112
 * @brief   Flag to enable SSSP.
113
 */
114
#if !defined(OS_CFG_SSSP_ENABLE)
115
  #define AMIROOS_CFG_SSSP_ENABLE               false
116
#else /* !defined(OS_CFG_SSSP_ENABLE) */
117
  #define AMIROOS_CFG_SSSP_ENABLE               OS_CFG_SSSP_ENABLE
118
#endif /* !defined(OS_CFG_SSSP_ENABLE) */
119

  
120
/**
121
 * @brief   Flag to set the module as SSSP master.
122
 * @details There must be only one module with this flag set to true in a system.
123
 */
124
#if !defined(OS_CFG_SSSP_MASTER)
125
  #define AMIROOS_CFG_SSSP_MASTER               false
126
#else /* !defined(OS_CFG_SSSP_MASTER) */
127
  #define AMIROOS_CFG_SSSP_MASTER               OS_CFG_SSSP_MASTER
128
#endif /* !defined(OS_CFG_SSSP_MASTER) */
129

  
130
/**
131
 * @brief   Flag to set the module to be the first in the stack.
132
 * @details There must be only one module with this flag set to true in a system.
133
 */
134
#if !defined(OS_CFG_SSSP_STACK_START)
135
  #define AMIROOS_CFG_SSSP_STACK_START          false
136
#else /* !defined(OS_CFG_SSSP_STACK_START) */
137
  #define AMIROOS_CFG_SSSP_STACK_START          OS_CFG_SSSP_STACK_START
138
#endif /* !defined(OS_CFG_SSSP_STACK_START) */
139

  
140
/**
141
 * @brief   Flag to set the module to be the last in the stack.
142
 * @details There must be only one module with this flag set to true in a system.
143
 */
144
#if !defined(OS_CFG_SSSP_STACK_END)
145
  #define AMIROOS_CFG_SSSP_STACK_END            false
146
#else /* !defined(OS_CFG_SSSP_STACK_END) */
147
  #define AMIROOS_CFG_SSSP_STACK_END            OS_CFG_SSSP_STACK_END
148
#endif /* !defined(OS_CFG_SSSP_STACK_END) */
149

  
150
/**
151
 * @brief   Delay time (in microseconds) how long a SSSP signal must be active.
152
 */
153
#if !defined(OS_CFG_SSSP_SIGNALDELAY)
154
  #define AMIROOS_CFG_SSSP_SIGNALDELAY          1000
155
#else /* !defined(OS_CFG_SSSP_SIGNALDELAY) */
156
  #define AMIROOS_CFG_SSSP_SIGNALDELAY          OS_CFG_SSSP_SIGNALDELAY
157
#endif /* !defined(OS_CFG_SSSP_SIGNALDELAY) */
158

  
159
/**
160
 * @brief   Time boundary for robot wide clock synchronization in microseconds.
161
 * @details Whenever the SSSP S (snychronization) signal gets logically deactivated,
162
 *          All modules need to align their local uptime to the nearest multiple of this value.
163
 */
164
#if !defined(OS_CFG_SSSP_SYSSYNCPERIOD)
165
  #define AMIROOS_CFG_SSSP_SYSSYNCPERIOD        1000000
166
#else /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */
167
  #define AMIROOS_CFG_SSSP_SYSSYNCPERIOD        OS_CFG_SSSP_SYSSYNCPERIOD
168
#endif /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */
169

  
170
/** @} */
171

  
172
/*===========================================================================*/
173
/**
174
 * @name System shell options
175
 * @{
176
 */
177
/*===========================================================================*/
178

  
179
/**
180
 * @brief   Shell enable flag.
181
 */
182
#if !defined(OS_CFG_SHELL_ENABLE)
183
  #define AMIROOS_CFG_SHELL_ENABLE              true
184
#else /* !defined(OS_CFG_SHELL_ENABLE) */
185
  #define AMIROOS_CFG_SHELL_ENABLE              OS_CFG_SHELL_ENABLE
186
#endif /* !defined(OS_CFG_SHELL_ENABLE) */
187

  
188
/**
189
 * @brief   Shell thread stack size.
190
 */
191
#if !defined(OS_CFG_SHELL_STACKSIZE)
192
  #define AMIROOS_CFG_SHELL_STACKSIZE           1024
193
#else /* !defined(OS_CFG_SHELL_STACKSIZE) */
194
  #define AMIROOS_CFG_SHELL_STACKSIZE           OS_CFG_SHELL_STACKSIZE
195
#endif /* !defined(OS_CFG_SHELL_STACKSIZE) */
196

  
197
/**
198
 * @brief   Shell thread priority.
199
 * @details Thread priorities are specified as an integer value.
200
 *          Predefined ranges are:
201
 *            lowest  ┌ THD_LOWPRIO_MIN
202
 *                    │ ...
203
 *                    └ THD_LOWPRIO_MAX
204
 *                    ┌ THD_NORMALPRIO_MIN
205
 *                    │ ...
206
 *                    └ THD_NORMALPRIO_MAX
207
 *                    ┌ THD_HIGHPRIO_MIN
208
 *                    │ ...
209
 *                    └ THD_HIGHPRIO_MAX
210
 *                    ┌ THD_RTPRIO_MIN
211
 *                    │ ...
212
 *            highest └ THD_RTPRIO_MAX
213
 */
214
#if !defined(OS_CFG_SHELL_THREADPRIO)
215
  #define AMIROOS_CFG_SHELL_THREADPRIO          AOS_THD_NORMALPRIO_MIN
216
#else /* !defined(OS_CFG_SHELL_THREADPRIO) */
217
  #define AMIROOS_CFG_SHELL_THREADPRIO          OS_CFG_SHELL_THREADPRIO
218
#endif /* !defined(OS_CFG_SHELL_THREADPRIO) */
219

  
220
/**
221
 * @brief   Shell maximum input line length.
222
 */
223
#if !defined(OS_CFG_SHELL_LINEWIDTH)
224
  #define AMIROOS_CFG_SHELL_LINEWIDTH           128
225
#else /* !defined(OS_CFG_SHELL_LINEWIDTH) */
226
  #define AMIROOS_CFG_SHELL_LINEWIDTH           OS_CFG_SHELL_LINEWIDTH
227
#endif /* !defined(OS_CFG_SHELL_LINEWIDTH) */
228

  
229
/**
230
 * @brief   Shell maximum number of arguments.
231
 */
232
#if !defined(OS_CFG_SHELL_MAXARGS)
233
  #define AMIROOS_CFG_SHELL_MAXARGS             16
234
#else /* !defined(OS_CFG_SHELL_MAXARGS) */
235
  #define AMIROOS_CFG_SHELL_MAXARGS             OS_CFG_SHELL_MAXARGS
236
#endif /* !defined(OS_CFG_SHELL_MAXARGS) */
237

  
238
/** @} */
239

  
240
#endif /* AOSCONF_H */
241

  
242
/** @} */
modules/NUCLEO-F767ZI/board.c
1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

  
5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

  
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

  
15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

  
19
#include "hal.h"
20
#include "stm32_gpio.h"
21

  
22
/*===========================================================================*/
23
/* Driver local definitions.                                                 */
24
/*===========================================================================*/
25

  
26
/*===========================================================================*/
27
/* Driver exported variables.                                                */
28
/*===========================================================================*/
29

  
30
/*===========================================================================*/
31
/* Driver local variables and types.                                         */
32
/*===========================================================================*/
33

  
34
/**
35
 * @brief   Type of STM32 GPIO port setup.
36
 */
37
typedef struct {
38
  uint32_t              moder;
39
  uint32_t              otyper;
40
  uint32_t              ospeedr;
41
  uint32_t              pupdr;
42
  uint32_t              odr;
43
  uint32_t              afrl;
44
  uint32_t              afrh;
45
} gpio_setup_t;
46

  
47
/**
48
 * @brief   Type of STM32 GPIO initialization data.
49
 */
50
typedef struct {
51
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
52
  gpio_setup_t          PAData;
53
#endif
54
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
55
  gpio_setup_t          PBData;
56
#endif
57
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
58
  gpio_setup_t          PCData;
59
#endif
60
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
61
  gpio_setup_t          PDData;
62
#endif
63
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
64
  gpio_setup_t          PEData;
65
#endif
66
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
67
  gpio_setup_t          PFData;
68
#endif
69
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
70
  gpio_setup_t          PGData;
71
#endif
72
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
73
  gpio_setup_t          PHData;
74
#endif
75
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
76
  gpio_setup_t          PIData;
77
#endif
78
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
79
  gpio_setup_t          PJData;
80
#endif
81
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
82
  gpio_setup_t          PKData;
83
#endif
84
} gpio_config_t;
85

  
86
/**
87
 * @brief   STM32 GPIO static initialization data.
88
 */
89
static const gpio_config_t gpio_default_config = {
90
#if STM32_HAS_GPIOA
91
  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
92
   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
93
#endif
94
#if STM32_HAS_GPIOB
95
  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
96
   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
97
#endif
98
#if STM32_HAS_GPIOC
99
  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
100
   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
101
#endif
102
#if STM32_HAS_GPIOD
103
  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
104
   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
105
#endif
106
#if STM32_HAS_GPIOE
107
  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
108
   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
109
#endif
110
#if STM32_HAS_GPIOF
111
  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
112
   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
113
#endif
114
#if STM32_HAS_GPIOG
115
  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
116
   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
117
#endif
118
#if STM32_HAS_GPIOH
119
  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
120
   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
121
#endif
122
#if STM32_HAS_GPIOI
123
  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
124
   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
125
#endif
126
#if STM32_HAS_GPIOJ
127
  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
128
   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},
129
#endif
130
#if STM32_HAS_GPIOK
131
  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
132
   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}
133
#endif
134
};
135

  
136
/*===========================================================================*/
137
/* Driver local functions.                                                   */
138
/*===========================================================================*/
139

  
140
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
141

  
142
  gpiop->OTYPER  = config->otyper;
143
  gpiop->OSPEEDR = config->ospeedr;
144
  gpiop->PUPDR   = config->pupdr;
145
  gpiop->ODR     = config->odr;
146
  gpiop->AFRL    = config->afrl;
147
  gpiop->AFRH    = config->afrh;
148
  gpiop->MODER   = config->moder;
149
}
150

  
151
static void stm32_gpio_init(void) {
152

  
153
  /* Enabling GPIO-related clocks, the mask comes from the
154
     registry header file.*/
155
  rccResetAHB1(STM32_GPIO_EN_MASK);
156
  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
157

  
158
  /* Initializing all the defined GPIO ports.*/
159
#if STM32_HAS_GPIOA
160
  gpio_init(GPIOA, &gpio_default_config.PAData);
161
#endif
162
#if STM32_HAS_GPIOB
163
  gpio_init(GPIOB, &gpio_default_config.PBData);
164
#endif
165
#if STM32_HAS_GPIOC
166
  gpio_init(GPIOC, &gpio_default_config.PCData);
167
#endif
168
#if STM32_HAS_GPIOD
169
  gpio_init(GPIOD, &gpio_default_config.PDData);
170
#endif
171
#if STM32_HAS_GPIOE
172
  gpio_init(GPIOE, &gpio_default_config.PEData);
173
#endif
174
#if STM32_HAS_GPIOF
175
  gpio_init(GPIOF, &gpio_default_config.PFData);
176
#endif
177
#if STM32_HAS_GPIOG
178
  gpio_init(GPIOG, &gpio_default_config.PGData);
179
#endif
180
#if STM32_HAS_GPIOH
181
  gpio_init(GPIOH, &gpio_default_config.PHData);
182
#endif
183
#if STM32_HAS_GPIOI
184
  gpio_init(GPIOI, &gpio_default_config.PIData);
185
#endif
186
#if STM32_HAS_GPIOJ
187
  gpio_init(GPIOJ, &gpio_default_config.PJData);
188
#endif
189
#if STM32_HAS_GPIOK
190
  gpio_init(GPIOK, &gpio_default_config.PKData);
191
#endif
192
}
193

  
194
/*===========================================================================*/
195
/* Driver interrupt handlers.                                                */
196
/*===========================================================================*/
197

  
198
/*===========================================================================*/
199
/* Driver exported functions.                                                */
200
/*===========================================================================*/
201

  
202
/**
203
 * @brief   Early initialization code.
204
 * @details GPIO ports and system clocks are initialized before everything
205
 *          else.
206
 */
207
void __early_init(void) {
208

  
209
  stm32_gpio_init();
210
  stm32_clock_init();
211
}
212

  
213
#if HAL_USE_SDC || defined(__DOXYGEN__)
214
/**
215
 * @brief   SDC card detection.
216
 */
217
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
218

  
219
  (void)sdcp;
220
  /* TODO: Fill the implementation.*/
221
  return true;
222
}
223

  
224
/**
225
 * @brief   SDC card write protection detection.
226
 */
227
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
228

  
229
  (void)sdcp;
230
  /* TODO: Fill the implementation.*/
231
  return false;
232
}
233
#endif /* HAL_USE_SDC */
234

  
235
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
236
/**
237
 * @brief   MMC_SPI card detection.
238
 */
239
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
240

  
241
  (void)mmcp;
242
  /* TODO: Fill the implementation.*/
243
  return true;
244
}
245

  
246
/**
247
 * @brief   MMC_SPI card write protection detection.
248
 */
249
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
250

  
251
  (void)mmcp;
252
  /* TODO: Fill the implementation.*/
253
  return false;
254
}
255
#endif
256

  
257
/**
258
 * @brief   Board-specific initialization code.
259
 * @todo    Add your board-specific code, if any.
260
 */
261
void boardInit(void) {
262

  
263
}
modules/NUCLEO-F767ZI/board.h
1
/*
2
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
3
Copyright (C) 2016..2019  Thomas Schöpping et al.
4

  
5
This program is free software: you can redistribute it and/or modify
6
it under the terms of the GNU General Public License as published by
7
the Free Software Foundation, either version 3 of the License, or
8
(at your option) any later version.
9

  
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
14

  
15
You should have received a copy of the GNU General Public License
16
along with this program.  If not, see <http://www.gnu.org/licenses/>.
17
*/
18

  
19
#ifndef BOARD_H
20
#define BOARD_H
21

  
22
/*===========================================================================*/
23
/* Driver constants.                                                         */
24
/*===========================================================================*/
25

  
26
/*
27
 * Setup for STMicroelectronics STM32 Nucleo144-F767ZI board.
28
 */
29

  
30
/*
31
 * Board identifier.
32
 */
33
#define BOARD_ST_NUCLEO144_F767ZI
34
#define BOARD_NAME                  "STMicroelectronics STM32 Nucleo144-F767ZI"
35

  
36
/*
37
 * Ethernet PHY type.
38
 */
39
#define BOARD_PHY_ID                MII_LAN8742A_ID
40
#define BOARD_PHY_RMII
41

  
42
/*
43
 * Board oscillators-related settings.
44
 */
45
#if !defined(STM32_LSECLK)
46
#define STM32_LSECLK                32768U
47
#endif
48

  
49
#define STM32_LSEDRV                (3U << 3U)
50

  
51
#if !defined(STM32_HSECLK)
52
#define STM32_HSECLK                8000000U
53
#endif
54

  
55
#define STM32_HSE_BYPASS
56

  
57
/*
58
 * Board voltages.
59
 * Required for performance limits calculation.
60
 */
61
#define STM32_VDD                   300U
62

  
63
/*
64
 * MCU type as defined in the ST header.
65
 */
66
#define STM32F767xx
67

  
68
/*
69
 * IO pins assignments.
70
 */
71
#define GPIOA_ZIO_D32               0U
72
#define GPIOA_TIM2_CH1              0U
73
#define GPIOA_RMII_REF_CLK          1U
74
#define GPIOA_RMII_MDIO             2U
75
#define GPIOA_ARD_A0                3U
76
#define GPIOA_ADC123_IN3            3U
77
#define GPIOA_ZIO_D24               4U
78
#define GPIOA_SPI3_NSS              4U
79
#define GPIOA_ARD_D13               5U
80
#define GPIOA_SPI1_SCK              5U
81
#define GPIOA_ARD_D12               6U
82
#define GPIOA_SPI1_MISO             6U
83
#define GPIOA_ARD_D11               7U
84
#define GPIOA_SPI1_MOSI             7U
85
#define GPIOA_ZIO_D71               7U
86
#define GPIOA_RMII_RX_DV            7U
87
#define GPIOA_USB_SOF               8U
88
#define GPIOA_USB_VBUS              9U
89
#define GPIOA_USB_ID                10U
90
#define GPIOA_USB_DM                11U
91
#define GPIOA_USB_DP                12U
92
#define GPIOA_SWDIO                 13U
93
#define GPIOA_SWCLK                 14U
94
#define GPIOA_ZIO_D20               15U
95
#define GPIOA_I2S3_WS               15U
96

  
97
#define GPIOB_ZIO_D33               0U
98
#define GPIOB_TIM3_CH3              0U
99
#define GPIOB_LED1                  0U
100
#define GPIOB_ZIO_A6                1U
101
#define GPIOB_ADC12_IN9             1U
102
#define GPIOB_ZIO_D27               2U
103
#define GPIOB_QSPI_CLK              2U
104
#define GPIOB_ZIO_D23               3U
105
#define GPIOB_I2S3_CK               3U
106
#define GPIOB_ZIO_D25               4U
107
#define GPIOB_SPI3_MISO             4U
108
#define GPIOB_ZIO_D22               5U
109
#define GPIOB_I2S3_SD               5U
110
#define GPIOB_ZIO_D26               6U
111
#define GPIOB_QSPI_BK1_NCS          6U
112
#define GPIOB_LED2                  7U
113
#define GPIOB_ARD_D15               8U
114
#define GPIOB_I2C1_SCL              8U
115
#define GPIOB_ARD_D14               9U
116
#define GPIOB_I2C1_SDA              9U
117
#define GPIOB_ZIO_D36               10U
118
#define GPIOB_TIM2_CH3              10U
119
#define GPIOB_ZIO_D35               11U
120
#define GPIOB_TIM2_CH4              11U
121
#define GPIOB_ZIO_D19               12U
122
#define GPIOB_I2S2_WS               12U
123
#define GPIOB_ZIO_D18               13U
124
#define GPIOB_I2S2_CK               13U
125
#define GPIOB_RMII_TXD1             13U
126
#define GPIOB_LED3                  14U
127
#define GPIOB_ZIO_D17               15U
128
#define GPIOB_I2S2_SD               15U
129

  
130
#define GPIOC_ARD_A1                0U
131
#define GPIOC_ADC123_IN10           0U
132
#define GPIOC_RMII_MDC              1U
133
#define GPIOC_ZIO_A7                2U
134
#define GPIOC_ADC123_IN12           2U
135
#define GPIOC_ARD_A2                3U
136
#define GPIOC_ADC123_IN13           3U
137
#define GPIOC_RMII_RXD0             4U
138
#define GPIOC_RMII_RXD1             5U
139
#define GPIOC_ZIO_D16               6U
140
#define GPIOC_I2S2_MCK              6U
141
#define GPIOC_ZIO_D21               7U
142
#define GPIOC_I2S3_MCK              7U
143
#define GPIOC_ZIO_D43               8U
144
#define GPIOC_SDMMC_D0              8U
145
#define GPIOC_ZIO_D44               9U
146
#define GPIOC_SDMMC_D1              9U
147
#define GPIOC_ZIO_D45               10U
148
#define GPIOC_SDMMC_D2              10U
149
#define GPIOC_ZIO_D46               11U
150
#define GPIOC_SDMMC_D3              11U
151
#define GPIOC_ZIO_D47               12U
152
#define GPIOC_SDMMC_CK              12U
153
#define GPIOC_BUTTON                13U
154
#define GPIOC_OSC32_IN              14U
155
#define GPIOC_OSC32_OUT             15U
156

  
157
#define GPIOD_ZIO_D67               0U
158
#define GPIOD_CAN1_RX               0U
159
#define GPIOD_ZIO_D66               1U
160
#define GPIOD_CAN1_TX               1U
161
#define GPIOD_ZIO_D48               2U
162
#define GPIOD_SDMMC_CMD             2U
163
#define GPIOD_ZIO_D55               3U
164
#define GPIOD_USART2_CTS            3U
165
#define GPIOD_ZIO_D54               4U
166
#define GPIOD_USART2_RTS            4U
167
#define GPIOD_ZIO_D53               5U
168
#define GPIOD_USART2_TX             5U
169
#define GPIOD_ZIO_D52               6U
170
#define GPIOD_USART2_RX             6U
171
#define GPIOD_ZIO_D51               7U
172
#define GPIOD_USART2_SCLK           7U
173
#define GPIOD_USART3_RX             8U
174
#define GPIOD_STLK_RX               8U
175
#define GPIOD_USART3_TX             9U
176
#define GPIOD_STLK_TX               9U
177
#define GPIOD_PIN10                 10U
178
#define GPIOD_ZIO_D30               11U
179
#define GPIOD_QSPI_BK1_IO0          11U
180
#define GPIOD_ZIO_D29               12U
181
#define GPIOD_QSPI_BK1_IO1          12U
182
#define GPIOD_ZIO_D28               13U
183
#define GPIOD_QSPI_BK1_IO3          13U
184
#define GPIOD_ARD_D10               14U
185
#define GPIOD_SPI1_NSS              14U
186
#define GPIOD_ARD_D9                15U
187
#define GPIOD_TIM4_CH4              15U
188

  
189
#define GPIOE_ZIO_D34               0U
190
#define GPIOE_TIM4_ETR              0U
191
#define GPIOE_PIN1                  1U
192
#define GPIOE_ZIO_D31               2U
193
#define GPIOE_ZIO_D56               2U
194
#define GPIOE_SAI1_MCLK_A           2U
195
#define GPIOE_ZIO_D60               3U
196
#define GPIOE_SAI1_SD_B             3U
197
#define GPIOE_ZIO_D57               4U
198
#define GPIOE_SAI1_FS_A             4U
199
#define GPIOE_ZIO_D58               5U
200
#define GPIOE_SAI1_SCK_A            5U
201
#define GPIOE_ZIO_D59               6U
202
#define GPIOE_SAI1_SD_A             6U
203
#define GPIOE_ZIO_D41               7U
204
#define GPIOE_TIM1_ETR              7U
205
#define GPIOE_ZIO_D42               8U
206
#define GPIOE_TIM1_CH1N             8U
207
#define GPIOE_ARD_D6                9U
208
#define GPIOE_TIM1_CH1              9U
209
#define GPIOE_ZIO_D40               10U
210
#define GPIOE_TIM1_CH2N             10U
211
#define GPIOE_ARD_D5                11U
212
#define GPIOE_TIM1_CH2              11U
213
#define GPIOE_ZIO_D39               12U
214
#define GPIOE_TIM1_CH3N             12U
215
#define GPIOE_ARD_D3                13U
216
#define GPIOE_TIM1_CH3              13U
217
#define GPIOE_ZIO_D38               14U
218
#define GPIOE_ZIO_D37               15U
219
#define GPIOE_TIM1_BKIN1            15U
220

  
221
#define GPIOF_ZIO_D68               0U
222
#define GPIOF_I2C2_SDA              0U
223
#define GPIOF_ZIO_D69               1U
224
#define GPIOF_I2C2_SCL              1U
225
#define GPIOF_ZIO_D70               2U
226
#define GPIOF_I2C2_SMBA             2U
227
#define GPIOF_ARD_A3                3U
228
#define GPIOF_ADC3_IN9              3U
229
#define GPIOF_ZIO_A8                4U
230
#define GPIOF_ADC3_IN14             4U
231
#define GPIOF_ARD_A4                5U
232
#define GPIOF_ADC3_IN15             5U
233
#define GPIOF_PIN6                  6U
234
#define GPIOF_ZIO_D62               7U
235
#define GPIOF_SAI1_MCLK_B           7U
236
#define GPIOF_ZIO_D61               8U
237
#define GPIOF_SAI1_SCK_B            8U
238
#define GPIOF_ZIO_D63               9U
239
#define GPIOF_SAI1_FS_B             9U
240
#define GPIOF_ARD_A5                10U
241
#define GPIOF_ADC3_IN8              10U
242
#define GPIOF_PIN11                 11U
243
#define GPIOF_ARD_D8                12U
244
#define GPIOF_ARD_D7                13U
245
#define GPIOF_ARD_D4                14U
246
#define GPIOF_ARD_D2                15U
247

  
248
#define GPIOG_ZIO_D65               0U
249
#define GPIOG_ZIO_D64               1U
250
#define GPIOG_ZIO_D49               2U
251
#define GPIOG_ZIO_D50               3U
252
#define GPIOG_PIN4                  4U
253
#define GPIOG_PIN5                  5U
254
#define GPIOG_USB_GPIO_OUT          6U
255
#define GPIOG_USB_GPIO_IN           7U
256
#define GPIOG_PIN8                  8U
257
#define GPIOG_ARD_D0                9U
258
#define GPIOG_USART6_RX             9U
259
#define GPIOG_PIN10                 10U
260
#define GPIOG_RMII_TX_EN            11U
261
#define GPIOG_PIN12                 12U
262
#define GPIOG_RMII_TXD0             13U
263
#define GPIOG_ARD_D1                14U
264
#define GPIOG_USART6_TX             14U
265
#define GPIOG_PIN15                 15U
266

  
267
#define GPIOH_OSC_IN                0U
268
#define GPIOH_OSC_OUT               1U
269
#define GPIOH_PIN2                  2U
270
#define GPIOH_PIN3                  3U
271
#define GPIOH_PIN4                  4U
272
#define GPIOH_PIN5                  5U
273
#define GPIOH_PIN6                  6U
274
#define GPIOH_PIN7                  7U
275
#define GPIOH_PIN8                  8U
276
#define GPIOH_PIN9                  9U
277
#define GPIOH_PIN10                 10U
278
#define GPIOH_PIN11                 11U
279
#define GPIOH_PIN12                 12U
280
#define GPIOH_PIN13                 13U
281
#define GPIOH_PIN14                 14U
282
#define GPIOH_PIN15                 15U
283

  
284
#define GPIOI_PIN0                  0U
285
#define GPIOI_PIN1                  1U
286
#define GPIOI_PIN2                  2U
287
#define GPIOI_PIN3                  3U
288
#define GPIOI_PIN4                  4U
289
#define GPIOI_PIN5                  5U
290
#define GPIOI_PIN6                  6U
291
#define GPIOI_PIN7                  7U
292
#define GPIOI_PIN8                  8U
293
#define GPIOI_PIN9                  9U
294
#define GPIOI_PIN10                 10U
295
#define GPIOI_PIN11                 11U
296
#define GPIOI_PIN12                 12U
297
#define GPIOI_PIN13                 13U
298
#define GPIOI_PIN14                 14U
299
#define GPIOI_PIN15                 15U
300

  
301
#define GPIOJ_PIN0                  0U
302
#define GPIOJ_PIN1                  1U
303
#define GPIOJ_PIN2                  2U
304
#define GPIOJ_PIN3                  3U
305
#define GPIOJ_PIN4                  4U
306
#define GPIOJ_PIN5                  5U
307
#define GPIOJ_PIN6                  6U
308
#define GPIOJ_PIN7                  7U
309
#define GPIOJ_PIN8                  8U
310
#define GPIOJ_PIN9                  9U
311
#define GPIOJ_PIN10                 10U
312
#define GPIOJ_PIN11                 11U
313
#define GPIOJ_PIN12                 12U
314
#define GPIOJ_PIN13                 13U
315
#define GPIOJ_PIN14                 14U
316
#define GPIOJ_PIN15                 15U
317

  
318
#define GPIOK_PIN0                  0U
319
#define GPIOK_PIN1                  1U
320
#define GPIOK_PIN2                  2U
321
#define GPIOK_PIN3                  3U
322
#define GPIOK_PIN4                  4U
323
#define GPIOK_PIN5                  5U
324
#define GPIOK_PIN6                  6U
325
#define GPIOK_PIN7                  7U
326
#define GPIOK_PIN8                  8U
327
#define GPIOK_PIN9                  9U
328
#define GPIOK_PIN10                 10U
329
#define GPIOK_PIN11                 11U
330
#define GPIOK_PIN12                 12U
331
#define GPIOK_PIN13                 13U
332
#define GPIOK_PIN14                 14U
333
#define GPIOK_PIN15                 15U
334

  
335
/*
336
 * IO lines assignments.
337
 */
338
#define LINE_ZIO_D32                PAL_LINE(GPIOA, 0U)
339
#define LINE_TIM2_CH1               PAL_LINE(GPIOA, 0U)
340
#define LINE_RMII_REF_CLK           PAL_LINE(GPIOA, 1U)
341
#define LINE_RMII_MDIO              PAL_LINE(GPIOA, 2U)
342
#define LINE_ARD_A0                 PAL_LINE(GPIOA, 3U)
343
#define LINE_ADC123_IN3             PAL_LINE(GPIOA, 3U)
344
#define LINE_ZIO_D24                PAL_LINE(GPIOA, 4U)
345
#define LINE_SPI3_NSS               PAL_LINE(GPIOA, 4U)
346
#define LINE_ARD_D13                PAL_LINE(GPIOA, 5U)
347
#define LINE_SPI1_SCK               PAL_LINE(GPIOA, 5U)
348
#define LINE_ARD_D12                PAL_LINE(GPIOA, 6U)
349
#define LINE_SPI1_MISO              PAL_LINE(GPIOA, 6U)
350
#define LINE_ARD_D11                PAL_LINE(GPIOA, 7U)
351
#define LINE_SPI1_MOSI              PAL_LINE(GPIOA, 7U)
352
#define LINE_ZIO_D71                PAL_LINE(GPIOA, 7U)
353
#define LINE_RMII_RX_DV             PAL_LINE(GPIOA, 7U)
354
#define LINE_USB_SOF                PAL_LINE(GPIOA, 8U)
355
#define LINE_USB_VBUS               PAL_LINE(GPIOA, 9U)
356
#define LINE_USB_ID                 PAL_LINE(GPIOA, 10U)
357
#define LINE_USB_DM                 PAL_LINE(GPIOA, 11U)
358
#define LINE_USB_DP                 PAL_LINE(GPIOA, 12U)
359
#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
360
#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)
361
#define LINE_ZIO_D20                PAL_LINE(GPIOA, 15U)
362
#define LINE_I2S3_WS                PAL_LINE(GPIOA, 15U)
363
#define LINE_ZIO_D33                PAL_LINE(GPIOB, 0U)
364
#define LINE_TIM3_CH3               PAL_LINE(GPIOB, 0U)
365
#define LINE_LED1                   PAL_LINE(GPIOB, 0U)
366
#define LINE_ZIO_A6                 PAL_LINE(GPIOB, 1U)
367
#define LINE_ADC12_IN9              PAL_LINE(GPIOB, 1U)
368
#define LINE_ZIO_D27                PAL_LINE(GPIOB, 2U)
369
#define LINE_QSPI_CLK               PAL_LINE(GPIOB, 2U)
370
#define LINE_ZIO_D23                PAL_LINE(GPIOB, 3U)
371
#define LINE_I2S3_CK                PAL_LINE(GPIOB, 3U)
372
#define LINE_ZIO_D25                PAL_LINE(GPIOB, 4U)
373
#define LINE_SPI3_MISO              PAL_LINE(GPIOB, 4U)
374
#define LINE_ZIO_D22                PAL_LINE(GPIOB, 5U)
375
#define LINE_I2S3_SD                PAL_LINE(GPIOB, 5U)
376
#define LINE_ZIO_D26                PAL_LINE(GPIOB, 6U)
377
#define LINE_QSPI_BK1_NCS           PAL_LINE(GPIOB, 6U)
378
#define LINE_LED2                   PAL_LINE(GPIOB, 7U)
379
#define LINE_ARD_D15                PAL_LINE(GPIOB, 8U)
380
#define LINE_I2C1_SCL               PAL_LINE(GPIOB, 8U)
381
#define LINE_ARD_D14                PAL_LINE(GPIOB, 9U)
382
#define LINE_I2C1_SDA               PAL_LINE(GPIOB, 9U)
383
#define LINE_ZIO_D36                PAL_LINE(GPIOB, 10U)
384
#define LINE_TIM2_CH3               PAL_LINE(GPIOB, 10U)
385
#define LINE_ZIO_D35                PAL_LINE(GPIOB, 11U)
386
#define LINE_TIM2_CH4               PAL_LINE(GPIOB, 11U)
387
#define LINE_ZIO_D19                PAL_LINE(GPIOB, 12U)
388
#define LINE_I2S2_WS                PAL_LINE(GPIOB, 12U)
389
#define LINE_ZIO_D18                PAL_LINE(GPIOB, 13U)
390
#define LINE_I2S2_CK                PAL_LINE(GPIOB, 13U)
391
#define LINE_RMII_TXD1              PAL_LINE(GPIOB, 13U)
392
#define LINE_LED3                   PAL_LINE(GPIOB, 14U)
393
#define LINE_ZIO_D17                PAL_LINE(GPIOB, 15U)
394
#define LINE_I2S2_SD                PAL_LINE(GPIOB, 15U)
395
#define LINE_ARD_A1                 PAL_LINE(GPIOC, 0U)
396
#define LINE_ADC123_IN10            PAL_LINE(GPIOC, 0U)
397
#define LINE_RMII_MDC               PAL_LINE(GPIOC, 1U)
398
#define LINE_ZIO_A7                 PAL_LINE(GPIOC, 2U)
399
#define LINE_ADC123_IN12            PAL_LINE(GPIOC, 2U)
400
#define LINE_ARD_A2                 PAL_LINE(GPIOC, 3U)
401
#define LINE_ADC123_IN13            PAL_LINE(GPIOC, 3U)
402
#define LINE_RMII_RXD0              PAL_LINE(GPIOC, 4U)
403
#define LINE_RMII_RXD1              PAL_LINE(GPIOC, 5U)
404
#define LINE_ZIO_D16                PAL_LINE(GPIOC, 6U)
405
#define LINE_I2S2_MCK               PAL_LINE(GPIOC, 6U)
406
#define LINE_ZIO_D21                PAL_LINE(GPIOC, 7U)
407
#define LINE_I2S3_MCK               PAL_LINE(GPIOC, 7U)
408
#define LINE_ZIO_D43                PAL_LINE(GPIOC, 8U)
409
#define LINE_SDMMC_D0               PAL_LINE(GPIOC, 8U)
410
#define LINE_ZIO_D44                PAL_LINE(GPIOC, 9U)
411
#define LINE_SDMMC_D1               PAL_LINE(GPIOC, 9U)
412
#define LINE_ZIO_D45                PAL_LINE(GPIOC, 10U)
413
#define LINE_SDMMC_D2               PAL_LINE(GPIOC, 10U)
414
#define LINE_ZIO_D46                PAL_LINE(GPIOC, 11U)
415
#define LINE_SDMMC_D3               PAL_LINE(GPIOC, 11U)
416
#define LINE_ZIO_D47                PAL_LINE(GPIOC, 12U)
417
#define LINE_SDMMC_CK               PAL_LINE(GPIOC, 12U)
418
#define LINE_BUTTON                 PAL_LINE(GPIOC, 13U)
419
#define LINE_OSC32_IN               PAL_LINE(GPIOC, 14U)
420
#define LINE_OSC32_OUT              PAL_LINE(GPIOC, 15U)
421
#define LINE_ZIO_D67                PAL_LINE(GPIOD, 0U)
422
#define LINE_CAN1_RX                PAL_LINE(GPIOD, 0U)
423
#define LINE_ZIO_D66                PAL_LINE(GPIOD, 1U)
424
#define LINE_CAN1_TX                PAL_LINE(GPIOD, 1U)
425
#define LINE_ZIO_D48                PAL_LINE(GPIOD, 2U)
426
#define LINE_SDMMC_CMD              PAL_LINE(GPIOD, 2U)
427
#define LINE_ZIO_D55                PAL_LINE(GPIOD, 3U)
428
#define LINE_USART2_CTS             PAL_LINE(GPIOD, 3U)
429
#define LINE_ZIO_D54                PAL_LINE(GPIOD, 4U)
430
#define LINE_USART2_RTS             PAL_LINE(GPIOD, 4U)
431
#define LINE_ZIO_D53                PAL_LINE(GPIOD, 5U)
432
#define LINE_USART2_TX              PAL_LINE(GPIOD, 5U)
433
#define LINE_ZIO_D52                PAL_LINE(GPIOD, 6U)
434
#define LINE_USART2_RX              PAL_LINE(GPIOD, 6U)
435
#define LINE_ZIO_D51                PAL_LINE(GPIOD, 7U)
436
#define LINE_USART2_SCLK            PAL_LINE(GPIOD, 7U)
437
#define LINE_USART3_RX              PAL_LINE(GPIOD, 8U)
438
#define LINE_STLK_RX                PAL_LINE(GPIOD, 8U)
439
#define LINE_USART3_TX              PAL_LINE(GPIOD, 9U)
440
#define LINE_STLK_TX                PAL_LINE(GPIOD, 9U)
441
#define LINE_ZIO_D30                PAL_LINE(GPIOD, 11U)
442
#define LINE_QSPI_BK1_IO0           PAL_LINE(GPIOD, 11U)
443
#define LINE_ZIO_D29                PAL_LINE(GPIOD, 12U)
444
#define LINE_QSPI_BK1_IO1           PAL_LINE(GPIOD, 12U)
445
#define LINE_ZIO_D28                PAL_LINE(GPIOD, 13U)
446
#define LINE_QSPI_BK1_IO3           PAL_LINE(GPIOD, 13U)
447
#define LINE_ARD_D10                PAL_LINE(GPIOD, 14U)
448
#define LINE_SPI1_NSS               PAL_LINE(GPIOD, 14U)
449
#define LINE_ARD_D9                 PAL_LINE(GPIOD, 15U)
450
#define LINE_TIM4_CH4               PAL_LINE(GPIOD, 15U)
451
#define LINE_ZIO_D34                PAL_LINE(GPIOE, 0U)
452
#define LINE_TIM4_ETR               PAL_LINE(GPIOE, 0U)
453
#define LINE_ZIO_D31                PAL_LINE(GPIOE, 2U)
454
#define LINE_ZIO_D56                PAL_LINE(GPIOE, 2U)
455
#define LINE_SAI1_MCLK_A            PAL_LINE(GPIOE, 2U)
456
#define LINE_ZIO_D60                PAL_LINE(GPIOE, 3U)
457
#define LINE_SAI1_SD_B              PAL_LINE(GPIOE, 3U)
458
#define LINE_ZIO_D57                PAL_LINE(GPIOE, 4U)
459
#define LINE_SAI1_FS_A              PAL_LINE(GPIOE, 4U)
460
#define LINE_ZIO_D58                PAL_LINE(GPIOE, 5U)
461
#define LINE_SAI1_SCK_A             PAL_LINE(GPIOE, 5U)
462
#define LINE_ZIO_D59                PAL_LINE(GPIOE, 6U)
463
#define LINE_SAI1_SD_A              PAL_LINE(GPIOE, 6U)
464
#define LINE_ZIO_D41                PAL_LINE(GPIOE, 7U)
465
#define LINE_TIM1_ETR               PAL_LINE(GPIOE, 7U)
466
#define LINE_ZIO_D42                PAL_LINE(GPIOE, 8U)
467
#define LINE_TIM1_CH1N              PAL_LINE(GPIOE, 8U)
468
#define LINE_ARD_D6                 PAL_LINE(GPIOE, 9U)
469
#define LINE_TIM1_CH1               PAL_LINE(GPIOE, 9U)
470
#define LINE_ZIO_D40                PAL_LINE(GPIOE, 10U)
471
#define LINE_TIM1_CH2N              PAL_LINE(GPIOE, 10U)
472
#define LINE_ARD_D5                 PAL_LINE(GPIOE, 11U)
473
#define LINE_TIM1_CH2               PAL_LINE(GPIOE, 11U)
474
#define LINE_ZIO_D39                PAL_LINE(GPIOE, 12U)
475
#define LINE_TIM1_CH3N              PAL_LINE(GPIOE, 12U)
476
#define LINE_ARD_D3                 PAL_LINE(GPIOE, 13U)
477
#define LINE_TIM1_CH3               PAL_LINE(GPIOE, 13U)
478
#define LINE_ZIO_D38                PAL_LINE(GPIOE, 14U)
479
#define LINE_ZIO_D37                PAL_LINE(GPIOE, 15U)
480
#define LINE_TIM1_BKIN1             PAL_LINE(GPIOE, 15U)
481
#define LINE_ZIO_D68                PAL_LINE(GPIOF, 0U)
482
#define LINE_I2C2_SDA               PAL_LINE(GPIOF, 0U)
483
#define LINE_ZIO_D69                PAL_LINE(GPIOF, 1U)
484
#define LINE_I2C2_SCL               PAL_LINE(GPIOF, 1U)
485
#define LINE_ZIO_D70                PAL_LINE(GPIOF, 2U)
486
#define LINE_I2C2_SMBA              PAL_LINE(GPIOF, 2U)
487
#define LINE_ARD_A3                 PAL_LINE(GPIOF, 3U)
488
#define LINE_ADC3_IN9               PAL_LINE(GPIOF, 3U)
489
#define LINE_ZIO_A8                 PAL_LINE(GPIOF, 4U)
490
#define LINE_ADC3_IN14              PAL_LINE(GPIOF, 4U)
491
#define LINE_ARD_A4                 PAL_LINE(GPIOF, 5U)
492
#define LINE_ADC3_IN15              PAL_LINE(GPIOF, 5U)
493
#define LINE_ZIO_D62                PAL_LINE(GPIOF, 7U)
494
#define LINE_SAI1_MCLK_B            PAL_LINE(GPIOF, 7U)
495
#define LINE_ZIO_D61                PAL_LINE(GPIOF, 8U)
496
#define LINE_SAI1_SCK_B             PAL_LINE(GPIOF, 8U)
497
#define LINE_ZIO_D63                PAL_LINE(GPIOF, 9U)
498
#define LINE_SAI1_FS_B              PAL_LINE(GPIOF, 9U)
499
#define LINE_ARD_A5                 PAL_LINE(GPIOF, 10U)
500
#define LINE_ADC3_IN8               PAL_LINE(GPIOF, 10U)
501
#define LINE_ARD_D8                 PAL_LINE(GPIOF, 12U)
502
#define LINE_ARD_D7                 PAL_LINE(GPIOF, 13U)
503
#define LINE_ARD_D4                 PAL_LINE(GPIOF, 14U)
504
#define LINE_ARD_D2                 PAL_LINE(GPIOF, 15U)
505
#define LINE_ZIO_D65                PAL_LINE(GPIOG, 0U)
506
#define LINE_ZIO_D64                PAL_LINE(GPIOG, 1U)
507
#define LINE_ZIO_D49                PAL_LINE(GPIOG, 2U)
508
#define LINE_ZIO_D50                PAL_LINE(GPIOG, 3U)
509
#define LINE_USB_GPIO_OUT           PAL_LINE(GPIOG, 6U)
510
#define LINE_USB_GPIO_IN            PAL_LINE(GPIOG, 7U)
... This diff was truncated because it exceeds the maximum size that can be displayed.

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