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1 |
diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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2 |
index 6ade226..96c9da0 100644
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3 |
--- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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4 |
+++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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5 |
@@ -34,6 +34,7 @@
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6 |
/* Driver local definitions. */
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7 |
/*===========================================================================*/
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8 |
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9 |
+#if STM32_I2C_I2C1_USE_DMA
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10 |
#define I2C1_RX_DMA_CHANNEL \
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11 |
STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_CHN)
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13 |
@@ -41,7 +42,9 @@
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14 |
#define I2C1_TX_DMA_CHANNEL \
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15 |
STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_CHN)
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17 |
+#endif
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18 |
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19 |
+#if STM32_I2C_I2C2_USE_DMA
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20 |
#define I2C2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_CHN)
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23 |
@@ -49,7 +52,9 @@
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24 |
#define I2C2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_CHN)
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27 |
+#endif
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28 |
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29 |
+#if STM32_I2C_I2C3_USE_DMA
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30 |
#define I2C3_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \
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STM32_I2C3_RX_DMA_CHN)
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@@ -57,6 +62,7 @@
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#define I2C3_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_CHN)
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+#endif
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38 |
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/*===========================================================================*/
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40 |
/* Driver constants. */
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41 |
@@ -72,6 +78,20 @@
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42 |
#define I2C_EV6_MASTER_REC_MODE_SELECTED \
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43 |
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))
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44 |
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45 |
+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_RXNE))
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47 |
+
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48 |
+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP \
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+ ((uint32_t)(I2C_SR1_RXNE))
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50 |
+
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51 |
+#define I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | \
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+ I2C_SR1_BTF | I2C_SR1_RXNE))
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+
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55 |
+#define I2C_EV8_MASTER_BYTE_TRANSMITTING \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)<< 16) | \
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+ I2C_SR1_TXE))
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+
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \
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((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \
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I2C_SR1_BTF | I2C_SR1_TXE))
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@@ -129,8 +149,24 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
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dp->SR1 = 0;
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64 |
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65 |
/* Stops the associated DMA streams.*/
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- dmaStreamDisable(i2cp->dmatx);
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- dmaStreamDisable(i2cp->dmarx);
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+#if STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA
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+ if (&I2CD1 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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+#if STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA
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75 |
+ if (&I2CD2 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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+#if STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA
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+ if (&I2CD3 == i2cp) {
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+ dmaStreamDisable(i2cp->dmatx);
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+ dmaStreamDisable(i2cp->dmarx);
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+ }
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+#endif
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}
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87 |
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88 |
/**
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@@ -236,13 +272,17 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {
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90 |
}
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91 |
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92 |
/**
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- * @brief I2C shared ISR code.
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+ * @brief I2C shared ISR code for DMA access.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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-static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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101 |
+#if (STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA) || \
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+ (STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA) || \
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+ (STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA) || \
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+ defined(__DOXYGEN__)
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+static void i2c_lld_serve_event_interrupt_dma(I2CDriver *i2cp) {
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106 |
I2C_TypeDef *dp = i2cp->i2c;
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uint32_t regSR2 = dp->SR2;
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uint32_t event = dp->SR1;
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@@ -252,7 +292,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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110 |
done by the DMA.*/
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111 |
switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
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112 |
case I2C_EV5_MASTER_MODE_SELECT:
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113 |
- if ((i2cp->addr >> 8) > 0) {
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+ if ((i2cp->addr >> 8) > 0) {
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/* 10-bit address: 1 1 1 1 0 X X R/W */
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116 |
dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
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117 |
} else {
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118 |
@@ -293,6 +333,140 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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119 |
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
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120 |
(void)dp->SR2;
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121 |
}
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122 |
+#endif /* any I2CDx uses DMA mode */
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+
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124 |
+/**
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125 |
+ * @brief I2C shared ISR code for non-DMA access.
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126 |
+ *
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127 |
+ * @param[in] i2cp pointer to the @p I2CDriver object
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128 |
+ *
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129 |
+ * @notapi
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130 |
+ */
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131 |
+#if (STM32_I2C_USE_I2C1 && !STM32_I2C_I2C1_USE_DMA) || \
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+ (STM32_I2C_USE_I2C2 && !STM32_I2C_I2C2_USE_DMA) || \
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133 |
+ (STM32_I2C_USE_I2C3 && !STM32_I2C_I2C3_USE_DMA) || \
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134 |
+ defined(__DOXYGEN__)
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135 |
+static void i2c_lld_serve_event_interrupt_isr(I2CDriver *i2cp) {
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136 |
+ I2C_TypeDef *dp = i2cp->i2c;
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137 |
+ uint32_t regSR2 = dp->SR2;
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138 |
+ uint32_t event = dp->SR1;
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139 |
+
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+ switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
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+ case I2C_EV5_MASTER_MODE_SELECT:
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142 |
+ dp->CR2 |= I2C_CR2_ITBUFEN;
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143 |
+ dp->DR = i2cp->addr;
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+ break;
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145 |
+ case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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146 |
+ (void)dp->SR2; // clear ADDR flag
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147 |
+ /* EV8_1 */
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148 |
+ dp->DR = *(i2cp->txbuf);
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+
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150 |
+ ++i2cp->txbuf;
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+ --i2cp->txbytes;
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+
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153 |
+ /* if N == 1, skip the I2C_EV8_MASTER_BYTE_TRANSMITTING event
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154 |
+ * but enter I2C_EV8_2_MASTER_BYTE_TRANSMITTED next */
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155 |
+ if (i2cp->txbytes == 0) {
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156 |
+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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158 |
+ break;
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159 |
+ case I2C_EV6_MASTER_REC_MODE_SELECTED:
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160 |
+ switch (i2cp->rxbytes) {
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161 |
+ case 1:
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162 |
+ dp->CR1 &= ~I2C_CR1_ACK;
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163 |
+ (void)dp->SR2; // clear ADDR flag
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+ dp->CR1 |= I2C_CR1_STOP;
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+ break;
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+ case 2:
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167 |
+ (void)dp->SR2; // clear ADDR flag
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168 |
+ /* EV6_1 */
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+ dp->CR1 |= I2C_CR1_POS;
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+ dp->CR1 &= ~I2C_CR1_ACK;
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171 |
+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ break;
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+ case 3: /* N == 3 is a very special case, since EV7 is completely skipped */
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174 |
+ (void)dp->SR2; // clear ADDR flag
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175 |
+ /* Disable the I2C_EV7_MASTER_REC_BYTE_RECEIVED event
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176 |
+ * but enter I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP next */
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177 |
+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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178 |
+ break;
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179 |
+ default: /* N > 2 */
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180 |
+ (void)dp->SR2; // clear ADDR flag
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181 |
+ break;
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182 |
+ }
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183 |
+ break;
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184 |
+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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185 |
+ if (i2cp->rxbytes > 3) {
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186 |
+ *(i2cp->rxbuf) = dp->DR;
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187 |
+ ++i2cp->rxbuf;
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188 |
+ --i2cp->rxbytes;
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189 |
+ }
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190 |
+ if (i2cp->rxbytes == 3) {
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191 |
+ /* Disable this event for DataN-2, but force into event
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192 |
+ * I2C_EV7_2_EV7_3_MASTER_REC_BYTE_RECEIVED_QUEUED by not reading dp->DR. */
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193 |
+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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194 |
+ }
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195 |
+ break;
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196 |
+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP:
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197 |
+ osalDbgAssert(i2cp->rxbytes == 1, "more than 1 byte to be received");
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198 |
+ *(i2cp->rxbuf) = dp->DR;
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199 |
+ --i2cp->rxbytes;
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200 |
+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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201 |
+ _i2c_wakeup_isr(i2cp);
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202 |
+ break;
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203 |
+ case I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED:
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204 |
+ if (i2cp->rxbytes == 3) {
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205 |
+ /* EV7_2 (N > 2) */
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206 |
+ dp->CR1 &= ~I2C_CR1_ACK;
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207 |
+ *(i2cp->rxbuf) = dp->DR;
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208 |
+ ++i2cp->rxbuf;
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209 |
+ dp->CR1 |= I2C_CR1_STOP;
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210 |
+ *(i2cp->rxbuf) = dp->DR;
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211 |
+ ++i2cp->rxbuf;
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212 |
+ i2cp->rxbytes -= 2;
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213 |
+ /* enable I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP event */
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214 |
+ dp->CR2 |= I2C_CR2_ITBUFEN;
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215 |
+ } else {
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216 |
+ /* EV7_3 (N == 2) */
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217 |
+ dp->CR1 |= I2C_CR1_STOP;
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218 |
+ *(i2cp->rxbuf) = dp->DR;
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219 |
+ ++i2cp->rxbuf;
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220 |
+ *(i2cp->rxbuf) = dp->DR;
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221 |
+ i2cp->rxbytes -= 2;
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222 |
+
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223 |
+ dp->CR1 &= ~I2C_CR1_POS;
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224 |
+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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225 |
+
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226 |
+ _i2c_wakeup_isr(i2cp);
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227 |
+ }
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228 |
+ break;
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229 |
+ case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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230 |
+ dp->DR = *(i2cp->txbuf);
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231 |
+ ++i2cp->txbuf;
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232 |
+ --i2cp->txbytes;
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233 |
+
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234 |
+ /* if this was the last byte, ensure that this event is not entered again */
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235 |
+ if (i2cp->txbytes == 0) {
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236 |
+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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237 |
+ }
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238 |
+ break;
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239 |
+ case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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240 |
+ if (i2cp->rxbytes > 0) {
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241 |
+ /* start "read after write" operation (LSB of address = 1 => read) */
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242 |
+ i2cp->addr |= 0x01;
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243 |
+ dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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244 |
+ } else {
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245 |
+ dp->CR1 |= I2C_CR1_STOP;
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246 |
+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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247 |
+ _i2c_wakeup_isr(i2cp);
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248 |
+ }
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249 |
+ break;
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250 |
+ default:
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251 |
+ osalDbgAssert(i2cp->rxbytes != 1, "more than 1 byte to be received");
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252 |
+ break;
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253 |
+ }
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254 |
+}
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255 |
+#endif /* any I2CDx uses non-DMA mode */
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256 |
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257 |
/**
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258 |
* @brief DMA RX end IRQ handler.
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259 |
@@ -302,6 +476,10 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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260 |
*
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261 |
* @notapi
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262 |
*/
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263 |
+#if (STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA) || \
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264 |
+ (STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA) || \
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265 |
+ (STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA) || \
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266 |
+ defined(__DOXYGEN__)
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267 |
static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
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268 |
I2C_TypeDef *dp = i2cp->i2c;
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269 |
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270 |
@@ -347,6 +525,7 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
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271 |
of R/W transaction itself.*/
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272 |
dp->CR2 |= I2C_CR2_ITEVTEN;
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273 |
}
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274 |
+#endif /* any I2CDx uses DMA mode */
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275 |
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276 |
/**
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277 |
* @brief I2C error handler.
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278 |
@@ -359,8 +538,24 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
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279 |
static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
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280 |
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281 |
/* Clears interrupt flags just to be safe.*/
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282 |
- dmaStreamDisable(i2cp->dmatx);
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283 |
- dmaStreamDisable(i2cp->dmarx);
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284 |
+#if STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA
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285 |
+ if (&I2CD1 == i2cp) {
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286 |
+ dmaStreamDisable(i2cp->dmatx);
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287 |
+ dmaStreamDisable(i2cp->dmarx);
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|
288 |
+ }
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|
289 |
+#endif
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290 |
+#if STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA
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291 |
+ if (&I2CD2 == i2cp) {
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292 |
+ dmaStreamDisable(i2cp->dmatx);
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293 |
+ dmaStreamDisable(i2cp->dmarx);
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|
294 |
+ }
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|
295 |
+#endif
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|
296 |
+#if STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA
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|
297 |
+ if (&I2CD3 == i2cp) {
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|
298 |
+ dmaStreamDisable(i2cp->dmatx);
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299 |
+ dmaStreamDisable(i2cp->dmarx);
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|
300 |
+ }
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|
301 |
+#endif
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302 |
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303 |
i2cp->errors = I2C_NO_ERROR;
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304 |
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305 |
@@ -407,7 +602,11 @@ OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
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306 |
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|
307 |
OSAL_IRQ_PROLOGUE();
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|
308 |
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|
309 |
- i2c_lld_serve_event_interrupt(&I2CD1);
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|
310 |
+#if STM32_I2C_I2C1_USE_DMA
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|
311 |
+ i2c_lld_serve_event_interrupt_dma(&I2CD1);
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|
312 |
+#else
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|
313 |
+ i2c_lld_serve_event_interrupt_isr(&I2CD1);
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|
314 |
+#endif
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|
315 |
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|
316 |
OSAL_IRQ_EPILOGUE();
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|
317 |
}
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|
318 |
@@ -437,7 +636,11 @@ OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
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|
319 |
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|
320 |
OSAL_IRQ_PROLOGUE();
|
|
321 |
|
|
322 |
- i2c_lld_serve_event_interrupt(&I2CD2);
|
|
323 |
+#if STM32_I2C_I2C2_USE_DMA
|
|
324 |
+ i2c_lld_serve_event_interrupt_dma(&I2CD2);
|
|
325 |
+#else
|
|
326 |
+ i2c_lld_serve_event_interrupt_isr(&I2CD2);
|
|
327 |
+#endif
|
|
328 |
|
|
329 |
OSAL_IRQ_EPILOGUE();
|
|
330 |
}
|
|
331 |
@@ -469,7 +672,11 @@ OSAL_IRQ_HANDLER(STM32_I2C3_EVENT_HANDLER) {
|
|
332 |
|
|
333 |
OSAL_IRQ_PROLOGUE();
|
|
334 |
|
|
335 |
- i2c_lld_serve_event_interrupt(&I2CD3);
|
|
336 |
+#if STM32_I2C_I2C3_USE_DMA
|
|
337 |
+ i2c_lld_serve_event_interrupt_dma(&I2CD3);
|
|
338 |
+#else
|
|
339 |
+ i2c_lld_serve_event_interrupt_isr(&I2CD3);
|
|
340 |
+#endif
|
|
341 |
|
|
342 |
OSAL_IRQ_EPILOGUE();
|
|
343 |
}
|
|
344 |
@@ -506,24 +713,30 @@ void i2c_lld_init(void) {
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|
345 |
i2cObjectInit(&I2CD1);
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|
346 |
I2CD1.thread = NULL;
|
|
347 |
I2CD1.i2c = I2C1;
|
|
348 |
+#if STM32_I2C_I2C1_USE_DMA
|
|
349 |
I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
|
|
350 |
I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
|
|
351 |
+#endif
|
|
352 |
#endif /* STM32_I2C_USE_I2C1 */
|
|
353 |
|
|
354 |
#if STM32_I2C_USE_I2C2
|
|
355 |
i2cObjectInit(&I2CD2);
|
|
356 |
I2CD2.thread = NULL;
|
|
357 |
I2CD2.i2c = I2C2;
|
|
358 |
+#if STM32_I2C_I2C2_USE_DMA
|
|
359 |
I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
|
|
360 |
I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
|
|
361 |
+#endif
|
|
362 |
#endif /* STM32_I2C_USE_I2C2 */
|
|
363 |
|
|
364 |
#if STM32_I2C_USE_I2C3
|
|
365 |
i2cObjectInit(&I2CD3);
|
|
366 |
I2CD3.thread = NULL;
|
|
367 |
I2CD3.i2c = I2C3;
|
|
368 |
+#if STM32_I2C_I2C3_USE_DMA
|
|
369 |
I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
|
|
370 |
I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
|
|
371 |
+#endif
|
|
372 |
#endif /* STM32_I2C_USE_I2C3 */
|
|
373 |
}
|
|
374 |
|
|
375 |
@@ -540,20 +753,24 @@ void i2c_lld_start(I2CDriver *i2cp) {
|
|
376 |
/* If in stopped state then enables the I2C and DMA clocks.*/
|
|
377 |
if (i2cp->state == I2C_STOP) {
|
|
378 |
|
|
379 |
- i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
380 |
- STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
381 |
- STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
382 |
- STM32_DMA_CR_DIR_M2P;
|
|
383 |
- i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
384 |
- STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
385 |
- STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
386 |
- STM32_DMA_CR_DIR_P2M;
|
|
387 |
-
|
|
388 |
#if STM32_I2C_USE_I2C1
|
|
389 |
if (&I2CD1 == i2cp) {
|
|
390 |
+#if STM32_I2C_I2C1_USE_DMA
|
|
391 |
bool b;
|
|
392 |
|
|
393 |
+ i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
394 |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
395 |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
396 |
+ STM32_DMA_CR_DIR_M2P;
|
|
397 |
+ i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
398 |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
399 |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
400 |
+ STM32_DMA_CR_DIR_P2M;
|
|
401 |
+#endif
|
|
402 |
+
|
|
403 |
rccResetI2C1();
|
|
404 |
+
|
|
405 |
+#if STM32_I2C_I2C1_USE_DMA
|
|
406 |
b = dmaStreamAllocate(i2cp->dmarx,
|
|
407 |
STM32_I2C_I2C1_IRQ_PRIORITY,
|
|
408 |
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
|
|
409 |
@@ -564,22 +781,52 @@ void i2c_lld_start(I2CDriver *i2cp) {
|
|
410 |
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
|
|
411 |
(void *)i2cp);
|
|
412 |
osalDbgAssert(!b, "stream already allocated");
|
|
413 |
+#endif
|
|
414 |
+
|
|
415 |
rccEnableI2C1(true);
|
|
416 |
nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
|
|
417 |
nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
|
|
418 |
|
|
419 |
+#if STM32_I2C_I2C1_USE_DMA
|
|
420 |
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
|
|
421 |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
|
|
422 |
i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
|
|
423 |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
|
|
424 |
+
|
|
425 |
+ /* I2C registers pointed by the DMA.*/
|
|
426 |
+ dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR);
|
|
427 |
+ dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR);
|
|
428 |
+#endif
|
|
429 |
+
|
|
430 |
+ /* Reset i2c peripheral.*/
|
|
431 |
+ dp->CR1 = I2C_CR1_SWRST;
|
|
432 |
+ dp->CR1 = 0;
|
|
433 |
+#if STM32_I2C_I2C1_USE_DMA
|
|
434 |
+ dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN;
|
|
435 |
+#else
|
|
436 |
+ dp->CR2 = I2C_CR2_ITERREN;
|
|
437 |
+#endif
|
|
438 |
}
|
|
439 |
#endif /* STM32_I2C_USE_I2C1 */
|
|
440 |
|
|
441 |
#if STM32_I2C_USE_I2C2
|
|
442 |
if (&I2CD2 == i2cp) {
|
|
443 |
+#if STM32_I2C_I2C2_USE_DMA
|
|
444 |
bool b;
|
|
445 |
|
|
446 |
+ i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
447 |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
448 |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
449 |
+ STM32_DMA_CR_DIR_M2P;
|
|
450 |
+ i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
|
451 |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
|
|
452 |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
|
|
453 |
+ STM32_DMA_CR_DIR_P2M;
|
|
454 |
+#endif
|
|
455 |
+
|
|
456 |
rccResetI2C2();
|
|
457 |
+
|
|
458 |
+#if STM32_I2C_I2C2_USE_DMA
|
|
459 |
b = dmaStreamAllocate(i2cp->dmarx,
|
|
460 |
STM32_I2C_I2C2_IRQ_PRIORITY,
|
|