Revision 340f2bdf
| bootloader/AMiRo-BLT | ||
|---|---|---|
| 1 |
Subproject commit 591c0fd3a0677d69b3e1c89fa9e202797cb04a36 |
|
| 1 |
Subproject commit 2b9a14a2588e910d0e7d6bc3f77975d9ea70a6c8 |
|
| modules/PowerManagement_1-1/board.c | ||
|---|---|---|
| 47 | 47 |
* @param[in] odr OD register configuration. |
| 48 | 48 |
* @param[in] afrl AF register (low) configuration. |
| 49 | 49 |
* @param[in] afrh AF register (high ) configuration. |
| 50 |
* @param[in] ignmask Mask to ignore individual pads. |
|
| 51 | 50 |
*/ |
| 52 | 51 |
static void _gpio_init(stm32_gpio_t *gpiop, |
| 53 | 52 |
const uint32_t moder, |
| ... | ... | |
| 56 | 55 |
const uint32_t pupdr, |
| 57 | 56 |
const uint32_t odr, |
| 58 | 57 |
const uint32_t afrl, |
| 59 |
const uint32_t afrh, |
|
| 60 |
const uint16_t ignmask) {
|
|
| 61 |
|
|
| 62 |
const uint8_t lut[] = {0x00, 0x03, 0x0C, 0x0F,
|
|
| 63 |
0x30, 0x33, 0x3C, 0x3F, |
|
| 64 |
0xC0, 0xC3, 0xCC, 0xCF, |
|
| 65 |
0xF0, 0xF3, 0xFC, 0xFF}; |
|
| 66 |
|
|
| 67 |
/* some bit-magic to fan out the mask */ |
|
| 68 |
const uint32_t ignmask2 = (lut[(ignmask >> 12) ] << 24) | |
|
| 69 |
(lut[(ignmask >> 8) & 0x0F] << 16) | |
|
| 70 |
(lut[(ignmask >> 4) & 0x0F] << 8) | |
|
| 71 |
(lut[(ignmask ) & 0x0F]); |
|
| 72 |
const uint32_t ignmask4_low = (lut[lut[(ignmask >> 6) & 0x03]] << 24) | |
|
| 73 |
(lut[lut[(ignmask >> 4) & 0x03]] << 16) | |
|
| 74 |
(lut[lut[(ignmask >> 2) & 0x03]] << 8) | |
|
| 75 |
(lut[lut[(ignmask ) & 0x03]]); |
|
| 76 |
const uint32_t ignmask4_high = (lut[lut[(ignmask >> 14) ]] << 24) | |
|
| 77 |
(lut[lut[(ignmask >> 12) & 0x03]] << 16) | |
|
| 78 |
(lut[lut[(ignmask >> 10) & 0x03]] << 8) | |
|
| 79 |
(lut[lut[(ignmask >> 8) & 0x03]]); |
|
| 80 |
|
|
| 81 |
gpiop->OTYPER = (gpiop->OTYPER & ignmask ) | (otyper & ~ignmask ); |
|
| 82 |
gpiop->OSPEEDR = (gpiop->OSPEEDR & ignmask2 ) | (ospeedr & ~ignmask2 ); |
|
| 83 |
gpiop->PUPDR = (gpiop->PUPDR & ignmask2 ) | (pupdr & ~ignmask2 ); |
|
| 84 |
gpiop->ODR = (gpiop->ODR & ignmask ) | (odr & ~ignmask ); |
|
| 85 |
gpiop->AFRL = (gpiop->AFRL & ignmask4_low ) | (afrl & ~ignmask4_low ); |
|
| 86 |
gpiop->AFRH = (gpiop->AFRH & ignmask4_high) | (afrh & ~ignmask4_high); |
|
| 87 |
gpiop->MODER = (gpiop->MODER & ignmask2 ) | (moder & ~ignmask2 ); |
|
| 58 |
const uint32_t afrh) {
|
|
| 59 |
|
|
| 60 |
gpiop->OTYPER = otyper; |
|
| 61 |
gpiop->OSPEEDR = ospeedr; |
|
| 62 |
gpiop->PUPDR = pupdr; |
|
| 63 |
gpiop->ODR = odr; |
|
| 64 |
gpiop->AFRL = afrl; |
|
| 65 |
gpiop->AFRH = afrh; |
|
| 66 |
gpiop->MODER = moder; |
|
| 67 |
|
|
| 68 |
return; |
|
| 88 | 69 |
} |
| 89 | 70 |
|
| 90 | 71 |
/** |
| ... | ... | |
| 99 | 80 |
|
| 100 | 81 |
/* Initializing all the defined GPIO ports.*/ |
| 101 | 82 |
#if STM32_HAS_GPIOA |
| 102 |
_gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_IGNORE);
|
|
| 83 |
_gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH); |
|
| 103 | 84 |
#endif |
| 104 | 85 |
#if STM32_HAS_GPIOB |
| 105 |
_gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_IGNORE);
|
|
| 86 |
_gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH); |
|
| 106 | 87 |
#endif |
| 107 | 88 |
#if STM32_HAS_GPIOC |
| 108 |
_gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_IGNORE);
|
|
| 89 |
_gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH); |
|
| 109 | 90 |
#endif |
| 110 | 91 |
#if STM32_HAS_GPIOD |
| 111 |
_gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_IGNORE);
|
|
| 92 |
_gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH); |
|
| 112 | 93 |
#endif |
| 113 | 94 |
#if STM32_HAS_GPIOE |
| 114 |
_gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_IGNORE);
|
|
| 95 |
_gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH); |
|
| 115 | 96 |
#endif |
| 116 | 97 |
#if STM32_HAS_GPIOF |
| 117 |
_gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_IGNORE);
|
|
| 98 |
_gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH); |
|
| 118 | 99 |
#endif |
| 119 | 100 |
#if STM32_HAS_GPIOG |
| 120 |
_gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_IGNORE);
|
|
| 101 |
_gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH); |
|
| 121 | 102 |
#endif |
| 122 | 103 |
#if STM32_HAS_GPIOH |
| 123 |
_gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_IGNORE);
|
|
| 104 |
_gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH); |
|
| 124 | 105 |
#endif |
| 125 | 106 |
#if STM32_HAS_GPIOI |
| 126 |
_gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_IGNORE);
|
|
| 107 |
_gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRL);
|
|
| 127 | 108 |
#endif |
| 128 | 109 |
#if STM32_HAS_GPIOJ |
| 129 |
_gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_IGNORE);
|
|
| 110 |
_gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH); |
|
| 130 | 111 |
#endif |
| 131 | 112 |
#if STM32_HAS_GPIOK |
| 132 |
_gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_IGNORE);
|
|
| 113 |
_gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH); |
|
| 133 | 114 |
#endif |
| 134 | 115 |
} |
| 135 | 116 |
|
| modules/PowerManagement_1-1/board.h | ||
|---|---|---|
| 313 | 313 |
* in the initialization code. |
| 314 | 314 |
* Please refer to the STM32 Reference Manual for details. |
| 315 | 315 |
*/ |
| 316 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 317 | 316 |
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
| 318 | 317 |
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
| 319 | 318 |
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
| ... | ... | |
| 351 | 350 |
* PA14 - SWCLK (alternate 0 pushpull floating) |
| 352 | 351 |
* PA15 - SYS_SPI_SS1_N (input floating) |
| 353 | 352 |
*/ |
| 354 |
#define VAL_GPIOA_IGNORE 0 |
|
| 355 | 353 |
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP) | \ |
| 356 | 354 |
PIN_MODE_INPUT(GPIOA_PIN1) | \ |
| 357 | 355 |
PIN_MODE_INPUT(GPIOA_SYS_UART_TX) | \ |
| ... | ... | |
| 469 | 467 |
* PB14 - BT_CTS (inout floating) |
| 470 | 468 |
* PB15 - SYS_UART_UP (output opendrain high) |
| 471 | 469 |
*/ |
| 472 |
#define VAL_GPIOB_IGNORE (PIN_IGNORE(GPIOB_POWER_EN) | \ |
|
| 473 |
PIN_IGNORE(GPIOB_SYS_UART_DN) | \ |
|
| 474 |
PIN_IGNORE(GPIOB_LED) | \ |
|
| 475 |
PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
|
| 476 | 470 |
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_IR_INT1_N) | \ |
| 477 | 471 |
PIN_MODE_ANALOG(GPIOB_VSYS_SENSE) | \ |
| 478 | 472 |
PIN_MODE_OUTPUT(GPIOB_POWER_EN) | \ |
| ... | ... | |
| 590 | 584 |
* PC14 - SYS_WARMRST_N (output opendrain high) |
| 591 | 585 |
* PC15 - BT_RST (output opendrain high) |
| 592 | 586 |
*/ |
| 593 |
#define VAL_GPIOC_IGNORE (PIN_IGNORE(GPIOC_CHARGE_EN1_N) | \ |
|
| 594 |
PIN_IGNORE(GPIOC_SYS_INT_N) | \ |
|
| 595 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 596 | 587 |
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_CHARGE_STAT1A) | \ |
| 597 | 588 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATLOW1) | \ |
| 598 | 589 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATGD1_N) | \ |
| ... | ... | |
| 710 | 701 |
* PD14 - PIN14 (input floating) |
| 711 | 702 |
* PD15 - PIN15 (input floating) |
| 712 | 703 |
*/ |
| 713 |
#define VAL_GPIOD_IGNORE (PIN_IGNORE(GPIOD_CHARGE_EN2_N)) & 0 |
|
| 714 | 704 |
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ |
| 715 | 705 |
PIN_MODE_INPUT(GPIOD_PIN1) | \ |
| 716 | 706 |
PIN_MODE_OUTPUT(GPIOD_CHARGE_EN2_N) | \ |
| ... | ... | |
| 828 | 818 |
* PE14 - PIN14 (input floating) |
| 829 | 819 |
* PE15 - PIN15 (input floating) |
| 830 | 820 |
*/ |
| 831 |
#define VAL_GPIOE_IGNORE 0 |
|
| 832 | 821 |
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ |
| 833 | 822 |
PIN_MODE_INPUT(GPIOE_PIN1) | \ |
| 834 | 823 |
PIN_MODE_INPUT(GPIOE_PIN2) | \ |
| ... | ... | |
| 946 | 935 |
* PF14 - PIN14 (input floating) |
| 947 | 936 |
* PF15 - PIN15 (input floating) |
| 948 | 937 |
*/ |
| 949 |
#define VAL_GPIOF_IGNORE 0 |
|
| 950 | 938 |
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ |
| 951 | 939 |
PIN_MODE_INPUT(GPIOF_PIN1) | \ |
| 952 | 940 |
PIN_MODE_INPUT(GPIOF_PIN2) | \ |
| ... | ... | |
| 1064 | 1052 |
* PG14 - PIN14 (input floating) |
| 1065 | 1053 |
* PG15 - PIN15 (input floating) |
| 1066 | 1054 |
*/ |
| 1067 |
#define VAL_GPIOG_IGNORE 0 |
|
| 1068 | 1055 |
#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ |
| 1069 | 1056 |
PIN_MODE_INPUT(GPIOG_PIN1) | \ |
| 1070 | 1057 |
PIN_MODE_INPUT(GPIOG_PIN2) | \ |
| ... | ... | |
| 1182 | 1169 |
* PH14 - PIN14 (input floating) |
| 1183 | 1170 |
* PH15 - PIN15 (input floating) |
| 1184 | 1171 |
*/ |
| 1185 |
#define VAL_GPIOH_IGNORE 0 |
|
| 1186 | 1172 |
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ |
| 1187 | 1173 |
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ |
| 1188 | 1174 |
PIN_MODE_INPUT(GPIOH_PIN2) | \ |
| ... | ... | |
| 1300 | 1286 |
* PI14 - PIN14 (input floating) |
| 1301 | 1287 |
* PI15 - PIN15 (input floating) |
| 1302 | 1288 |
*/ |
| 1303 |
#define VAL_GPIOI_IGNORE 0 |
|
| 1304 | 1289 |
#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ |
| 1305 | 1290 |
PIN_MODE_INPUT(GPIOI_PIN1) | \ |
| 1306 | 1291 |
PIN_MODE_INPUT(GPIOI_PIN2) | \ |
| modules/PowerManagement_1-1/module.h | ||
|---|---|---|
| 246 | 246 |
extern ROMCONST apalControlGpio_t moduleGpioGaugeBatGd1; |
| 247 | 247 |
|
| 248 | 248 |
/** |
| 249 |
* @brief CHARG_EN1 output signal GPIO. |
|
| 249 |
* @brief CHARGE_EN1 output signal GPIO.
|
|
| 250 | 250 |
*/ |
| 251 | 251 |
extern ROMCONST apalControlGpio_t moduleGpioChargeEn1; |
| 252 | 252 |
|
| modules/PowerManagement_1-2/board.c | ||
|---|---|---|
| 47 | 47 |
* @param[in] odr OD register configuration. |
| 48 | 48 |
* @param[in] afrl AF register (low) configuration. |
| 49 | 49 |
* @param[in] afrh AF register (high ) configuration. |
| 50 |
* @param[in] ignmask Mask to ignore individual pads. |
|
| 51 | 50 |
*/ |
| 52 | 51 |
static void _gpio_init(stm32_gpio_t *gpiop, |
| 53 | 52 |
const uint32_t moder, |
| ... | ... | |
| 56 | 55 |
const uint32_t pupdr, |
| 57 | 56 |
const uint32_t odr, |
| 58 | 57 |
const uint32_t afrl, |
| 59 |
const uint32_t afrh, |
|
| 60 |
const uint16_t ignmask) {
|
|
| 61 |
|
|
| 62 |
const uint8_t lut[] = {0x00, 0x03, 0x0C, 0x0F,
|
|
| 63 |
0x30, 0x33, 0x3C, 0x3F, |
|
| 64 |
0xC0, 0xC3, 0xCC, 0xCF, |
|
| 65 |
0xF0, 0xF3, 0xFC, 0xFF}; |
|
| 66 |
|
|
| 67 |
/* some bit-magic to fan out the mask */ |
|
| 68 |
const uint32_t ignmask2 = (lut[(ignmask >> 12) ] << 24) | |
|
| 69 |
(lut[(ignmask >> 8) & 0x0F] << 16) | |
|
| 70 |
(lut[(ignmask >> 4) & 0x0F] << 8) | |
|
| 71 |
(lut[(ignmask ) & 0x0F]); |
|
| 72 |
const uint32_t ignmask4_low = (lut[lut[(ignmask >> 6) & 0x03]] << 24) | |
|
| 73 |
(lut[lut[(ignmask >> 4) & 0x03]] << 16) | |
|
| 74 |
(lut[lut[(ignmask >> 2) & 0x03]] << 8) | |
|
| 75 |
(lut[lut[(ignmask ) & 0x03]]); |
|
| 76 |
const uint32_t ignmask4_high = (lut[lut[(ignmask >> 14) ]] << 24) | |
|
| 77 |
(lut[lut[(ignmask >> 12) & 0x03]] << 16) | |
|
| 78 |
(lut[lut[(ignmask >> 10) & 0x03]] << 8) | |
|
| 79 |
(lut[lut[(ignmask >> 8) & 0x03]]); |
|
| 80 |
|
|
| 81 |
gpiop->OTYPER = (gpiop->OTYPER & ignmask ) | (otyper & ~ignmask ); |
|
| 82 |
gpiop->OSPEEDR = (gpiop->OSPEEDR & ignmask2 ) | (ospeedr & ~ignmask2 ); |
|
| 83 |
gpiop->PUPDR = (gpiop->PUPDR & ignmask2 ) | (pupdr & ~ignmask2 ); |
|
| 84 |
gpiop->ODR = (gpiop->ODR & ignmask ) | (odr & ~ignmask ); |
|
| 85 |
gpiop->AFRL = (gpiop->AFRL & ignmask4_low ) | (afrl & ~ignmask4_low ); |
|
| 86 |
gpiop->AFRH = (gpiop->AFRH & ignmask4_high) | (afrh & ~ignmask4_high); |
|
| 87 |
gpiop->MODER = (gpiop->MODER & ignmask2 ) | (moder & ~ignmask2 ); |
|
| 58 |
const uint32_t afrh) {
|
|
| 59 |
|
|
| 60 |
gpiop->OTYPER = otyper; |
|
| 61 |
gpiop->OSPEEDR = ospeedr; |
|
| 62 |
gpiop->PUPDR = pupdr; |
|
| 63 |
gpiop->ODR = odr; |
|
| 64 |
gpiop->AFRL = afrl; |
|
| 65 |
gpiop->AFRH = afrh; |
|
| 66 |
gpiop->MODER = moder; |
|
| 67 |
|
|
| 68 |
return; |
|
| 88 | 69 |
} |
| 89 | 70 |
|
| 90 | 71 |
/** |
| ... | ... | |
| 99 | 80 |
|
| 100 | 81 |
/* Initializing all the defined GPIO ports.*/ |
| 101 | 82 |
#if STM32_HAS_GPIOA |
| 102 |
_gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_IGNORE);
|
|
| 83 |
_gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH); |
|
| 103 | 84 |
#endif |
| 104 | 85 |
#if STM32_HAS_GPIOB |
| 105 |
_gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_IGNORE);
|
|
| 86 |
_gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH); |
|
| 106 | 87 |
#endif |
| 107 | 88 |
#if STM32_HAS_GPIOC |
| 108 |
_gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_IGNORE);
|
|
| 89 |
_gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH); |
|
| 109 | 90 |
#endif |
| 110 | 91 |
#if STM32_HAS_GPIOD |
| 111 |
_gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_IGNORE);
|
|
| 92 |
_gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH); |
|
| 112 | 93 |
#endif |
| 113 | 94 |
#if STM32_HAS_GPIOE |
| 114 |
_gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_IGNORE);
|
|
| 95 |
_gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH); |
|
| 115 | 96 |
#endif |
| 116 | 97 |
#if STM32_HAS_GPIOF |
| 117 |
_gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_IGNORE);
|
|
| 98 |
_gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH); |
|
| 118 | 99 |
#endif |
| 119 | 100 |
#if STM32_HAS_GPIOG |
| 120 |
_gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_IGNORE);
|
|
| 101 |
_gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH); |
|
| 121 | 102 |
#endif |
| 122 | 103 |
#if STM32_HAS_GPIOH |
| 123 |
_gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_IGNORE);
|
|
| 104 |
_gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH); |
|
| 124 | 105 |
#endif |
| 125 | 106 |
#if STM32_HAS_GPIOI |
| 126 |
_gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_IGNORE);
|
|
| 107 |
_gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRL);
|
|
| 127 | 108 |
#endif |
| 128 | 109 |
#if STM32_HAS_GPIOJ |
| 129 |
_gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_IGNORE);
|
|
| 110 |
_gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH); |
|
| 130 | 111 |
#endif |
| 131 | 112 |
#if STM32_HAS_GPIOK |
| 132 |
_gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_IGNORE);
|
|
| 113 |
_gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH); |
|
| 133 | 114 |
#endif |
| 134 | 115 |
} |
| 135 | 116 |
|
| modules/PowerManagement_1-2/board.h | ||
|---|---|---|
| 314 | 314 |
* in the initialization code. |
| 315 | 315 |
* Please refer to the STM32 Reference Manual for details. |
| 316 | 316 |
*/ |
| 317 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 318 | 317 |
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
| 319 | 318 |
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
| 320 | 319 |
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
| ... | ... | |
| 352 | 351 |
* PA14 - SWCLK (alternate 0 pushpull floating) |
| 353 | 352 |
* PA15 - SYS_SPI_SS1_N (input floating) |
| 354 | 353 |
*/ |
| 355 |
#define VAL_GPIOA_IGNORE 0 |
|
| 356 | 354 |
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP) | \ |
| 357 | 355 |
PIN_MODE_INPUT(GPIOA_SWITCH_STATUS_N) | \ |
| 358 | 356 |
PIN_MODE_INPUT(GPIOA_SYS_UART_TX) | \ |
| ... | ... | |
| 470 | 468 |
* PB14 - BT_CTS (inout floating) |
| 471 | 469 |
* PB15 - SYS_UART_UP (output opendrain high) |
| 472 | 470 |
*/ |
| 473 |
#define VAL_GPIOB_IGNORE (PIN_IGNORE(GPIOB_POWER_EN) | \ |
|
| 474 |
PIN_IGNORE(GPIOB_SYS_UART_DN) | \ |
|
| 475 |
PIN_IGNORE(GPIOB_LED) | \ |
|
| 476 |
PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
|
| 477 | 471 |
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_IR_INT1_N) | \ |
| 478 | 472 |
PIN_MODE_ANALOG(GPIOB_VSYS_SENSE) | \ |
| 479 | 473 |
PIN_MODE_OUTPUT(GPIOB_POWER_EN) | \ |
| ... | ... | |
| 591 | 585 |
* PC14 - SYS_WARMRST_N (output opendrain high) |
| 592 | 586 |
* PC15 - BT_RST (output opendrain high) |
| 593 | 587 |
*/ |
| 594 |
#define VAL_GPIOC_IGNORE (PIN_IGNORE(GPIOC_CHARGE_EN1_N) | \ |
|
| 595 |
PIN_IGNORE(GPIOC_SYS_INT_N) | \ |
|
| 596 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 597 | 588 |
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_CHARGE_STAT1A) | \ |
| 598 | 589 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATLOW1) | \ |
| 599 | 590 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATGD1_N) | \ |
| ... | ... | |
| 711 | 702 |
* PD14 - PIN14 (input floating) |
| 712 | 703 |
* PD15 - PIN15 (input floating) |
| 713 | 704 |
*/ |
| 714 |
#define VAL_GPIOD_IGNORE (PIN_IGNORE(GPIOD_CHARGE_EN2_N)) & 0 |
|
| 715 | 705 |
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ |
| 716 | 706 |
PIN_MODE_INPUT(GPIOD_PIN1) | \ |
| 717 | 707 |
PIN_MODE_OUTPUT(GPIOD_CHARGE_EN2_N) | \ |
| ... | ... | |
| 829 | 819 |
* PE14 - PIN14 (input floating) |
| 830 | 820 |
* PE15 - PIN15 (input floating) |
| 831 | 821 |
*/ |
| 832 |
#define VAL_GPIOE_IGNORE 0 |
|
| 833 | 822 |
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ |
| 834 | 823 |
PIN_MODE_INPUT(GPIOE_PIN1) | \ |
| 835 | 824 |
PIN_MODE_INPUT(GPIOE_PIN2) | \ |
| ... | ... | |
| 947 | 936 |
* PF14 - PIN14 (input floating) |
| 948 | 937 |
* PF15 - PIN15 (input floating) |
| 949 | 938 |
*/ |
| 950 |
#define VAL_GPIOF_IGNORE 0 |
|
| 951 | 939 |
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ |
| 952 | 940 |
PIN_MODE_INPUT(GPIOF_PIN1) | \ |
| 953 | 941 |
PIN_MODE_INPUT(GPIOF_PIN2) | \ |
| ... | ... | |
| 1065 | 1053 |
* PG14 - PIN14 (input floating) |
| 1066 | 1054 |
* PG15 - PIN15 (input floating) |
| 1067 | 1055 |
*/ |
| 1068 |
#define VAL_GPIOG_IGNORE 0 |
|
| 1069 | 1056 |
#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ |
| 1070 | 1057 |
PIN_MODE_INPUT(GPIOG_PIN1) | \ |
| 1071 | 1058 |
PIN_MODE_INPUT(GPIOG_PIN2) | \ |
| ... | ... | |
| 1183 | 1170 |
* PH14 - PIN14 (input floating) |
| 1184 | 1171 |
* PH15 - PIN15 (input floating) |
| 1185 | 1172 |
*/ |
| 1186 |
#define VAL_GPIOH_IGNORE 0 |
|
| 1187 | 1173 |
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ |
| 1188 | 1174 |
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ |
| 1189 | 1175 |
PIN_MODE_INPUT(GPIOH_PIN2) | \ |
| ... | ... | |
| 1301 | 1287 |
* PI14 - PIN14 (input floating) |
| 1302 | 1288 |
* PI15 - PIN15 (input floating) |
| 1303 | 1289 |
*/ |
| 1304 |
#define VAL_GPIOI_IGNORE 0 |
|
| 1305 | 1290 |
#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ |
| 1306 | 1291 |
PIN_MODE_INPUT(GPIOI_PIN1) | \ |
| 1307 | 1292 |
PIN_MODE_INPUT(GPIOI_PIN2) | \ |
| modules/PowerManagement_1-2/module.h | ||
|---|---|---|
| 251 | 251 |
extern ROMCONST apalControlGpio_t moduleGpioGaugeBatGd1; |
| 252 | 252 |
|
| 253 | 253 |
/** |
| 254 |
* @brief CHARG_EN1 output signal GPIO. |
|
| 254 |
* @brief CHARGE_EN1 output signal GPIO.
|
|
| 255 | 255 |
*/ |
| 256 | 256 |
extern ROMCONST apalControlGpio_t moduleGpioChargeEn1; |
| 257 | 257 |
|
Also available in: Unified diff