Revision 37bacabf
| modules/DiWheelDrive_1-1/board.c | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief DiWheeDrive v1.1 Board specific initializations. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup diwheeldrive_board |
| modules/DiWheelDrive_1-1/board.h | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief DiWheeDrive v1.1 Board specific macros. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup diwheeldrive_board |
| ... | ... | |
| 252 | 252 |
#define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
| 253 | 253 |
#define PIN_ODR_LOW(n) (0U << (n)) |
| 254 | 254 |
#define PIN_ODR_HIGH(n) (1U << (n)) |
| 255 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 255 | 256 |
|
| 256 | 257 |
/* |
| 257 | 258 |
* GPIOA setup: |
| ... | ... | |
| 273 | 274 |
* PA14 - SWCLK (input pullup) |
| 274 | 275 |
* PA15 - DRIVE_PWM2B (alternate pushpull 50MHz) |
| 275 | 276 |
*/ |
| 277 |
#define VAL_GPIOAIGN (PIN_IGNORE(GPIOA_LED)) & 0 |
|
| 276 | 278 |
#define VAL_GPIOACRL (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 277 | 279 |
PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 278 | 280 |
PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
| ... | ... | |
| 326 | 328 |
* PB14 - SYS_UART_UP (output opendrain high 50MHz) |
| 327 | 329 |
* PB15 - ACCEL_INT_N (input pullup) |
| 328 | 330 |
*/ |
| 331 |
#define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
|
| 329 | 332 |
#define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 330 | 333 |
PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
| 331 | 334 |
PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
| ... | ... | |
| 379 | 382 |
* PC14 - GYRO_SS_N (output pushpull high 50MHz) |
| 380 | 383 |
* PC15 - PIN15 (input floating) |
| 381 | 384 |
*/ |
| 385 |
#define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_INT_N) | \ |
|
| 386 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 382 | 387 |
#define VAL_GPIOCCRL (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
| 383 |
PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \
|
|
| 388 |
PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 384 | 389 |
PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 385 | 390 |
PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 386 | 391 |
PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 432 | 437 |
* PD14 - PIN14 (input floating) |
| 433 | 438 |
* PD15 - PIN15 (input floating) |
| 434 | 439 |
*/ |
| 440 |
#define VAL_GPIODIGN 0 |
|
| 435 | 441 |
#define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 436 | 442 |
PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 437 | 443 |
PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| ... | ... | |
| 485 | 491 |
* PE14 - PIN14 (input floating) |
| 486 | 492 |
* PE15 - PIN15 (input floating) |
| 487 | 493 |
*/ |
| 494 |
#define VAL_GPIOEIGN 0 |
|
| 488 | 495 |
#define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 489 | 496 |
PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 490 | 497 |
PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 538 | 545 |
* PF14 - PIN14 (input floating) |
| 539 | 546 |
* PF15 - PIN15 (input floating) |
| 540 | 547 |
*/ |
| 548 |
#define VAL_GPIOFIGN 0 |
|
| 541 | 549 |
#define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 542 | 550 |
PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 543 | 551 |
PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 591 | 599 |
* PG14 - PIN14 (input floating) |
| 592 | 600 |
* PG15 - PIN15 (input floating) |
| 593 | 601 |
*/ |
| 602 |
#define VAL_GPIOGIGN 0 |
|
| 594 | 603 |
#define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 595 | 604 |
PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 596 | 605 |
PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| modules/DiWheelDrive_1-1/module.h | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief Structures and constant for the DiWheelDrive module. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup diwheeldrive_module |
| modules/LightRing_1-0/board.c | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief LightRing v1.0 Board specific initializations. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup lightring_board |
| modules/LightRing_1-0/board.h | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief LightRing v1.0 Board specific macros. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup lightring_board |
| ... | ... | |
| 236 | 236 |
#define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
| 237 | 237 |
#define PIN_ODR_LOW(n) (0U << (n)) |
| 238 | 238 |
#define PIN_ODR_HIGH(n) (1U << (n)) |
| 239 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 239 | 240 |
|
| 240 | 241 |
/* |
| 241 | 242 |
* GPIOA setup: |
| ... | ... | |
| 257 | 258 |
* PA14 - SWCLK (input pullup) |
| 258 | 259 |
* PA15 - PIN15 (input floating) |
| 259 | 260 |
*/ |
| 261 |
#define VAL_GPIOAIGN 0 |
|
| 260 | 262 |
#define VAL_GPIOACRL (PIN_CR(GPIOA_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 261 | 263 |
PIN_CR(GPIOA_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 262 | 264 |
PIN_CR(GPIOA_LASER_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
| ... | ... | |
| 310 | 312 |
* PB14 - WL_MISO (input pullup) |
| 311 | 313 |
* PB15 - WL_MOSI (alternate pushpull 50MHz) |
| 312 | 314 |
*/ |
| 315 |
#define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_DN)) & 0 |
|
| 313 | 316 |
#define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 314 | 317 |
PIN_CR(GPIOB_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 315 | 318 |
PIN_CR(GPIOB_LASER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
| ... | ... | |
| 363 | 366 |
* PC14 - SYS_PD_N (output opendrain high 50MHz) |
| 364 | 367 |
* PC15 - PIN15 (input floating) |
| 365 | 368 |
*/ |
| 369 |
#define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 366 | 370 |
#define VAL_GPIOCCRL (PIN_CR(GPIOC_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 367 | 371 |
PIN_CR(GPIOC_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 368 | 372 |
PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 416 | 420 |
* PD14 - PIN14 (input floating) |
| 417 | 421 |
* PD15 - PIN15 (input floating) |
| 418 | 422 |
*/ |
| 423 |
#define VAL_GPIODIGN (PIN_IGNORE(GPIOD_SYS_INT_N)) & 0 |
|
| 419 | 424 |
#define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 420 | 425 |
PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 421 | 426 |
PIN_CR(GPIOD_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| ... | ... | |
| 469 | 474 |
* PE14 - PIN14 (input floating) |
| 470 | 475 |
* PE15 - PIN15 (input floating) |
| 471 | 476 |
*/ |
| 477 |
#define VAL_GPIOEIGN 0 |
|
| 472 | 478 |
#define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 473 | 479 |
PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 474 | 480 |
PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 522 | 528 |
* PF14 - PIN14 (input floating) |
| 523 | 529 |
* PF15 - PIN15 (input floating) |
| 524 | 530 |
*/ |
| 531 |
#define VAL_GPIOFIGN 0 |
|
| 525 | 532 |
#define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 526 | 533 |
PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 527 | 534 |
PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| ... | ... | |
| 575 | 582 |
* PG14 - PIN14 (input floating) |
| 576 | 583 |
* PG15 - PIN15 (input floating) |
| 577 | 584 |
*/ |
| 585 |
#define VAL_GPIOGIGN 0 |
|
| 578 | 586 |
#define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 579 | 587 |
PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 580 | 588 |
PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| modules/PowerManagement_1-1/board.c | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief PowerManagement v1.1 Board specific initializations. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup powermanagement_board |
| ... | ... | |
| 28 | 28 |
#include <stm32_gpio.h> |
| 29 | 29 |
|
| 30 | 30 |
/** |
| 31 |
* @brief Type of STM32 GPIO port setup. |
|
| 31 |
* @brief GPIO initialization. |
|
| 32 |
* |
|
| 33 |
* @param[in] gpiop GPIO register block. |
|
| 34 |
* @param[in] config GPIO configuration. |
|
| 32 | 35 |
*/ |
| 33 |
typedef struct {
|
|
| 34 |
uint32_t moder; |
|
| 35 |
uint32_t otyper; |
|
| 36 |
uint32_t ospeedr; |
|
| 37 |
uint32_t pupdr; |
|
| 38 |
uint32_t odr; |
|
| 39 |
uint32_t afrl; |
|
| 40 |
uint32_t afrh; |
|
| 41 |
} gpio_setup_t; |
|
| 42 | 36 |
|
| 43 |
/** |
|
| 44 |
* @brief Type of STM32 GPIO initialization data. |
|
| 45 |
*/ |
|
| 46 |
typedef struct {
|
|
| 47 |
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) |
|
| 48 |
gpio_setup_t PAData; |
|
| 49 |
#endif |
|
| 50 |
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) |
|
| 51 |
gpio_setup_t PBData; |
|
| 52 |
#endif |
|
| 53 |
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) |
|
| 54 |
gpio_setup_t PCData; |
|
| 55 |
#endif |
|
| 56 |
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) |
|
| 57 |
gpio_setup_t PDData; |
|
| 58 |
#endif |
|
| 59 |
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) |
|
| 60 |
gpio_setup_t PEData; |
|
| 61 |
#endif |
|
| 62 |
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) |
|
| 63 |
gpio_setup_t PFData; |
|
| 64 |
#endif |
|
| 65 |
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) |
|
| 66 |
gpio_setup_t PGData; |
|
| 67 |
#endif |
|
| 68 |
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) |
|
| 69 |
gpio_setup_t PHData; |
|
| 70 |
#endif |
|
| 71 |
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) |
|
| 72 |
gpio_setup_t PIData; |
|
| 73 |
#endif |
|
| 74 |
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) |
|
| 75 |
gpio_setup_t PJData; |
|
| 76 |
#endif |
|
| 77 |
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) |
|
| 78 |
gpio_setup_t PKData; |
|
| 79 |
#endif |
|
| 80 |
} gpio_config_t; |
|
| 81 | 37 |
|
| 82 |
/** |
|
| 83 |
* @brief STM32 GPIO static initialization data. |
|
| 84 |
*/ |
|
| 85 |
static const gpio_config_t gpio_default_config = {
|
|
| 86 |
#if STM32_HAS_GPIOA |
|
| 87 |
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
|
| 88 |
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
|
| 89 |
#endif |
|
| 90 |
#if STM32_HAS_GPIOB |
|
| 91 |
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
|
| 92 |
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
|
| 93 |
#endif |
|
| 94 |
#if STM32_HAS_GPIOC |
|
| 95 |
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
|
| 96 |
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
|
| 97 |
#endif |
|
| 98 |
#if STM32_HAS_GPIOD |
|
| 99 |
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
|
| 100 |
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
|
| 101 |
#endif |
|
| 102 |
#if STM32_HAS_GPIOE |
|
| 103 |
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
|
| 104 |
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
|
| 105 |
#endif |
|
| 106 |
#if STM32_HAS_GPIOF |
|
| 107 |
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
|
| 108 |
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
|
| 109 |
#endif |
|
| 110 |
#if STM32_HAS_GPIOG |
|
| 111 |
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
|
| 112 |
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
|
| 113 |
#endif |
|
| 114 |
#if STM32_HAS_GPIOH |
|
| 115 |
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
|
| 116 |
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
|
| 117 |
#endif |
|
| 118 |
#if STM32_HAS_GPIOI |
|
| 119 |
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
|
| 120 |
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, |
|
| 121 |
#endif |
|
| 122 |
#if STM32_HAS_GPIOJ |
|
| 123 |
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
|
| 124 |
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, |
|
| 125 |
#endif |
|
| 126 |
#if STM32_HAS_GPIOK |
|
| 127 |
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
|
| 128 |
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} |
|
| 129 |
#endif |
|
| 130 |
}; |
|
| 131 | 38 |
|
| 132 | 39 |
/** |
| 133 | 40 |
* @brief GPIO initialization. |
| 134 | 41 |
* |
| 135 |
* @param[in] gpiop GPIO register block. |
|
| 136 |
* @param[in] config GPIO configuration. |
|
| 42 |
* @param[in] gpiop GPIO register block. |
|
| 43 |
* @param[in] moder Mode register configuration. |
|
| 44 |
* @param[in] otyper Otype register configuration. |
|
| 45 |
* @param[in] ospeedr Ospeed register configuration. |
|
| 46 |
* @param[in] pupdr Pupd register configuration. |
|
| 47 |
* @param[in] odr OD register configuration. |
|
| 48 |
* @param[in] afrl AF register (low) configuration. |
|
| 49 |
* @param[in] afrh AF register (high ) configuration. |
|
| 50 |
* @param[in] ignmask Mask to ignore individual pads. |
|
| 137 | 51 |
*/ |
| 138 |
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
|
| 139 |
|
|
| 140 |
gpiop->OTYPER = config->otyper; |
|
| 141 |
gpiop->OSPEEDR = config->ospeedr; |
|
| 142 |
gpiop->PUPDR = config->pupdr; |
|
| 143 |
gpiop->ODR = config->odr; |
|
| 144 |
gpiop->AFRL = config->afrl; |
|
| 145 |
gpiop->AFRH = config->afrh; |
|
| 146 |
gpiop->MODER = config->moder; |
|
| 52 |
static void gpio_init(stm32_gpio_t *gpiop, |
|
| 53 |
const uint32_t moder, |
|
| 54 |
const uint32_t otyper, |
|
| 55 |
const uint32_t ospeedr, |
|
| 56 |
const uint32_t pupdr, |
|
| 57 |
const uint32_t odr, |
|
| 58 |
const uint32_t afrl, |
|
| 59 |
const uint32_t afrh, |
|
| 60 |
const uint16_t ignmask) {
|
|
| 61 |
|
|
| 62 |
uint32_t ignmask2 = 0; |
|
| 63 |
uint32_t ignmask4_low = 0; |
|
| 64 |
uint32_t ignmask4_high = 0; |
|
| 65 |
|
|
| 66 |
/* some bit-magic to fan out the mask */ |
|
| 67 |
const uint8_t lut[] = {0x00, 0x03, 0x0C, 0x0F,
|
|
| 68 |
0x30, 0x33, 0x3C, 0x3F, |
|
| 69 |
0xC0, 0xC3, 0xCC, 0xCF, |
|
| 70 |
0xF0, 0xF3, 0xFC, 0xFF}; |
|
| 71 |
for (uint8_t i = 0; i < 4; ++i) {
|
|
| 72 |
ignmask2 |= lut[(ignmask >> 4*i) & 0x0F] << (8*i); |
|
| 73 |
ignmask4_low |= lut[lut[(ignmask >> 2*i) & 0x03]] << (8*i); |
|
| 74 |
ignmask4_high |= lut[lut[(ignmask >> (8 + 2*i)) & 0x03]] << (8*i); |
|
| 75 |
} |
|
| 76 |
|
|
| 77 |
gpiop->OTYPER = (gpiop->OTYPER & ignmask ) | (otyper & ~ignmask ); |
|
| 78 |
gpiop->OSPEEDR = (gpiop->OSPEEDR & ignmask2 ) | (ospeedr & ~ignmask2 ); |
|
| 79 |
gpiop->PUPDR = (gpiop->PUPDR & ignmask2 ) | (pupdr & ~ignmask2 ); |
|
| 80 |
gpiop->ODR = (gpiop->ODR & ignmask ) | (odr & ~ignmask ); |
|
| 81 |
gpiop->AFRL = (gpiop->AFRL & ignmask4_low ) | (afrl & ~ignmask4_low ); |
|
| 82 |
gpiop->AFRH = (gpiop->AFRH & ignmask4_high) | (afrh & ~ignmask4_high); |
|
| 83 |
gpiop->MODER = (gpiop->MODER & ignmask2 ) | (moder & ~ignmask2 ); |
|
| 147 | 84 |
} |
| 148 | 85 |
|
| 149 | 86 |
/** |
| ... | ... | |
| 158 | 95 |
|
| 159 | 96 |
/* Initializing all the defined GPIO ports.*/ |
| 160 | 97 |
#if STM32_HAS_GPIOA |
| 161 |
gpio_init(GPIOA, &gpio_default_config.PAData);
|
|
| 98 |
gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_IGNORE);
|
|
| 162 | 99 |
#endif |
| 163 | 100 |
#if STM32_HAS_GPIOB |
| 164 |
gpio_init(GPIOB, &gpio_default_config.PBData);
|
|
| 101 |
gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_IGNORE);
|
|
| 165 | 102 |
#endif |
| 166 | 103 |
#if STM32_HAS_GPIOC |
| 167 |
gpio_init(GPIOC, &gpio_default_config.PCData);
|
|
| 104 |
gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_IGNORE);
|
|
| 168 | 105 |
#endif |
| 169 | 106 |
#if STM32_HAS_GPIOD |
| 170 |
gpio_init(GPIOD, &gpio_default_config.PDData);
|
|
| 107 |
gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_IGNORE);
|
|
| 171 | 108 |
#endif |
| 172 | 109 |
#if STM32_HAS_GPIOE |
| 173 |
gpio_init(GPIOE, &gpio_default_config.PEData);
|
|
| 110 |
gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_IGNORE);
|
|
| 174 | 111 |
#endif |
| 175 | 112 |
#if STM32_HAS_GPIOF |
| 176 |
gpio_init(GPIOF, &gpio_default_config.PFData);
|
|
| 113 |
gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_IGNORE);
|
|
| 177 | 114 |
#endif |
| 178 | 115 |
#if STM32_HAS_GPIOG |
| 179 |
gpio_init(GPIOG, &gpio_default_config.PGData);
|
|
| 116 |
gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_IGNORE);
|
|
| 180 | 117 |
#endif |
| 181 | 118 |
#if STM32_HAS_GPIOH |
| 182 |
gpio_init(GPIOH, &gpio_default_config.PHData);
|
|
| 119 |
gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_IGNORE);
|
|
| 183 | 120 |
#endif |
| 184 | 121 |
#if STM32_HAS_GPIOI |
| 185 |
gpio_init(GPIOI, &gpio_default_config.PIData);
|
|
| 122 |
gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_IGNORE);
|
|
| 186 | 123 |
#endif |
| 187 | 124 |
#if STM32_HAS_GPIOJ |
| 188 |
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
|
| 125 |
gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_IGNORE);
|
|
| 189 | 126 |
#endif |
| 190 | 127 |
#if STM32_HAS_GPIOK |
| 191 |
gpio_init(GPIOK, &gpio_default_config.PKData);
|
|
| 128 |
gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_IGNORE);
|
|
| 192 | 129 |
#endif |
| 193 | 130 |
} |
| 194 | 131 |
|
| modules/PowerManagement_1-1/board.h | ||
|---|---|---|
| 17 | 17 |
*/ |
| 18 | 18 |
|
| 19 | 19 |
/** |
| 20 |
* @file
|
|
| 20 |
* @file |
|
| 21 | 21 |
* @brief PowerManagement v1.1 Board specific macros. |
| 22 | 22 |
* |
| 23 | 23 |
* @addtogroup powermanagement_board |
| ... | ... | |
| 299 | 299 |
* in the initialization code. |
| 300 | 300 |
* Please refer to the STM32 Reference Manual for details. |
| 301 | 301 |
*/ |
| 302 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 302 | 303 |
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
| 303 | 304 |
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
| 304 | 305 |
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
| ... | ... | |
| 336 | 337 |
* PA14 - SWCLK (alternate 0 pushpull floating) |
| 337 | 338 |
* PA15 - SYS_SPI_SS1_N (input floating) |
| 338 | 339 |
*/ |
| 340 |
#define VAL_GPIOA_IGNORE 0 |
|
| 339 | 341 |
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP) | \ |
| 340 | 342 |
PIN_MODE_INPUT(GPIOA_PIN1) | \ |
| 341 | 343 |
PIN_MODE_INPUT(GPIOA_SYS_UART_TX) | \ |
| ... | ... | |
| 453 | 455 |
* PB14 - BT_CTS (inout floating) |
| 454 | 456 |
* PB15 - SYS_UART_UP (output opendrain high) |
| 455 | 457 |
*/ |
| 458 |
#define VAL_GPIOB_IGNORE (PIN_IGNORE(GPIOB_POWER_EN) | \ |
|
| 459 |
PIN_IGNORE(GPIOB_SYS_UART_DN) | \ |
|
| 460 |
PIN_IGNORE(GPIOB_LED) | \ |
|
| 461 |
PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
|
| 456 | 462 |
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_IR_INT1_N) | \ |
| 457 | 463 |
PIN_MODE_ANALOG(GPIOB_VSYS_SENSE) | \ |
| 458 | 464 |
PIN_MODE_OUTPUT(GPIOB_POWER_EN) | \ |
| ... | ... | |
| 570 | 576 |
* PC14 - SYS_WARMRST_N (output opendrain high) |
| 571 | 577 |
* PC15 - BT_RST (output opendrain high) |
| 572 | 578 |
*/ |
| 579 |
#define VAL_GPIOC_IGNORE (PIN_IGNORE(GPIOC_CHARGE_EN1_N) | \ |
|
| 580 |
PIN_IGNORE(GPIOC_SYS_INT_N) | \ |
|
| 581 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 573 | 582 |
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_CHARGE_STAT1A) | \ |
| 574 | 583 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATLOW1) | \ |
| 575 | 584 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATGD1_N) | \ |
| ... | ... | |
| 687 | 696 |
* PD14 - PIN14 (input floating) |
| 688 | 697 |
* PD15 - PIN15 (input floating) |
| 689 | 698 |
*/ |
| 699 |
#define VAL_GPIOD_IGNORE (PIN_IGNORE(GPIOD_CHARGE_EN2_N)) & 0 |
|
| 690 | 700 |
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ |
| 691 | 701 |
PIN_MODE_INPUT(GPIOD_PIN1) | \ |
| 692 | 702 |
PIN_MODE_OUTPUT(GPIOD_CHARGE_EN2_N) | \ |
| ... | ... | |
| 804 | 814 |
* PE14 - PIN14 (input floating) |
| 805 | 815 |
* PE15 - PIN15 (input floating) |
| 806 | 816 |
*/ |
| 817 |
#define VAL_GPIOE_IGNORE 0 |
|
| 807 | 818 |
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ |
| 808 | 819 |
PIN_MODE_INPUT(GPIOE_PIN1) | \ |
| 809 | 820 |
PIN_MODE_INPUT(GPIOE_PIN2) | \ |
| ... | ... | |
| 921 | 932 |
* PF14 - PIN14 (input floating) |
| 922 | 933 |
* PF15 - PIN15 (input floating) |
| 923 | 934 |
*/ |
| 935 |
#define VAL_GPIOF_IGNORE 0 |
|
| 924 | 936 |
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ |
| 925 | 937 |
PIN_MODE_INPUT(GPIOF_PIN1) | \ |
| 926 | 938 |
PIN_MODE_INPUT(GPIOF_PIN2) | \ |
| ... | ... | |
| 1038 | 1050 |
* PG14 - PIN14 (input floating) |
| 1039 | 1051 |
* PG15 - PIN15 (input floating) |
| 1040 | 1052 |
*/ |
| 1053 |
#define VAL_GPIOG_IGNORE 0 |
|
| 1041 | 1054 |
#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ |
| 1042 | 1055 |
PIN_MODE_INPUT(GPIOG_PIN1) | \ |
| 1043 | 1056 |
PIN_MODE_INPUT(GPIOG_PIN2) | \ |
| ... | ... | |
| 1155 | 1168 |
* PH14 - PIN14 (input floating) |
| 1156 | 1169 |
* PH15 - PIN15 (input floating) |
| 1157 | 1170 |
*/ |
| 1171 |
#define VAL_GPIOH_IGNORE 0 |
|
| 1158 | 1172 |
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ |
| 1159 | 1173 |
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ |
| 1160 | 1174 |
PIN_MODE_INPUT(GPIOH_PIN2) | \ |
| ... | ... | |
| 1272 | 1286 |
* PI14 - PIN14 (input floating) |
| 1273 | 1287 |
* PI15 - PIN15 (input floating) |
| 1274 | 1288 |
*/ |
| 1289 |
#define VAL_GPIOI_IGNORE 0 |
|
| 1275 | 1290 |
#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ |
| 1276 | 1291 |
PIN_MODE_INPUT(GPIOI_PIN1) | \ |
| 1277 | 1292 |
PIN_MODE_INPUT(GPIOI_PIN2) | \ |
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