Revision 37bacabf modules/PowerManagement_1-1/board.c
modules/PowerManagement_1-1/board.c | ||
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*/ |
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/** |
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* @file
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* @file |
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* @brief PowerManagement v1.1 Board specific initializations. |
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* |
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* @addtogroup powermanagement_board |
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#include <stm32_gpio.h> |
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/** |
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* @brief Type of STM32 GPIO port setup. |
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* @brief GPIO initialization. |
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* |
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* @param[in] gpiop GPIO register block. |
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* @param[in] config GPIO configuration. |
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*/ |
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typedef struct { |
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uint32_t moder; |
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uint32_t otyper; |
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uint32_t ospeedr; |
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uint32_t pupdr; |
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uint32_t odr; |
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uint32_t afrl; |
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uint32_t afrh; |
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} gpio_setup_t; |
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/** |
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* @brief Type of STM32 GPIO initialization data. |
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*/ |
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typedef struct { |
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#if STM32_HAS_GPIOA || defined(__DOXYGEN__) |
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gpio_setup_t PAData; |
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#endif |
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#if STM32_HAS_GPIOB || defined(__DOXYGEN__) |
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gpio_setup_t PBData; |
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#endif |
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#if STM32_HAS_GPIOC || defined(__DOXYGEN__) |
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gpio_setup_t PCData; |
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#endif |
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#if STM32_HAS_GPIOD || defined(__DOXYGEN__) |
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gpio_setup_t PDData; |
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#endif |
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__) |
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gpio_setup_t PEData; |
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#endif |
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__) |
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gpio_setup_t PFData; |
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#endif |
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__) |
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gpio_setup_t PGData; |
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#endif |
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__) |
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gpio_setup_t PHData; |
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#endif |
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#if STM32_HAS_GPIOI || defined(__DOXYGEN__) |
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gpio_setup_t PIData; |
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#endif |
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#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) |
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gpio_setup_t PJData; |
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#endif |
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#if STM32_HAS_GPIOK || defined(__DOXYGEN__) |
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gpio_setup_t PKData; |
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#endif |
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} gpio_config_t; |
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/** |
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* @brief STM32 GPIO static initialization data. |
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*/ |
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static const gpio_config_t gpio_default_config = { |
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#if STM32_HAS_GPIOA |
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOB |
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOC |
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOD |
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOE |
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOF |
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOG |
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOH |
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOI |
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOJ |
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{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, |
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VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, |
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#endif |
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#if STM32_HAS_GPIOK |
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{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, |
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VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} |
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#endif |
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}; |
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/** |
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* @brief GPIO initialization. |
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* |
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* @param[in] gpiop GPIO register block. |
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* @param[in] config GPIO configuration. |
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* @param[in] gpiop GPIO register block. |
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* @param[in] moder Mode register configuration. |
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* @param[in] otyper Otype register configuration. |
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* @param[in] ospeedr Ospeed register configuration. |
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* @param[in] pupdr Pupd register configuration. |
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* @param[in] odr OD register configuration. |
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* @param[in] afrl AF register (low) configuration. |
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* @param[in] afrh AF register (high ) configuration. |
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* @param[in] ignmask Mask to ignore individual pads. |
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*/ |
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static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { |
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gpiop->OTYPER = config->otyper; |
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gpiop->OSPEEDR = config->ospeedr; |
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gpiop->PUPDR = config->pupdr; |
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gpiop->ODR = config->odr; |
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gpiop->AFRL = config->afrl; |
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gpiop->AFRH = config->afrh; |
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gpiop->MODER = config->moder; |
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static void gpio_init(stm32_gpio_t *gpiop, |
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const uint32_t moder, |
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const uint32_t otyper, |
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const uint32_t ospeedr, |
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const uint32_t pupdr, |
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const uint32_t odr, |
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const uint32_t afrl, |
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const uint32_t afrh, |
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const uint16_t ignmask) { |
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uint32_t ignmask2 = 0; |
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uint32_t ignmask4_low = 0; |
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uint32_t ignmask4_high = 0; |
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/* some bit-magic to fan out the mask */ |
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const uint8_t lut[] = {0x00, 0x03, 0x0C, 0x0F, |
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0x30, 0x33, 0x3C, 0x3F, |
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0xC0, 0xC3, 0xCC, 0xCF, |
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0xF0, 0xF3, 0xFC, 0xFF}; |
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for (uint8_t i = 0; i < 4; ++i) { |
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ignmask2 |= lut[(ignmask >> 4*i) & 0x0F] << (8*i); |
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ignmask4_low |= lut[lut[(ignmask >> 2*i) & 0x03]] << (8*i); |
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ignmask4_high |= lut[lut[(ignmask >> (8 + 2*i)) & 0x03]] << (8*i); |
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} |
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gpiop->OTYPER = (gpiop->OTYPER & ignmask ) | (otyper & ~ignmask ); |
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gpiop->OSPEEDR = (gpiop->OSPEEDR & ignmask2 ) | (ospeedr & ~ignmask2 ); |
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gpiop->PUPDR = (gpiop->PUPDR & ignmask2 ) | (pupdr & ~ignmask2 ); |
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gpiop->ODR = (gpiop->ODR & ignmask ) | (odr & ~ignmask ); |
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gpiop->AFRL = (gpiop->AFRL & ignmask4_low ) | (afrl & ~ignmask4_low ); |
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gpiop->AFRH = (gpiop->AFRH & ignmask4_high) | (afrh & ~ignmask4_high); |
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gpiop->MODER = (gpiop->MODER & ignmask2 ) | (moder & ~ignmask2 ); |
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} |
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/** |
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/* Initializing all the defined GPIO ports.*/ |
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#if STM32_HAS_GPIOA |
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gpio_init(GPIOA, &gpio_default_config.PAData);
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gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_IGNORE);
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#endif |
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#if STM32_HAS_GPIOB |
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gpio_init(GPIOB, &gpio_default_config.PBData);
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gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_IGNORE);
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#endif |
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#if STM32_HAS_GPIOC |
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gpio_init(GPIOC, &gpio_default_config.PCData);
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gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_IGNORE);
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#endif |
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#if STM32_HAS_GPIOD |
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gpio_init(GPIOD, &gpio_default_config.PDData);
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gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_IGNORE);
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#endif |
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#if STM32_HAS_GPIOE |
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gpio_init(GPIOE, &gpio_default_config.PEData);
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gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_IGNORE);
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#endif |
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#if STM32_HAS_GPIOF |
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gpio_init(GPIOF, &gpio_default_config.PFData);
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gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_IGNORE);
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#endif |
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#if STM32_HAS_GPIOG |
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gpio_init(GPIOG, &gpio_default_config.PGData);
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gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_IGNORE);
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#endif |
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#if STM32_HAS_GPIOH |
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gpio_init(GPIOH, &gpio_default_config.PHData);
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gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_IGNORE);
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#endif |
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#if STM32_HAS_GPIOI |
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gpio_init(GPIOI, &gpio_default_config.PIData);
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gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_IGNORE);
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#endif |
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#if STM32_HAS_GPIOJ |
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gpio_init(GPIOJ, &gpio_default_config.PJData);
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gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_IGNORE);
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#endif |
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#if STM32_HAS_GPIOK |
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gpio_init(GPIOK, &gpio_default_config.PKData);
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gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_IGNORE);
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#endif |
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} |
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