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amiro-os / modules / PowerManagement_1-1 / board.c @ 37bacabf

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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2018  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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 * @file
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 * @brief   PowerManagement v1.1 Board specific initializations.
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 *
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 * @addtogroup powermanagement_board
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 * @{
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 */
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#include <hal.h>
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#include <stm32_gpio.h>
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/**
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 * @brief   GPIO initialization.
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 *
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 * @param[in]   gpiop   GPIO register block.
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 * @param[in]   config  GPIO configuration.
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 */
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/**
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 * @brief   GPIO initialization.
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 *
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 * @param[in] gpiop     GPIO register block.
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 * @param[in] moder     Mode register configuration.
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 * @param[in] otyper    Otype register configuration.
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 * @param[in] ospeedr   Ospeed register configuration.
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 * @param[in] pupdr     Pupd register configuration.
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 * @param[in] odr       OD register configuration.
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 * @param[in] afrl      AF register (low) configuration.
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 * @param[in] afrh      AF register (high ) configuration.
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 * @param[in] ignmask   Mask to ignore individual pads.
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 */
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static void gpio_init(stm32_gpio_t *gpiop,
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                      const uint32_t moder,
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                      const uint32_t otyper,
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                      const uint32_t ospeedr,
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                      const uint32_t pupdr,
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                      const uint32_t odr,
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                      const uint32_t afrl,
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                      const uint32_t afrh,
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                      const uint16_t ignmask) {
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  uint32_t ignmask2 = 0;
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  uint32_t ignmask4_low = 0;
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  uint32_t ignmask4_high = 0;
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  /* some bit-magic to fan out the mask */
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  const uint8_t lut[] = {0x00, 0x03, 0x0C, 0x0F,
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                         0x30, 0x33, 0x3C, 0x3F,
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                         0xC0, 0xC3, 0xCC, 0xCF,
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                         0xF0, 0xF3, 0xFC, 0xFF};
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  for (uint8_t i = 0; i < 4; ++i) {
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    ignmask2 |= lut[(ignmask >> 4*i) & 0x0F] << (8*i);
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    ignmask4_low |= lut[lut[(ignmask >> 2*i) & 0x03]] << (8*i);
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    ignmask4_high |= lut[lut[(ignmask >> (8 + 2*i)) & 0x03]] << (8*i);
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  }
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  gpiop->OTYPER  = (gpiop->OTYPER  & ignmask      ) | (otyper  & ~ignmask      );
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  gpiop->OSPEEDR = (gpiop->OSPEEDR & ignmask2     ) | (ospeedr & ~ignmask2     );
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  gpiop->PUPDR   = (gpiop->PUPDR   & ignmask2     ) | (pupdr   & ~ignmask2     );
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  gpiop->ODR     = (gpiop->ODR     & ignmask      ) | (odr     & ~ignmask      );
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  gpiop->AFRL    = (gpiop->AFRL    & ignmask4_low ) | (afrl    & ~ignmask4_low );
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  gpiop->AFRH    = (gpiop->AFRH    & ignmask4_high) | (afrh    & ~ignmask4_high);
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  gpiop->MODER   = (gpiop->MODER   & ignmask2     ) | (moder   & ~ignmask2     );
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}
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/**
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 * @brief   GPIO initilization for all ports.
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 */
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static void stm32_gpio_init(void) {
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  /* Enabling GPIO-related clocks, the mask comes from the
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     registry header file.*/
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  rccResetAHB1(STM32_GPIO_EN_MASK);
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  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
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  /* Initializing all the defined GPIO ports.*/
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#if STM32_HAS_GPIOA
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  gpio_init(GPIOA, VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_IGNORE);
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#endif
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#if STM32_HAS_GPIOB
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  gpio_init(GPIOB, VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_IGNORE);
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#endif
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#if STM32_HAS_GPIOC
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  gpio_init(GPIOC, VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_IGNORE);
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#endif
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#if STM32_HAS_GPIOD
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  gpio_init(GPIOD, VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_IGNORE);
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#endif
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#if STM32_HAS_GPIOE
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  gpio_init(GPIOE, VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_IGNORE);
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#endif
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#if STM32_HAS_GPIOF
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  gpio_init(GPIOF, VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_IGNORE);
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#endif
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#if STM32_HAS_GPIOG
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  gpio_init(GPIOG, VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_IGNORE);
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#endif
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#if STM32_HAS_GPIOH
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  gpio_init(GPIOH, VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_IGNORE);
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#endif
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#if STM32_HAS_GPIOI
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  gpio_init(GPIOI, VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_IGNORE);
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#endif
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#if STM32_HAS_GPIOJ
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  gpio_init(GPIOJ, VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_IGNORE);
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#endif
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#if STM32_HAS_GPIOK
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  gpio_init(GPIOK, VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_IGNORE);
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#endif
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}
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/**
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 * @brief   Early initialization code.
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 * @details This initialization must be performed just after stack setup
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 *          and before any other initialization.
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 */
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void __early_init(void) {
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  stm32_gpio_init();
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  stm32_clock_init();
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}
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/**
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 * @brief   Board-specific initialization code.
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 * @todo    Add your board-specific code, if any.
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 */
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void boardInit(void) {
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}
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/** @} */