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amiro-os / modules / DiWheelDrive_1-2 / board.h @ 510b93cc

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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019  Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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 * @file
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 * @brief   DiWheeDrive v1.2 Board specific macros.
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 *
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 * @addtogroup diwheeldrive_board
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 * @{
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 */
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#ifndef BOARD_H
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#define BOARD_H
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/*===========================================================================*/
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/* Driver constants.                                                         */
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/*===========================================================================*/
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/*
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 * Setup for AMiRo DiWheelDrive v1.2 board.
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 */
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/*
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 * Board identifier.
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 */
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#define BOARD_DIWHEELDRIVE_1_2
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#define BOARD_NAME              "AMiRo DiWheelDrive v1.2"
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/*
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 * Board oscillators-related settings.
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 * NOTE: LSE not fitted.
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 */
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK                0U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK                8000000U
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#endif
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/*
57
 * Board voltages.
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 * Required for performance limits calculation.
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 */
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#define STM32_VDD                   330U
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/*
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 * MCU type as defined in the ST header.
64
 */
65
#define STM32F103xE
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/*
68
 * IO pins assignments.
69
 */
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#define GPIOA_WKUP                  0U
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#define GPIOA_LED                   1U
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#define GPIOA_DRIVE_PWM1A           2U
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#define GPIOA_DRIVE_PWM1B           3U
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#define GPIOA_PIN4                  4U
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#define GPIOA_PIN5                  5U
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#define GPIOA_PIN6                  6U
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#define GPIOA_PIN7                  7U
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#define GPIOA_PIN8                  8U
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#define GPIOA_PROG_RX               9U
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#define GPIOA_PROG_TX               10U
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#define GPIOA_CAN_RX                11U
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#define GPIOA_CAN_TX                12U
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#define GPIOA_SWDIO                 13U
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#define GPIOA_SWCLK                 14U
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#define GPIOA_DRIVE_PWM2B           15U
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#define GPIOB_PIN0                  0U
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#define GPIOB_DRIVE_SENSE2          1U
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#define GPIOB_POWER_EN              2U
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#define GPIOB_DRIVE_PWM2A           3U
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#define GPIOB_PIN4                  4U
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#define GPIOB_PIN5                  5U
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#define GPIOB_DRIVE_ENC1A           6U
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#define GPIOB_DRIVE_ENC1B           7U
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#define GPIOB_IMU_SCL               8U
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#define GPIOB_IMU_SDA               9U
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#define GPIOB_IR_SCL                10U
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#define GPIOB_IR_SDA                11U
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#define GPIOB_IR_INT                12U
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#define GPIOB_PIN13                 13U
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#define GPIOB_SYS_UART_UP           14U
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#define GPIOB_IMU_INT               15U
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#define GPIOC_DRIVE_SENSE1          0U
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#define GPIOC_SYS_INT_N             1U
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#define GPIOC_IMU_RESET_N           2U
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#define GPIOC_PATH_DCSTAT           3U
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#define GPIOC_PIN4                  4U
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#define GPIOC_PATH_DCEN             5U
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#define GPIOC_DRIVE_ENC2B           6U
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#define GPIOC_DRIVE_ENC2A           7U
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#define GPIOC_SYS_PD_N              8U
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#define GPIOC_SYS_REG_EN            9U
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#define GPIOC_SYS_UART_RX           10U
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#define GPIOC_SYS_UART_TX           11U
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#define GPIOC_IMU_BOOT_LOAD_N       12U
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#define GPIOC_PIN13                 13U
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#define GPIOC_PIN14                 14U
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#define GPIOC_IMU_BL_IND            15U
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#define GPIOD_OSC_IN                0U
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#define GPIOD_OSC_OUT               1U
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#define GPIOD_SYS_WARMRST_N         2U
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#define GPIOD_PIN3                  3U
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#define GPIOD_PIN4                  4U
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#define GPIOD_PIN5                  5U
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#define GPIOD_PIN6                  6U
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#define GPIOD_PIN7                  7U
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#define GPIOD_PIN8                  8U
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#define GPIOD_PIN9                  9U
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#define GPIOD_PIN10                 10U
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#define GPIOD_PIN11                 11U
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#define GPIOD_PIN12                 12U
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#define GPIOD_PIN13                 13U
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#define GPIOD_PIN14                 14U
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#define GPIOD_PIN15                 15U
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#define GPIOE_PIN0                  0U
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#define GPIOE_PIN1                  1U
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#define GPIOE_PIN2                  2U
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#define GPIOE_PIN3                  3U
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#define GPIOE_PIN4                  4U
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#define GPIOE_PIN5                  5U
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#define GPIOE_PIN6                  6U
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#define GPIOE_PIN7                  7U
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#define GPIOE_PIN8                  8U
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#define GPIOE_PIN9                  9U
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#define GPIOE_PIN10                 10U
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#define GPIOE_PIN11                 11U
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#define GPIOE_PIN12                 12U
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#define GPIOE_PIN13                 13U
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#define GPIOE_PIN14                 14U
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#define GPIOE_PIN15                 15U
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155
#define GPIOF_PIN0                  0U
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#define GPIOF_PIN1                  1U
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#define GPIOF_PIN2                  2U
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#define GPIOF_PIN3                  3U
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#define GPIOF_PIN4                  4U
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#define GPIOF_PIN5                  5U
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#define GPIOF_PIN6                  6U
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#define GPIOF_PIN7                  7U
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#define GPIOF_PIN8                  8U
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#define GPIOF_PIN9                  9U
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#define GPIOF_PIN10                 10U
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#define GPIOF_PIN11                 11U
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#define GPIOF_PIN12                 12U
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#define GPIOF_PIN13                 13U
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#define GPIOF_PIN14                 14U
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#define GPIOF_PIN15                 15U
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172
#define GPIOG_PIN0                  0U
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#define GPIOG_PIN1                  1U
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#define GPIOG_PIN2                  2U
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#define GPIOG_PIN3                  3U
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#define GPIOG_PIN4                  4U
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#define GPIOG_PIN5                  5U
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#define GPIOG_PIN6                  6U
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#define GPIOG_PIN7                  7U
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#define GPIOG_PIN8                  8U
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#define GPIOG_PIN9                  9U
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#define GPIOG_PIN10                 10U
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#define GPIOG_PIN11                 11U
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#define GPIOG_PIN12                 12U
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#define GPIOG_PIN13                 13U
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#define GPIOG_PIN14                 14U
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#define GPIOG_PIN15                 15U
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189
/*
190
 * IO lines assignments.
191
 */
192
#define LINE_WKUP                   PAL_LINE(GPIOA, GPIOA_WKUP)
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#define LINE_LED                    PAL_LINE(GPIOA, GPIOA_LED)
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#define LINE_DRIVE_PWM1A            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A)
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#define LINE_DRIVE_PWM1B            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B)
196
#define LINE_PROG_RX                PAL_LINE(GPIOA, GPIOA_PROG_RX)
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#define LINE_PROG_TX                PAL_LINE(GPIOA, GPIOA_PROG_TX)
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#define LINE_CAN_RX                 PAL_LINE(GPIOA, GPIOA_CAN_RX)
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#define LINE_CAN_TX                 PAL_LINE(GPIOA, GPIOA_CAN_TX)
200
#define LINE_SWDIO                  PAL_LINE(GPIOA, GPIOA_SWDIO)
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#define LINE_SWCLK                  PAL_LINE(GPIOA, GPIOA_SWCLK)
202
#define LINE_DRIVE_PWM2B            PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B)
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#define LINE_DRIVE_SENSE2           PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2)
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#define LINE_POWER_EN               PAL_LINE(GPIOB, GPIOB_POWER_EN)
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#define LINE_DRIVE_PWM2A            PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A)
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#define LINE_DRIVE_ENC1A            PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A)
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#define LINE_DRIVE_ENC1B            PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B)
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#define LINE_IMU_SCL                PAL_LINE(GPIOB, GPIOB_IMU_SCL)
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#define LINE_IMU_SDA                PAL_LINE(GPIOB, GPIOB_IMU_SDA)
211
#define LINE_IR_SCL                 PAL_LINE(GPIOB, GPIOB_IR_SCL)
212
#define LINE_IR_SDA                 PAL_LINE(GPIOB, GPIOB_IR_SDA)
213
#define LINE_IR_INT                 PAL_LINE(GPIOB, GPIOB_IR_INT)
214
#define LINE_SYS_UART_UP            PAL_LINE(GPIOB, GPIOB_SYS_UART_UP)
215
#define LINE_IMU_INT                PAL_LINE(GPIOB, GPIOB_IMU_INT)
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#define LINE_DRIVE_SENSE1           PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1)
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#define LINE_SYS_INT_N              PAL_LINE(GPIOC, GPIOC_SYS_INT_N)
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#define LINE_IMU_RESET_N            PAL_LINE(GPIOC, GPIOC_IMU_RESET_N)
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#define LINE_PATH_DCSTAT            PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT)
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#define LINE_PATH_DCEN              PAL_LINE(GPIOC, GPIOC_PATH_DCEN)
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#define LINE_DRIVE_ENC2B            PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B)
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#define LINE_DRIVE_ENC2A            PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A)
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#define LINE_SYS_PD_N               PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
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#define LINE_SYS_REG_EN             PAL_LINE(GPIOC, GPIOC_SYS_REG_EN)
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#define LINE_SYS_UART_RX            PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
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#define LINE_SYS_UART_TX            PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
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#define LINE_IMU_BOOT_LOAD_N        PAL_LINE(GPIOC, GPIOC_IMU_BOOT_LOAD_N)
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#define LINE_IMU_BL_IND             PAL_LINE(GPIOC, GPIOC_IMU_BL_IND)
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231
#define LINE_OSC_IN                 PAL_LINE(GPIOD, GPIOD_OSC_IN)
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#define LINE_OSC_OUT                PAL_LINE(GPIOD, GPIOD_OSC_OUT)
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#define LINE_SYS_WARMRST_N          PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N)
234

    
235
/*===========================================================================*/
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/* Driver pre-compile time settings.                                         */
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/*===========================================================================*/
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239
/*===========================================================================*/
240
/* Derived constants and error checks.                                       */
241
/*===========================================================================*/
242

    
243
/*===========================================================================*/
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/* Driver data structures and types.                                         */
245
/*===========================================================================*/
246

    
247
/*===========================================================================*/
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/* Driver macros.                                                            */
249
/*===========================================================================*/
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251
/*
252
 * I/O ports initial setup, this configuration is established soon after reset
253
 * in the initialization code.
254
 * Please refer to the STM32 Reference Manual for details.
255
 */
256
#define PIN_MODE_INPUT              0U
257
#define PIN_MODE_OUTPUT_2M          2U
258
#define PIN_MODE_OUTPUT_10M         1U
259
#define PIN_MODE_OUTPUT_50M         3U
260
#define PIN_CNF_INPUT_ANALOG        0U
261
#define PIN_CNF_INPUT_FLOATING      1U
262
#define PIN_CNF_INPUT_PULLX         2U
263
#define PIN_CNF_OUTPUT_PUSHPULL     0U
264
#define PIN_CNF_OUTPUT_OPENDRAIN    1U
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#define PIN_CNF_ALTERNATE_PUSHPULL  2U
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#define PIN_CNF_ALTERNATE_OPENDRAIN 3U
267
#define PIN_CR(pin, mode, cnf)      (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U))
268
#define PIN_ODR_LOW(n)              (0U << (n))
269
#define PIN_ODR_HIGH(n)             (1U << (n))
270
#define PIN_IGNORE(n)               (1U << (n))
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272
/*
273
 * GPIOA setup:
274
 *
275
 * PA0  - WKUP                      (input floating)
276
 * PA1  - LED                       (output opendrain high 50MHz)
277
 * PA2  - DRIVE_PWM1A               (alternate pushpull 50MHz)
278
 * PA3  - DRIVE_PWM1B               (alternate pushpull 50MHz)
279
 * PA4  - PIN4                      (input floating)
280
 * PA5  - PIN5                      (input floating)
281
 * PA6  - PIN6                      (input floating)
282
 * PA7  - PIN7                      (input floating)
283
 * PA8  - PIN8                      (input floating)
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 * PA9  - PROG_RX                   (alternate pushpull 50MHz)
285
 * PA10 - PROG_TX                   (input pullup)
286
 * PA11 - CAN_RX                    (input pullup)
287
 * PA12 - CAN_TX                    (alternate pushpull 50MHz)
288
 * PA13 - SWDIO                     (input pullup)
289
 * PA14 - SWCLK                     (input pullup)
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 * PA15 - DRIVE_PWM2B               (alternate pushpull 50MHz)
291
 */
292
#define VAL_GPIOAIGN                (PIN_IGNORE(GPIOA_LED)) & 0
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#define VAL_GPIOACRL                (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |            \
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                                     PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
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                                     PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
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                                     PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
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#define VAL_GPIOACRH                (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
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                                     PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |      \
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                                     PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                  \
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                                     PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                   \
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                                     PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |       \
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                                     PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                    \
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                                     PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) |                    \
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                                     PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL))
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#define VAL_GPIOAODR                (PIN_ODR_HIGH(GPIOA_WKUP) |                                                    \
310
                                     PIN_ODR_HIGH(GPIOA_LED) |                                                     \
311
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) |                                             \
312
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) |                                             \
313
                                     PIN_ODR_LOW(GPIOA_PIN4) |                                                     \
314
                                     PIN_ODR_LOW(GPIOA_PIN5) |                                                     \
315
                                     PIN_ODR_LOW(GPIOA_PIN6) |                                                     \
316
                                     PIN_ODR_LOW(GPIOA_PIN7) |                                                     \
317
                                     PIN_ODR_LOW(GPIOA_PIN8) |                                                     \
318
                                     PIN_ODR_HIGH(GPIOA_PROG_RX) |                                                 \
319
                                     PIN_ODR_HIGH(GPIOA_PROG_TX) |                                                 \
320
                                     PIN_ODR_HIGH(GPIOA_CAN_RX) |                                                  \
321
                                     PIN_ODR_HIGH(GPIOA_CAN_TX) |                                                  \
322
                                     PIN_ODR_HIGH(GPIOA_SWDIO) |                                                   \
323
                                     PIN_ODR_HIGH(GPIOA_SWCLK) |                                                   \
324
                                     PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B))
325

    
326
/*
327
 * GPIOB setup:
328
 *
329
 * PB0  - PIN0                      (input floating)
330
 * PB1  - DRIVE_SENSE2              (input analog)
331
 * PB2  - POWER_EN                  (output pushpull low 50MHz)
332
 * PB3  - DRIVE_PWM2A               (alternate pushpull 50MHz)
333
 * PB4  - PIN4                      (input floating)
334
 * PB5  - PIN5                      (input floating)
335
 * PB6  - DRIVE_ENC1A               (input floating)
336
 * PB7  - DRIVE_ENC1B               (input floating)
337
 * PB8  - IMU_SCL                   (alternate opendrain 50MHz)
338
 * PB9  - IMU_SDA                   (alternate opendrain 50MHz)
339
 * PB10 - IR_SCL                    (alternate opendrain 50MHz)
340
 * PB11 - IR_SDA                    (alternate opendrain 50MHz)
341
 * PB12 - IR_INT                    (input floating)
342
 * PB13 - PIN13                     (input floating)
343
 * PB14 - SYS_UART_UP               (output opendrain high 50MHz)
344
 * PB15 - IMU_INT                   (input floating)
345
 */
346
#define VAL_GPIOBIGN                (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0
347
#define VAL_GPIOBCRL                (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
348
                                     PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) |            \
349
                                     PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |        \
350
                                     PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) |  \
351
                                     PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
352
                                     PIN_CR(GPIOB_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
353
                                     PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
354
                                     PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
355
#define VAL_GPIOBCRH                (PIN_CR(GPIOB_IMU_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |     \
356
                                     PIN_CR(GPIOB_IMU_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |     \
357
                                     PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |      \
358
                                     PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) |      \
359
                                     PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                \
360
                                     PIN_CR(GPIOB_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
361
                                     PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |    \
362
                                     PIN_CR(GPIOB_IMU_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
363
#define VAL_GPIOBODR                (PIN_ODR_LOW(GPIOB_PIN0) |                                                     \
364
                                     PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) |                                            \
365
                                     PIN_ODR_LOW(GPIOB_POWER_EN) |                                                 \
366
                                     PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) |                                             \
367
                                     PIN_ODR_LOW(GPIOB_PIN4) |                                                     \
368
                                     PIN_ODR_LOW(GPIOB_PIN5) |                                                     \
369
                                     PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) |                                             \
370
                                     PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) |                                             \
371
                                     PIN_ODR_HIGH(GPIOB_IMU_SCL) |                                                 \
372
                                     PIN_ODR_HIGH(GPIOB_IMU_SDA) |                                                 \
373
                                     PIN_ODR_HIGH(GPIOB_IR_SCL) |                                                  \
374
                                     PIN_ODR_HIGH(GPIOB_IR_SDA) |                                                  \
375
                                     PIN_ODR_HIGH(GPIOB_IR_INT) |                                                  \
376
                                     PIN_ODR_LOW(GPIOB_PIN13) |                                                    \
377
                                     PIN_ODR_HIGH(GPIOB_SYS_UART_UP) |                                             \
378
                                     PIN_ODR_LOW(GPIOB_IMU_INT))
379

    
380
/*
381
 * GPIOC setup:
382
 *
383
 * PC0  - DRIVE_SENSE1              (input analog)
384
 * PC1  - SYS_INT_N                 (output opendrain low 50MHz)
385
 * PC2  - IMU_RESET_N               (output opendrain high 50MHz)
386
 * PC3  - PATH_DCSTAT               (input floating)
387
 * PC4  - PIN4                      (input floating)
388
 * PC5  - PATH_DCEN                 (output pushpull low 50MHz)
389
 * PC6  - DRIVE_ENC2B               (input floating)
390
 * PC7  - DRIVE_ENC2A               (input floating)
391
 * PC8  - SYS_PD_N                  (output opendrain high 50MHz)
392
 * PC9  - SYS_REG_EN                (input floating)
393
 * PC10 - SYS_UART_RX               (input floating)
394
 * PC11 - SYS_UART_TX               (input floating)
395
 * PC12 - IMU_BOOT_LOAD_N           (output opendrain high 50MHz)
396
 * PC13 - PIN13                     (input floating)
397
 * PC14 - PIN14                     (input floating)
398
 * PC15 - IMU_BL_IND                (input floating)
399
 */
400
#define VAL_GPIOCIGN                (PIN_IGNORE(GPIOC_SYS_INT_N) |                                                 \
401
                                     PIN_IGNORE(GPIOC_SYS_PD_N)) & 0
402
#define VAL_GPIOCCRL                (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) |            \
403
                                     PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |      \
404
                                     PIN_CR(GPIOC_IMU_RESET_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |    \
405
                                     PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
406
                                     PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
407
                                     PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) |       \
408
                                     PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
409
                                     PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
410
#define VAL_GPIOCCRH                (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |       \
411
                                     PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |            \
412
                                     PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
413
                                     PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |           \
414
                                     PIN_CR(GPIOC_IMU_BOOT_LOAD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |  \
415
                                     PIN_CR(GPIOC_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
416
                                     PIN_CR(GPIOC_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
417
                                     PIN_CR(GPIOC_IMU_BL_IND, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
418
#define VAL_GPIOCODR                (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) |                                            \
419
                                     PIN_ODR_LOW(GPIOC_SYS_INT_N) |                                                \
420
                                     PIN_ODR_HIGH(GPIOC_IMU_RESET_N) |                                             \
421
                                     PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) |                                             \
422
                                     PIN_ODR_LOW(GPIOC_PIN4) |                                                     \
423
                                     PIN_ODR_LOW(GPIOC_PATH_DCEN) |                                                \
424
                                     PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) |                                             \
425
                                     PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) |                                             \
426
                                     PIN_ODR_HIGH(GPIOC_SYS_PD_N) |                                                \
427
                                     PIN_ODR_HIGH(GPIOC_SYS_REG_EN) |                                              \
428
                                     PIN_ODR_HIGH(GPIOC_SYS_UART_RX) |                                             \
429
                                     PIN_ODR_HIGH(GPIOC_SYS_UART_TX) |                                             \
430
                                     PIN_ODR_HIGH(GPIOC_IMU_BOOT_LOAD_N) |                                         \
431
                                     PIN_ODR_LOW(GPIOC_PIN13) |                                                    \
432
                                     PIN_ODR_LOW(GPIOC_PIN14) |                                                    \
433
                                     PIN_ODR_LOW(GPIOC_IMU_BL_IND))
434

    
435
/*
436
 * GPIOD setup:
437
 *
438
 * PD0  - OSC_IN                    (input floating)
439
 * PD1  - OSC_OUT                   (input floating)
440
 * PD2  - SYS_WARMRST_N             (output opendrain high 50MHz)
441
 * PD3  - PIN3                      (input floating)
442
 * PD4  - PIN4                      (input floating)
443
 * PD5  - PIN5                      (input floating)
444
 * PD6  - PIN6                      (input floating)
445
 * PD7  - PIN7                      (input floating)
446
 * PD8  - PIN8                      (input floating)
447
 * PD9  - PIN9                      (input floating)
448
 * PD10 - PIN10                     (input floating)
449
 * PD11 - PIN11                     (input floating)
450
 * PD12 - PIN12                     (input floating)
451
 * PD13 - PIN13                     (input floating)
452
 * PD14 - PIN14                     (input floating)
453
 * PD15 - PIN15                     (input floating)
454
 */
455
#define VAL_GPIODIGN                0
456
#define VAL_GPIODCRL                (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                \
457
                                     PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |               \
458
                                     PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) |  \
459
                                     PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
460
                                     PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
461
                                     PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
462
                                     PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
463
                                     PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
464
#define VAL_GPIODCRH                (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
465
                                     PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
466
                                     PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
467
                                     PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
468
                                     PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
469
                                     PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
470
                                     PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
471
                                     PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
472
#define VAL_GPIODODR                (PIN_ODR_HIGH(GPIOD_OSC_IN) |                                                  \
473
                                     PIN_ODR_HIGH(GPIOD_OSC_OUT) |                                                 \
474
                                     PIN_ODR_HIGH(GPIOD_SYS_WARMRST_N) |                                           \
475
                                     PIN_ODR_LOW(GPIOD_PIN3) |                                                     \
476
                                     PIN_ODR_LOW(GPIOD_PIN4) |                                                     \
477
                                     PIN_ODR_LOW(GPIOD_PIN5) |                                                     \
478
                                     PIN_ODR_LOW(GPIOD_PIN6) |                                                     \
479
                                     PIN_ODR_LOW(GPIOD_PIN7) |                                                     \
480
                                     PIN_ODR_LOW(GPIOD_PIN8) |                                                     \
481
                                     PIN_ODR_LOW(GPIOD_PIN9) |                                                     \
482
                                     PIN_ODR_LOW(GPIOD_PIN10) |                                                    \
483
                                     PIN_ODR_LOW(GPIOD_PIN11) |                                                    \
484
                                     PIN_ODR_LOW(GPIOD_PIN12) |                                                    \
485
                                     PIN_ODR_LOW(GPIOD_PIN13) |                                                    \
486
                                     PIN_ODR_LOW(GPIOD_PIN14) |                                                    \
487
                                     PIN_ODR_LOW(GPIOD_PIN15))
488

    
489
/*
490
 * GPIOE setup:
491
 *
492
 * PE0  - PIN0                      (input floating)
493
 * PE1  - PIN1                      (input floating)
494
 * PE2  - PIN2                      (input floating)
495
 * PE3  - PIN3                      (input floating)
496
 * PE4  - PIN4                      (input floating)
497
 * PE5  - PIN5                      (input floating)
498
 * PE6  - PIN6                      (input floating)
499
 * PE7  - PIN7                      (input floating)
500
 * PE8  - PIN8                      (input floating)
501
 * PE9  - PIN9                      (input floating)
502
 * PE10 - PIN10                     (input floating)
503
 * PE11 - PIN11                     (input floating)
504
 * PE12 - PIN12                     (input floating)
505
 * PE13 - PIN13                     (input floating)
506
 * PE14 - PIN14                     (input floating)
507
 * PE15 - PIN15                     (input floating)
508
 */
509
#define VAL_GPIOEIGN                0
510
#define VAL_GPIOECRL                (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
511
                                     PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
512
                                     PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
513
                                     PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
514
                                     PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
515
                                     PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
516
                                     PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
517
                                     PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
518
#define VAL_GPIOECRH                (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
519
                                     PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
520
                                     PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
521
                                     PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
522
                                     PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
523
                                     PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
524
                                     PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
525
                                     PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
526
#define VAL_GPIOEODR                (PIN_ODR_LOW(GPIOE_PIN0) |                                                     \
527
                                     PIN_ODR_LOW(GPIOE_PIN1) |                                                     \
528
                                     PIN_ODR_LOW(GPIOE_PIN2) |                                                     \
529
                                     PIN_ODR_LOW(GPIOE_PIN3) |                                                     \
530
                                     PIN_ODR_LOW(GPIOE_PIN4) |                                                     \
531
                                     PIN_ODR_LOW(GPIOE_PIN5) |                                                     \
532
                                     PIN_ODR_LOW(GPIOE_PIN6) |                                                     \
533
                                     PIN_ODR_LOW(GPIOE_PIN7) |                                                     \
534
                                     PIN_ODR_LOW(GPIOE_PIN8) |                                                     \
535
                                     PIN_ODR_LOW(GPIOE_PIN9) |                                                     \
536
                                     PIN_ODR_LOW(GPIOE_PIN10) |                                                    \
537
                                     PIN_ODR_LOW(GPIOE_PIN11) |                                                    \
538
                                     PIN_ODR_LOW(GPIOE_PIN12) |                                                    \
539
                                     PIN_ODR_LOW(GPIOE_PIN13) |                                                    \
540
                                     PIN_ODR_LOW(GPIOE_PIN14) |                                                    \
541
                                     PIN_ODR_LOW(GPIOE_PIN15))
542

    
543
/*
544
 * GPIOF setup:
545
 *
546
 * PF0  - PIN0                      (input floating)
547
 * PF1  - PIN1                      (input floating)
548
 * PF2  - PIN2                      (input floating)
549
 * PF3  - PIN3                      (input floating)
550
 * PF4  - PIN4                      (input floating)
551
 * PF5  - PIN5                      (input floating)
552
 * PF6  - PIN6                      (input floating)
553
 * PF7  - PIN7                      (input floating)
554
 * PF8  - PIN8                      (input floating)
555
 * PF9  - PIN9                      (input floating)
556
 * PF10 - PIN10                     (input floating)
557
 * PF11 - PIN11                     (input floating)
558
 * PF12 - PIN12                     (input floating)
559
 * PF13 - PIN13                     (input floating)
560
 * PF14 - PIN14                     (input floating)
561
 * PF15 - PIN15                     (input floating)
562
 */
563
#define VAL_GPIOFIGN                0
564
#define VAL_GPIOFCRL                (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
565
                                     PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
566
                                     PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
567
                                     PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
568
                                     PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
569
                                     PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
570
                                     PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
571
                                     PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
572
#define VAL_GPIOFCRH                (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
573
                                     PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
574
                                     PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
575
                                     PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
576
                                     PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
577
                                     PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
578
                                     PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
579
                                     PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
580
#define VAL_GPIOFODR                (PIN_ODR_LOW(GPIOF_PIN0) |                                                     \
581
                                     PIN_ODR_LOW(GPIOF_PIN1) |                                                     \
582
                                     PIN_ODR_LOW(GPIOF_PIN2) |                                                     \
583
                                     PIN_ODR_LOW(GPIOF_PIN3) |                                                     \
584
                                     PIN_ODR_LOW(GPIOF_PIN4) |                                                     \
585
                                     PIN_ODR_LOW(GPIOF_PIN5) |                                                     \
586
                                     PIN_ODR_LOW(GPIOF_PIN6) |                                                     \
587
                                     PIN_ODR_LOW(GPIOF_PIN7) |                                                     \
588
                                     PIN_ODR_LOW(GPIOF_PIN8) |                                                     \
589
                                     PIN_ODR_LOW(GPIOF_PIN9) |                                                     \
590
                                     PIN_ODR_LOW(GPIOF_PIN10) |                                                    \
591
                                     PIN_ODR_LOW(GPIOF_PIN11) |                                                    \
592
                                     PIN_ODR_LOW(GPIOF_PIN12) |                                                    \
593
                                     PIN_ODR_LOW(GPIOF_PIN13) |                                                    \
594
                                     PIN_ODR_LOW(GPIOF_PIN14) |                                                    \
595
                                     PIN_ODR_LOW(GPIOF_PIN15))
596

    
597
/*
598
 * GPIOG setup:
599
 *
600
 * PG0  - PIN0                      (input floating)
601
 * PG1  - PIN1                      (input floating)
602
 * PG2  - PIN2                      (input floating)
603
 * PG3  - PIN3                      (input floating)
604
 * PG4  - PIN4                      (input floating)
605
 * PG5  - PIN5                      (input floating)
606
 * PG6  - PIN6                      (input floating)
607
 * PG7  - PIN7                      (input floating)
608
 * PG8  - PIN8                      (input floating)
609
 * PG9  - PIN9                      (input floating)
610
 * PG10 - PIN10                     (input floating)
611
 * PG11 - PIN11                     (input floating)
612
 * PG12 - PIN12                     (input floating)
613
 * PG13 - PIN13                     (input floating)
614
 * PG14 - PIN14                     (input floating)
615
 * PG15 - PIN15                     (input floating)
616
 */
617
#define VAL_GPIOGIGN                0
618
#define VAL_GPIOGCRL                (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
619
                                     PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
620
                                     PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
621
                                     PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
622
                                     PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
623
                                     PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
624
                                     PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
625
                                     PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
626
#define VAL_GPIOGCRH                (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
627
                                     PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                  \
628
                                     PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
629
                                     PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
630
                                     PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
631
                                     PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
632
                                     PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) |                 \
633
                                     PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING))
634
#define VAL_GPIOGODR                (PIN_ODR_LOW(GPIOG_PIN0) |                                                     \
635
                                     PIN_ODR_LOW(GPIOG_PIN1) |                                                     \
636
                                     PIN_ODR_LOW(GPIOG_PIN2) |                                                     \
637
                                     PIN_ODR_LOW(GPIOG_PIN3) |                                                     \
638
                                     PIN_ODR_LOW(GPIOG_PIN4) |                                                     \
639
                                     PIN_ODR_LOW(GPIOG_PIN5) |                                                     \
640
                                     PIN_ODR_LOW(GPIOG_PIN6) |                                                     \
641
                                     PIN_ODR_LOW(GPIOG_PIN7) |                                                     \
642
                                     PIN_ODR_LOW(GPIOG_PIN8) |                                                     \
643
                                     PIN_ODR_LOW(GPIOG_PIN9) |                                                     \
644
                                     PIN_ODR_LOW(GPIOG_PIN10) |                                                    \
645
                                     PIN_ODR_LOW(GPIOG_PIN11) |                                                    \
646
                                     PIN_ODR_LOW(GPIOG_PIN12) |                                                    \
647
                                     PIN_ODR_LOW(GPIOG_PIN13) |                                                    \
648
                                     PIN_ODR_LOW(GPIOG_PIN14) |                                                    \
649
                                     PIN_ODR_LOW(GPIOG_PIN15))
650

    
651
/*===========================================================================*/
652
/* External declarations.                                                    */
653
/*===========================================================================*/
654

    
655
#if !defined(_FROM_ASM_)
656
#ifdef __cplusplus
657
extern "C" {
658
#endif
659
  void boardInit(void);
660
#ifdef __cplusplus
661
}
662
#endif
663
#endif /* _FROM_ASM_ */
664

    
665
#endif /* BOARD_H */
666

    
667
/** @} */