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1 27d0378b Simon Welzel
/*
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    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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    Licensed under the Apache License, Version 2.0 (the "License");
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    you may not use this file except in compliance with the License.
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    You may obtain a copy of the License at
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        http://www.apache.org/licenses/LICENSE-2.0
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    Unless required by applicable law or agreed to in writing, software
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    distributed under the License is distributed on an "AS IS" BASIS,
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    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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    See the License for the specific language governing permissions and
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    limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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 * STM32L1xx drivers configuration.
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 * The following settings override the default settings present in
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 * the various device driver implementation headers.
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 * Note that the settings for each driver only have effect if the whole
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 * driver is enabled in halconf.h.
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 *
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 * IRQ priorities:
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 * 15...0       Lowest...Highest.
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 *
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 * DMA priorities:
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 * 0...3        Lowest...Highest.
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 */
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#define STM32L4xx_MCUCONF
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/*
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 * HAL driver system settings.
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 */
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#define STM32_NO_INIT                       FALSE
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#define STM32_VOS                           STM32_VOS_RANGE1
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#define STM32_PVD_ENABLE                    FALSE
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#define STM32_PLS                           STM32_PLS_LEV0
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#define STM32_HSI16_ENABLED                 FALSE
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#define STM32_LSI_ENABLED                   TRUE
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#define STM32_HSE_ENABLED                   FALSE
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#define STM32_LSE_ENABLED                   TRUE
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#define STM32_MSIPLL_ENABLED                TRUE
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#define STM32_ADC_CLOCK_ENABLED             TRUE
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#define STM32_USB_CLOCK_ENABLED             TRUE
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#define STM32_SAI1_CLOCK_ENABLED            TRUE
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#define STM32_SAI2_CLOCK_ENABLED            TRUE
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#define STM32_MSIRANGE                      STM32_MSIRANGE_4M
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#define STM32_MSISRANGE                     STM32_MSISRANGE_4M
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#define STM32_SW                            STM32_SW_PLL
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#define STM32_PLLSRC                        STM32_PLLSRC_MSI
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#define STM32_PLLM_VALUE                    1
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#define STM32_PLLN_VALUE                    80
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#define STM32_PLLP_VALUE                    7
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#define STM32_PLLQ_VALUE                    6
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#define STM32_PLLR_VALUE                    4
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#define STM32_HPRE                          STM32_HPRE_DIV1
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#define STM32_PPRE1                         STM32_PPRE1_DIV1
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#define STM32_PPRE2                         STM32_PPRE2_DIV1
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#define STM32_STOPWUCK                      STM32_STOPWUCK_MSI
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#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
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#define STM32_PLLSAI1N_VALUE                72
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#define STM32_PLLSAI1P_VALUE                7
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#define STM32_PLLSAI1Q_VALUE                6
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#define STM32_PLLSAI1R_VALUE                6
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#define STM32_PLLSAI2N_VALUE                72
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#define STM32_PLLSAI2P_VALUE                7
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#define STM32_PLLSAI2R_VALUE                6
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#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
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#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
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#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK
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#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK
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#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
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#define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK
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#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK
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#define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK
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#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
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#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1
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#define STM32_SAI1SEL                       STM32_SAI1SEL_OFF
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#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF
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#define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL                        STM32_RTCSEL_LSI
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/*
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 * IRQ system settings.
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 */
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#define STM32_IRQ_EXTI0_PRIORITY            6
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#define STM32_IRQ_EXTI1_PRIORITY            6
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#define STM32_IRQ_EXTI2_PRIORITY            6
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#define STM32_IRQ_EXTI3_PRIORITY            6
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#define STM32_IRQ_EXTI4_PRIORITY            6
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#define STM32_IRQ_EXTI5_9_PRIORITY          6
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#define STM32_IRQ_EXTI10_15_PRIORITY        6
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#define STM32_IRQ_EXTI1635_38_PRIORITY      6
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#define STM32_IRQ_EXTI18_PRIORITY           6
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#define STM32_IRQ_EXTI19_PRIORITY           6
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#define STM32_IRQ_EXTI20_PRIORITY           6
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#define STM32_IRQ_EXTI21_22_PRIORITY        15
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/*
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 * ADC driver system settings.
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 */
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#define STM32_ADC_DUAL_MODE                 FALSE
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#define STM32_ADC_COMPACT_SAMPLES           FALSE
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#define STM32_ADC_USE_ADC1                  FALSE
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#define STM32_ADC_USE_ADC2                  FALSE
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#define STM32_ADC_USE_ADC3                  TRUE // turned on
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#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 2)
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#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(1, 3)
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#define STM32_ADC_ADC1_DMA_PRIORITY         2
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#define STM32_ADC_ADC2_DMA_PRIORITY         2
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#define STM32_ADC_ADC3_DMA_PRIORITY         2
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#define STM32_ADC_ADC12_IRQ_PRIORITY        5
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#define STM32_ADC_ADC3_IRQ_PRIORITY         5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5
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#define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_AHB_DIV1
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/*
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 * CAN driver system settings.
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 */
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#define STM32_CAN_USE_CAN1                  TRUE
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#define STM32_CAN_CAN1_IRQ_PRIORITY         11
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/*
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 * DAC driver system settings.
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 */
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#define STM32_DAC_DUAL_MODE                 FALSE
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#define STM32_DAC_USE_DAC1_CH1              FALSE
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#define STM32_DAC_USE_DAC1_CH2              FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(2, 4)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)
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/*
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 * GPT driver system settings.
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 */
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#define STM32_GPT_USE_TIM1                  FALSE
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#define STM32_GPT_USE_TIM2                  FALSE
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#define STM32_GPT_USE_TIM3                  FALSE
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#define STM32_GPT_USE_TIM4                  FALSE
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#define STM32_GPT_USE_TIM5                  FALSE
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#define STM32_GPT_USE_TIM6                  FALSE
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#define STM32_GPT_USE_TIM7                  FALSE
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#define STM32_GPT_USE_TIM8                  FALSE
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#define STM32_GPT_USE_TIM15                 FALSE
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#define STM32_GPT_USE_TIM16                 FALSE
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#define STM32_GPT_USE_TIM17                 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY         7
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#define STM32_GPT_TIM2_IRQ_PRIORITY         7
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#define STM32_GPT_TIM3_IRQ_PRIORITY         7
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#define STM32_GPT_TIM4_IRQ_PRIORITY         7
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#define STM32_GPT_TIM5_IRQ_PRIORITY         7
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#define STM32_GPT_TIM6_IRQ_PRIORITY         7
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#define STM32_GPT_TIM7_IRQ_PRIORITY         7
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#define STM32_GPT_TIM8_IRQ_PRIORITY         7
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#define STM32_GPT_TIM15_IRQ_PRIORITY        7
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#define STM32_GPT_TIM16_IRQ_PRIORITY        7
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#define STM32_GPT_TIM17_IRQ_PRIORITY        7
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/*
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 * I2C driver system settings.
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 */
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#define STM32_I2C_USE_I2C1                  FALSE
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#define STM32_I2C_USE_I2C2                  FALSE
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#define STM32_I2C_USE_I2C3                  TRUE
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#define STM32_I2C_BUSY_TIMEOUT              50
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#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C1_IRQ_PRIORITY         5
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#define STM32_I2C_I2C2_IRQ_PRIORITY         5
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#define STM32_I2C_I2C3_IRQ_PRIORITY         5
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#define STM32_I2C_I2C1_DMA_PRIORITY         3
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#define STM32_I2C_I2C2_DMA_PRIORITY         3
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#define STM32_I2C_I2C3_DMA_PRIORITY         3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
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/*
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 * ICU driver system settings.
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 */
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#define STM32_ICU_USE_TIM1                  FALSE
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#define STM32_ICU_USE_TIM2                  FALSE
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#define STM32_ICU_USE_TIM3                  FALSE
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#define STM32_ICU_USE_TIM4                  FALSE
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#define STM32_ICU_USE_TIM5                  FALSE
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#define STM32_ICU_USE_TIM8                  FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY         7
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#define STM32_ICU_TIM2_IRQ_PRIORITY         7
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#define STM32_ICU_TIM3_IRQ_PRIORITY         7
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#define STM32_ICU_TIM4_IRQ_PRIORITY         7
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#define STM32_ICU_TIM5_IRQ_PRIORITY         7
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#define STM32_ICU_TIM8_IRQ_PRIORITY         7
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/*
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 * PWM driver system settings.
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 */
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#define STM32_PWM_USE_ADVANCED              FALSE
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#define STM32_PWM_USE_TIM1                  FALSE
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#define STM32_PWM_USE_TIM2                  FALSE
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#define STM32_PWM_USE_TIM3                  FALSE
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#define STM32_PWM_USE_TIM4                  FALSE
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#define STM32_PWM_USE_TIM5                  FALSE
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#define STM32_PWM_USE_TIM8                  FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY         7
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#define STM32_PWM_TIM2_IRQ_PRIORITY         7
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#define STM32_PWM_TIM3_IRQ_PRIORITY         7
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#define STM32_PWM_TIM4_IRQ_PRIORITY         7
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#define STM32_PWM_TIM5_IRQ_PRIORITY         7
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#define STM32_PWM_TIM8_IRQ_PRIORITY         7
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/*
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 * QSPI driver system settings.
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 */
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#define STM32_QSPI_USE_QUADSPI1             FALSE
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#define STM32_QSPI_QUADSPI1_DMA_STREAM      STM32_DMA_STREAM_ID(2, 7)
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/*
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 * SDC driver system settings.
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 */
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#define STM32_SDC_USE_SDMMC1                FALSE
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#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE
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#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000
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#define STM32_SDC_SDMMC_READ_TIMEOUT        1000
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#define STM32_SDC_SDMMC_CLOCK_DELAY         10
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#define STM32_SDC_SDMMC1_DMA_PRIORITY       3
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#define STM32_SDC_SDMMC1_IRQ_PRIORITY       9
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#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID(2, 4)
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/*
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 * SERIAL driver system settings.
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 */
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#define STM32_SERIAL_USE_USART1             FALSE
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#define STM32_SERIAL_USE_USART2             TRUE
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#define STM32_SERIAL_USE_USART3             FALSE
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#define STM32_SERIAL_USE_LPUART1            FALSE
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#define STM32_SERIAL_USART1_PRIORITY        12
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#define STM32_SERIAL_USART2_PRIORITY        12
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#define STM32_SERIAL_USART3_PRIORITY        12
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#define STM32_SERIAL_LPUART1_PRIORITY       12
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/*
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 * SPI driver system settings.
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 */
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#define STM32_SPI_USE_SPI1                  FALSE
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#define STM32_SPI_USE_SPI2                  FALSE
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#define STM32_SPI_USE_SPI3                  FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
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#define STM32_SPI_SPI1_DMA_PRIORITY         1
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#define STM32_SPI_SPI2_DMA_PRIORITY         1
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#define STM32_SPI_SPI3_DMA_PRIORITY         1
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#define STM32_SPI_SPI1_IRQ_PRIORITY         10
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#define STM32_SPI_SPI2_IRQ_PRIORITY         10
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#define STM32_SPI_SPI3_IRQ_PRIORITY         10
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#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
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/*
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 * ST driver system settings.
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 */
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#define STM32_ST_IRQ_PRIORITY               8
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#define STM32_ST_USE_TIMER                  2
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/*
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 * UART driver system settings.
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 */
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#define STM32_UART_USE_USART1               FALSE
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#define STM32_UART_USE_USART2               TRUE
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#define STM32_UART_USE_USART3               FALSE
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#define STM32_UART_USE_UART4                FALSE
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#define STM32_UART_USE_UART5                FALSE
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#define STM32_UART_USE_LPUART1              FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)
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#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
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#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)
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#define STM32_UART_LPUART1_RX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_LPUART1_TX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 6)
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#define STM32_UART_USART1_IRQ_PRIORITY      12
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#define STM32_UART_USART2_IRQ_PRIORITY      12
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#define STM32_UART_USART3_IRQ_PRIORITY      12
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#define STM32_UART_UART4_IRQ_PRIORITY       12
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#define STM32_UART_UART5_IRQ_PRIORITY       12
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#define STM32_UART_USART1_DMA_PRIORITY      0
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#define STM32_UART_USART2_DMA_PRIORITY      0
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#define STM32_UART_USART3_DMA_PRIORITY      0
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#define STM32_UART_UART4_DMA_PRIORITY       0
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#define STM32_UART_UART5_DMA_PRIORITY       0
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#define STM32_UART_LPUART1_DMA_PRIORITY     0
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#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
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/*
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 * USB driver system settings.
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 */
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#define STM32_USB_USE_OTG1                  FALSE
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#define STM32_USB_OTG1_IRQ_PRIORITY         14
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#define STM32_USB_OTG1_RX_FIFO_SIZE         512
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#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
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#define STM32_USB_OTG_THREAD_STACK_SIZE     128
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#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
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/*
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 * WDG driver system settings.
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 */
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#define STM32_WDG_USE_IWDG                  FALSE
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#endif /* MCUCONF_H */