amiro-os / modules / STM32L476RG-NUCLEO64 / mcuconf.h @ 7da800ab
History | View | Annotate | Download (14.4 KB)
1 | 27d0378b | Simon Welzel | /*
|
---|---|---|---|
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License");
|
||
5 | you may not use this file except in compliance with the License.
|
||
6 | You may obtain a copy of the License at
|
||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0
|
||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software
|
||
11 | distributed under the License is distributed on an "AS IS" BASIS,
|
||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
13 | See the License for the specific language governing permissions and
|
||
14 | limitations under the License.
|
||
15 | */
|
||
16 | |||
17 | #ifndef MCUCONF_H
|
||
18 | #define MCUCONF_H
|
||
19 | |||
20 | /*
|
||
21 | * STM32L1xx drivers configuration.
|
||
22 | * The following settings override the default settings present in
|
||
23 | * the various device driver implementation headers.
|
||
24 | * Note that the settings for each driver only have effect if the whole
|
||
25 | * driver is enabled in halconf.h.
|
||
26 | *
|
||
27 | * IRQ priorities:
|
||
28 | * 15...0 Lowest...Highest.
|
||
29 | *
|
||
30 | * DMA priorities:
|
||
31 | * 0...3 Lowest...Highest.
|
||
32 | */
|
||
33 | |||
34 | #define STM32L4xx_MCUCONF
|
||
35 | |||
36 | /*
|
||
37 | * HAL driver system settings.
|
||
38 | */
|
||
39 | #define STM32_NO_INIT FALSE
|
||
40 | #define STM32_VOS STM32_VOS_RANGE1
|
||
41 | #define STM32_PVD_ENABLE FALSE
|
||
42 | #define STM32_PLS STM32_PLS_LEV0
|
||
43 | #define STM32_HSI16_ENABLED FALSE
|
||
44 | #define STM32_LSI_ENABLED TRUE
|
||
45 | #define STM32_HSE_ENABLED FALSE
|
||
46 | #define STM32_LSE_ENABLED TRUE
|
||
47 | #define STM32_MSIPLL_ENABLED TRUE
|
||
48 | #define STM32_ADC_CLOCK_ENABLED TRUE
|
||
49 | #define STM32_USB_CLOCK_ENABLED TRUE
|
||
50 | #define STM32_SAI1_CLOCK_ENABLED TRUE
|
||
51 | #define STM32_SAI2_CLOCK_ENABLED TRUE
|
||
52 | #define STM32_MSIRANGE STM32_MSIRANGE_4M
|
||
53 | #define STM32_MSISRANGE STM32_MSISRANGE_4M
|
||
54 | #define STM32_SW STM32_SW_PLL
|
||
55 | #define STM32_PLLSRC STM32_PLLSRC_MSI
|
||
56 | #define STM32_PLLM_VALUE 1 |
||
57 | #define STM32_PLLN_VALUE 80 |
||
58 | #define STM32_PLLP_VALUE 7 |
||
59 | #define STM32_PLLQ_VALUE 6 |
||
60 | #define STM32_PLLR_VALUE 4 |
||
61 | #define STM32_HPRE STM32_HPRE_DIV1
|
||
62 | #define STM32_PPRE1 STM32_PPRE1_DIV1
|
||
63 | #define STM32_PPRE2 STM32_PPRE2_DIV1
|
||
64 | #define STM32_STOPWUCK STM32_STOPWUCK_MSI
|
||
65 | #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||
66 | #define STM32_MCOPRE STM32_MCOPRE_DIV1
|
||
67 | #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
|
||
68 | #define STM32_PLLSAI1N_VALUE 72 |
||
69 | #define STM32_PLLSAI1P_VALUE 7 |
||
70 | #define STM32_PLLSAI1Q_VALUE 6 |
||
71 | #define STM32_PLLSAI1R_VALUE 6 |
||
72 | #define STM32_PLLSAI2N_VALUE 72 |
||
73 | #define STM32_PLLSAI2P_VALUE 7 |
||
74 | #define STM32_PLLSAI2R_VALUE 6 |
||
75 | #define STM32_USART1SEL STM32_USART1SEL_SYSCLK
|
||
76 | #define STM32_USART2SEL STM32_USART2SEL_SYSCLK
|
||
77 | #define STM32_USART3SEL STM32_USART3SEL_SYSCLK
|
||
78 | #define STM32_UART4SEL STM32_UART4SEL_SYSCLK
|
||
79 | #define STM32_UART5SEL STM32_UART5SEL_SYSCLK
|
||
80 | #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
|
||
81 | #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
|
||
82 | #define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
|
||
83 | #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
|
||
84 | #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
|
||
85 | #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
|
||
86 | #define STM32_SAI1SEL STM32_SAI1SEL_OFF
|
||
87 | #define STM32_SAI2SEL STM32_SAI2SEL_OFF
|
||
88 | #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
|
||
89 | #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
|
||
90 | #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
|
||
91 | #define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
|
||
92 | #define STM32_RTCSEL STM32_RTCSEL_LSI
|
||
93 | |||
94 | /*
|
||
95 | * IRQ system settings.
|
||
96 | */
|
||
97 | #define STM32_IRQ_EXTI0_PRIORITY 6 |
||
98 | #define STM32_IRQ_EXTI1_PRIORITY 6 |
||
99 | #define STM32_IRQ_EXTI2_PRIORITY 6 |
||
100 | #define STM32_IRQ_EXTI3_PRIORITY 6 |
||
101 | #define STM32_IRQ_EXTI4_PRIORITY 6 |
||
102 | #define STM32_IRQ_EXTI5_9_PRIORITY 6 |
||
103 | #define STM32_IRQ_EXTI10_15_PRIORITY 6 |
||
104 | #define STM32_IRQ_EXTI1635_38_PRIORITY 6 |
||
105 | #define STM32_IRQ_EXTI18_PRIORITY 6 |
||
106 | #define STM32_IRQ_EXTI19_PRIORITY 6 |
||
107 | #define STM32_IRQ_EXTI20_PRIORITY 6 |
||
108 | #define STM32_IRQ_EXTI21_22_PRIORITY 15 |
||
109 | |||
110 | /*
|
||
111 | * ADC driver system settings.
|
||
112 | */
|
||
113 | #define STM32_ADC_DUAL_MODE FALSE
|
||
114 | #define STM32_ADC_COMPACT_SAMPLES FALSE
|
||
115 | #define STM32_ADC_USE_ADC1 FALSE
|
||
116 | #define STM32_ADC_USE_ADC2 FALSE
|
||
117 | 1678f270 | Simon Welzel | #define STM32_ADC_USE_ADC3 TRUE // turned on |
118 | 27d0378b | Simon Welzel | #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
119 | #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
||
120 | #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
||
121 | #define STM32_ADC_ADC1_DMA_PRIORITY 2 |
||
122 | #define STM32_ADC_ADC2_DMA_PRIORITY 2 |
||
123 | #define STM32_ADC_ADC3_DMA_PRIORITY 2 |
||
124 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
||
125 | #define STM32_ADC_ADC3_IRQ_PRIORITY 5 |
||
126 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
||
127 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
||
128 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
||
129 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||
130 | |||
131 | /*
|
||
132 | * CAN driver system settings.
|
||
133 | */
|
||
134 | #define STM32_CAN_USE_CAN1 TRUE
|
||
135 | #define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
||
136 | |||
137 | /*
|
||
138 | * DAC driver system settings.
|
||
139 | */
|
||
140 | #define STM32_DAC_DUAL_MODE FALSE
|
||
141 | #define STM32_DAC_USE_DAC1_CH1 FALSE
|
||
142 | #define STM32_DAC_USE_DAC1_CH2 FALSE
|
||
143 | #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
||
144 | #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
||
145 | #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
||
146 | #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
||
147 | #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
||
148 | #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
||
149 | |||
150 | /*
|
||
151 | * GPT driver system settings.
|
||
152 | */
|
||
153 | #define STM32_GPT_USE_TIM1 FALSE
|
||
154 | #define STM32_GPT_USE_TIM2 FALSE
|
||
155 | #define STM32_GPT_USE_TIM3 FALSE
|
||
156 | #define STM32_GPT_USE_TIM4 FALSE
|
||
157 | #define STM32_GPT_USE_TIM5 FALSE
|
||
158 | #define STM32_GPT_USE_TIM6 FALSE
|
||
159 | #define STM32_GPT_USE_TIM7 FALSE
|
||
160 | #define STM32_GPT_USE_TIM8 FALSE
|
||
161 | #define STM32_GPT_USE_TIM15 FALSE
|
||
162 | #define STM32_GPT_USE_TIM16 FALSE
|
||
163 | #define STM32_GPT_USE_TIM17 FALSE
|
||
164 | #define STM32_GPT_TIM1_IRQ_PRIORITY 7 |
||
165 | #define STM32_GPT_TIM2_IRQ_PRIORITY 7 |
||
166 | #define STM32_GPT_TIM3_IRQ_PRIORITY 7 |
||
167 | #define STM32_GPT_TIM4_IRQ_PRIORITY 7 |
||
168 | #define STM32_GPT_TIM5_IRQ_PRIORITY 7 |
||
169 | #define STM32_GPT_TIM6_IRQ_PRIORITY 7 |
||
170 | #define STM32_GPT_TIM7_IRQ_PRIORITY 7 |
||
171 | #define STM32_GPT_TIM8_IRQ_PRIORITY 7 |
||
172 | #define STM32_GPT_TIM15_IRQ_PRIORITY 7 |
||
173 | #define STM32_GPT_TIM16_IRQ_PRIORITY 7 |
||
174 | #define STM32_GPT_TIM17_IRQ_PRIORITY 7 |
||
175 | |||
176 | /*
|
||
177 | * I2C driver system settings.
|
||
178 | */
|
||
179 | #define STM32_I2C_USE_I2C1 FALSE
|
||
180 | #define STM32_I2C_USE_I2C2 FALSE
|
||
181 | 1678f270 | Simon Welzel | #define STM32_I2C_USE_I2C3 TRUE
|
182 | 27d0378b | Simon Welzel | #define STM32_I2C_BUSY_TIMEOUT 50 |
183 | #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
||
184 | #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
||
185 | #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
||
186 | #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
||
187 | #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
||
188 | #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
||
189 | #define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
||
190 | #define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
||
191 | #define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
||
192 | #define STM32_I2C_I2C1_DMA_PRIORITY 3 |
||
193 | #define STM32_I2C_I2C2_DMA_PRIORITY 3 |
||
194 | #define STM32_I2C_I2C3_DMA_PRIORITY 3 |
||
195 | #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
||
196 | |||
197 | /*
|
||
198 | * ICU driver system settings.
|
||
199 | */
|
||
200 | #define STM32_ICU_USE_TIM1 FALSE
|
||
201 | #define STM32_ICU_USE_TIM2 FALSE
|
||
202 | #define STM32_ICU_USE_TIM3 FALSE
|
||
203 | #define STM32_ICU_USE_TIM4 FALSE
|
||
204 | #define STM32_ICU_USE_TIM5 FALSE
|
||
205 | #define STM32_ICU_USE_TIM8 FALSE
|
||
206 | #define STM32_ICU_TIM1_IRQ_PRIORITY 7 |
||
207 | #define STM32_ICU_TIM2_IRQ_PRIORITY 7 |
||
208 | #define STM32_ICU_TIM3_IRQ_PRIORITY 7 |
||
209 | #define STM32_ICU_TIM4_IRQ_PRIORITY 7 |
||
210 | #define STM32_ICU_TIM5_IRQ_PRIORITY 7 |
||
211 | #define STM32_ICU_TIM8_IRQ_PRIORITY 7 |
||
212 | |||
213 | /*
|
||
214 | * PWM driver system settings.
|
||
215 | */
|
||
216 | #define STM32_PWM_USE_ADVANCED FALSE
|
||
217 | #define STM32_PWM_USE_TIM1 FALSE
|
||
218 | #define STM32_PWM_USE_TIM2 FALSE
|
||
219 | #define STM32_PWM_USE_TIM3 FALSE
|
||
220 | #define STM32_PWM_USE_TIM4 FALSE
|
||
221 | #define STM32_PWM_USE_TIM5 FALSE
|
||
222 | #define STM32_PWM_USE_TIM8 FALSE
|
||
223 | #define STM32_PWM_TIM1_IRQ_PRIORITY 7 |
||
224 | #define STM32_PWM_TIM2_IRQ_PRIORITY 7 |
||
225 | #define STM32_PWM_TIM3_IRQ_PRIORITY 7 |
||
226 | #define STM32_PWM_TIM4_IRQ_PRIORITY 7 |
||
227 | #define STM32_PWM_TIM5_IRQ_PRIORITY 7 |
||
228 | #define STM32_PWM_TIM8_IRQ_PRIORITY 7 |
||
229 | |||
230 | /*
|
||
231 | * QSPI driver system settings.
|
||
232 | */
|
||
233 | #define STM32_QSPI_USE_QUADSPI1 FALSE
|
||
234 | #define STM32_QSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
||
235 | |||
236 | /*
|
||
237 | * SDC driver system settings.
|
||
238 | */
|
||
239 | #define STM32_SDC_USE_SDMMC1 FALSE
|
||
240 | #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
|
||
241 | #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 |
||
242 | #define STM32_SDC_SDMMC_READ_TIMEOUT 1000 |
||
243 | #define STM32_SDC_SDMMC_CLOCK_DELAY 10 |
||
244 | #define STM32_SDC_SDMMC1_DMA_PRIORITY 3 |
||
245 | #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 |
||
246 | #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
||
247 | |||
248 | /*
|
||
249 | * SERIAL driver system settings.
|
||
250 | */
|
||
251 | #define STM32_SERIAL_USE_USART1 FALSE
|
||
252 | #define STM32_SERIAL_USE_USART2 TRUE
|
||
253 | #define STM32_SERIAL_USE_USART3 FALSE
|
||
254 | #define STM32_SERIAL_USE_LPUART1 FALSE
|
||
255 | #define STM32_SERIAL_USART1_PRIORITY 12 |
||
256 | #define STM32_SERIAL_USART2_PRIORITY 12 |
||
257 | #define STM32_SERIAL_USART3_PRIORITY 12 |
||
258 | #define STM32_SERIAL_LPUART1_PRIORITY 12 |
||
259 | |||
260 | /*
|
||
261 | * SPI driver system settings.
|
||
262 | */
|
||
263 | #define STM32_SPI_USE_SPI1 FALSE
|
||
264 | #define STM32_SPI_USE_SPI2 FALSE
|
||
265 | #define STM32_SPI_USE_SPI3 FALSE
|
||
266 | #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
||
267 | #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
||
268 | #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
||
269 | #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
||
270 | #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
||
271 | #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
||
272 | #define STM32_SPI_SPI1_DMA_PRIORITY 1 |
||
273 | #define STM32_SPI_SPI2_DMA_PRIORITY 1 |
||
274 | #define STM32_SPI_SPI3_DMA_PRIORITY 1 |
||
275 | #define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
||
276 | #define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
||
277 | #define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
||
278 | #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
||
279 | |||
280 | /*
|
||
281 | * ST driver system settings.
|
||
282 | */
|
||
283 | #define STM32_ST_IRQ_PRIORITY 8 |
||
284 | #define STM32_ST_USE_TIMER 2 |
||
285 | |||
286 | /*
|
||
287 | * UART driver system settings.
|
||
288 | */
|
||
289 | #define STM32_UART_USE_USART1 FALSE
|
||
290 | #define STM32_UART_USE_USART2 TRUE
|
||
291 | #define STM32_UART_USE_USART3 FALSE
|
||
292 | #define STM32_UART_USE_UART4 FALSE
|
||
293 | #define STM32_UART_USE_UART5 FALSE
|
||
294 | #define STM32_UART_USE_LPUART1 FALSE
|
||
295 | #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
||
296 | #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) |
||
297 | #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
||
298 | #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
||
299 | #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
||
300 | #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
||
301 | #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) |
||
302 | #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
||
303 | #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
||
304 | #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
||
305 | #define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
||
306 | #define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) |
||
307 | #define STM32_UART_USART1_IRQ_PRIORITY 12 |
||
308 | #define STM32_UART_USART2_IRQ_PRIORITY 12 |
||
309 | #define STM32_UART_USART3_IRQ_PRIORITY 12 |
||
310 | #define STM32_UART_UART4_IRQ_PRIORITY 12 |
||
311 | #define STM32_UART_UART5_IRQ_PRIORITY 12 |
||
312 | #define STM32_UART_USART1_DMA_PRIORITY 0 |
||
313 | #define STM32_UART_USART2_DMA_PRIORITY 0 |
||
314 | #define STM32_UART_USART3_DMA_PRIORITY 0 |
||
315 | #define STM32_UART_UART4_DMA_PRIORITY 0 |
||
316 | #define STM32_UART_UART5_DMA_PRIORITY 0 |
||
317 | #define STM32_UART_LPUART1_DMA_PRIORITY 0 |
||
318 | #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
||
319 | |||
320 | /*
|
||
321 | * USB driver system settings.
|
||
322 | */
|
||
323 | #define STM32_USB_USE_OTG1 FALSE
|
||
324 | #define STM32_USB_OTG1_IRQ_PRIORITY 14 |
||
325 | #define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
||
326 | #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||
327 | #define STM32_USB_OTG_THREAD_STACK_SIZE 128 |
||
328 | #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 |
||
329 | |||
330 | /*
|
||
331 | * WDG driver system settings.
|
||
332 | */
|
||
333 | #define STM32_WDG_USE_IWDG FALSE
|
||
334 | |||
335 | 7da800ab | Thomas Schöpping | /*
|
336 | * QEI driver system settings.
|
||
337 | */
|
||
338 | #define STM32_QEI_USE_TIM1 FALSE
|
||
339 | #define STM32_QEI_USE_TIM2 FALSE
|
||
340 | #define STM32_QEI_USE_TIM3 FALSE
|
||
341 | #define STM32_QEI_USE_TIM4 FALSE
|
||
342 | #define STM32_QEI_USE_TIM5 FALSE
|
||
343 | #define STM32_QEI_USE_TIM8 FALSE
|
||
344 | |||
345 | 27d0378b | Simon Welzel | #endif /* MCUCONF_H */ |