amiro-os / kernel / patches / Introduced-I2C-without-DMA.patch @ 870f74ac
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From 736d3be25b7389b6130e0c372328aa56e2532250 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Thomas=20Sch=C3=B6pping?= <tschoepp@cit-ec.uni-bielefeld.de>
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Date: Mon, 12 Jun 2017 17:28:49 +0200
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Subject: [PATCH] Introduced I2C without DMA (I2Cv1 only).
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---
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os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c | 181 ++++++++++++++++++++++++++++- |
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os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h | 30 +++++ |
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2 files changed, 210 insertions(+), 1 deletion(-) |
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diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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index 20b8cf8..b2cfb59 100644
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--- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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+++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
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@@ -34,6 +34,7 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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+#if STM32_I2C_USE_DMA
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#define I2C1_RX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_CHN) |
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@@ -57,6 +58,7 @@
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#define I2C3_TX_DMA_CHANNEL \ |
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_CHN) |
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+#endif /* STM32_I2C_USE_DMA */
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/*===========================================================================*/
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/* Driver constants. */
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@@ -72,6 +74,20 @@
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#define I2C_EV6_MASTER_REC_MODE_SELECTED \ |
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((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))
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|
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+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_RXNE))
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+
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+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP \
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+ ((uint32_t)( I2C_SR1_RXNE))
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+
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+#define I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | \
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+ I2C_SR1_BTF | I2C_SR1_RXNE))
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+
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+#define I2C_EV8_MASTER_BYTE_TRANSMITTING \
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+ ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)<< 16) | \
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+ I2C_SR1_TXE))
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+
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ |
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((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ |
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I2C_SR1_BTF | I2C_SR1_TXE)) |
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@@ -128,9 +144,11 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) { |
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dp->CR2 = 0;
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dp->SR1 = 0;
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+#if STM32_I2C_USE_DMA
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/* Stops the associated DMA streams.*/
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dmaStreamDisable(i2cp->dmatx); |
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dmaStreamDisable(i2cp->dmarx); |
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+#endif /* STM32_I2C_USE_DMA */
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} |
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/**
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@@ -247,12 +265,13 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { |
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uint32_t regSR2 = dp->SR2; |
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uint32_t event = dp->SR1; |
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|
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+#if STM32_I2C_USE_DMA
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/* Interrupts are disabled just before dmaStreamEnable() because there
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is no need of interrupts until next transaction begin. All the work is |
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done by the DMA.*/ |
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switch (I2C_EV_MASK & (event | (regSR2 << 16))) { |
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case I2C_EV5_MASTER_MODE_SELECT:
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- if ((i2cp->addr >> 8) > 0) {
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+ if ((i2cp->addr >> 8) > 0) {
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/* 10-bit address: 1 1 1 1 0 X X R/W */
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dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); |
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} else {
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@@ -292,8 +311,125 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { |
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/* Clear ADDR flag. */
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if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
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(void)dp->SR2;
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+#else
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+ switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
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+ case I2C_EV5_MASTER_MODE_SELECT:
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+ dp->CR2 |= I2C_CR2_ITBUFEN;
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+ dp->DR = i2cp->addr;
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+ break;
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+ case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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+ (void)dp->SR2; // clear ADDR flag
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+ /* EV8_1 */
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+ dp->DR = *(i2cp->txbuf);
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+
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+ ++i2cp->txbuf;
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+ --i2cp->txbytes;
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+
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+ /* if N == 1, skip the I2C_EV8_MASTER_BYTE_TRANSMITTING event
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+ * but enter I2C_EV8_2_MASTER_BYTE_TRANSMITTED next */
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+ if (i2cp->txbytes == 0) {
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV6_MASTER_REC_MODE_SELECTED:
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+ switch (i2cp->rxbytes) {
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+ case 1:
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ (void)dp->SR2; // clear ADDR flag
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+ dp->CR1 |= I2C_CR1_STOP;
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+ break;
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+ case 2:
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+ (void)dp->SR2; // clear ADDR flag
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+ /* EV6_1 */
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+ dp->CR1 |= I2C_CR1_POS;
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ break;
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+ case 3: /* N == 3 is a very special case, since EV7 is completely skipped */
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+ (void)dp->SR2; // clear ADDR flag
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+ /* Disable the I2C_EV7_MASTER_REC_BYTE_RECEIVED event
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+ * but enter I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP next */
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ break;
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+ default: /* N > 2 */
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+ (void)dp->SR2; // clear ADDR flag
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+ break;
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+ }
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+ break;
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+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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+ if (i2cp->rxbytes > 3) {
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ --i2cp->rxbytes;
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+ }
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+ if (i2cp->rxbytes == 3) {
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+ /* Disable this event for DataN-2, but force into event
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+ * I2C_EV7_2_EV7_3_MASTER_REC_BYTE_RECEIVED_QUEUED by not reading dp->DR. */
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP:
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+ osalDbgAssert(i2cp->rxbytes == 1, "more than 1 byte to be received");
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+ *(i2cp->rxbuf) = dp->DR;
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+ --i2cp->rxbytes;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+ _i2c_wakeup_isr(i2cp);
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+ break;
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+ case I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED:
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+ if (i2cp->rxbytes == 3) {
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+ /* EV7_2 (N > 2) */
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+ dp->CR1 &= ~I2C_CR1_ACK;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ dp->CR1 |= I2C_CR1_STOP;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ i2cp->rxbytes -= 2;
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+ /* enable I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP event */
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+ dp->CR2 |= I2C_CR2_ITBUFEN;
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+ } else {
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+ /* EV7_3 (N == 2) */
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+ dp->CR1 |= I2C_CR1_STOP;
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+ *(i2cp->rxbuf) = dp->DR;
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+ ++i2cp->rxbuf;
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+ *(i2cp->rxbuf) = dp->DR;
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+ i2cp->rxbytes -= 2;
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+
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+ dp->CR1 &= ~I2C_CR1_POS;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+
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+ _i2c_wakeup_isr(i2cp);
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+ }
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+ break;
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+ case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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+ dp->DR = *(i2cp->txbuf);
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+ ++i2cp->txbuf;
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+ --i2cp->txbytes;
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+
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+ /* if this was the last byte, ensure that this event is not entered again */
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+ if (i2cp->txbytes == 0) {
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+ dp->CR2 &= ~I2C_CR2_ITBUFEN;
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+ }
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+ break;
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+ case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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+ if (i2cp->rxbytes > 0) {
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+ /* start "read after write" operation (LSB of address = 1 => read) */
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+ i2cp->addr |= 0x01;
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+ dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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+ } else {
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+ dp->CR1 |= I2C_CR1_STOP;
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+ dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
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+ _i2c_wakeup_isr(i2cp);
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+ }
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+ break;
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+ default:
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+ osalDbgAssert(i2cp->rxbytes != 1, "more than 1 byte to be received");
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+ break;
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+ }
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+#endif /* STM32_I2C_USE_DMA */
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} |
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+#if STM32_I2C_USE_DMA
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/**
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* @brief DMA RX end IRQ handler.
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* |
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@@ -347,6 +483,7 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { |
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of R/W transaction itself.*/ |
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dp->CR2 |= I2C_CR2_ITEVTEN; |
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} |
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+#endif /* STM32_I2C_USE_DMA */
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/**
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* @brief I2C error handler.
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@@ -358,9 +495,11 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { |
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*/ |
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static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { |
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+#if STM32_I2C_USE_DMA
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/* Clears interrupt flags just to be safe.*/
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dmaStreamDisable(i2cp->dmatx); |
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dmaStreamDisable(i2cp->dmarx); |
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+#endif /* STM32_I2C_USE_DMA */
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i2cp->errors = I2C_NO_ERROR; |
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@@ -506,24 +645,30 @@ void i2c_lld_init(void) { |
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i2cObjectInit(&I2CD1); |
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I2CD1.thread = NULL;
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I2CD1.i2c = I2C1; |
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+#if STM32_I2C_USE_DMA
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I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); |
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I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); |
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+#endif /* STM32_I2C_USE_DMA */
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#endif /* STM32_I2C_USE_I2C1 */ |
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#if STM32_I2C_USE_I2C2
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i2cObjectInit(&I2CD2); |
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I2CD2.thread = NULL;
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I2CD2.i2c = I2C2; |
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+#if STM32_I2C_USE_DMA
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I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); |
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I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); |
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+#endif /* STM32_I2C_USE_DMA */
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#endif /* STM32_I2C_USE_I2C2 */ |
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#if STM32_I2C_USE_I2C3
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i2cObjectInit(&I2CD3); |
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I2CD3.thread = NULL;
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I2CD3.i2c = I2C3; |
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+#if STM32_I2C_USE_DMA
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I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); |
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I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); |
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+#endif /* STM32_I2C_USE_DMA */
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#endif /* STM32_I2C_USE_I2C3 */ |
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} |
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@@ -540,6 +685,7 @@ void i2c_lld_start(I2CDriver *i2cp) { |
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/* If in stopped state then enables the I2C and DMA clocks.*/
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if (i2cp->state == I2C_STOP) {
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+#if STM32_I2C_USE_DMA
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i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | |
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STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | |
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STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | |
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@@ -548,9 +694,11 @@ void i2c_lld_start(I2CDriver *i2cp) { |
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STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | |
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STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | |
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STM32_DMA_CR_DIR_P2M; |
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+#endif /* STM32_I2C_USE_DMA */
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|
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#if STM32_I2C_USE_I2C1
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if (&I2CD1 == i2cp) {
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+#if STM32_I2C_USE_DMA
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bool b;
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rccResetI2C1(); |
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@@ -564,19 +712,23 @@ void i2c_lld_start(I2CDriver *i2cp) { |
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(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, |
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(void *)i2cp);
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osalDbgAssert(!b, "stream already allocated");
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+#endif /* STM32_I2C_USE_DMA */
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rccEnableI2C1(FALSE); |
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nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); |
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nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); |
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|
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+#if STM32_I2C_USE_DMA
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); |
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i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); |
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+#endif /* STM32_I2C_USE_DMA */
|
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} |
| 292 |
#endif /* STM32_I2C_USE_I2C1 */ |
| 293 |
|
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#if STM32_I2C_USE_I2C2
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if (&I2CD2 == i2cp) {
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+#if STM32_I2C_USE_DMA
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bool b;
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|
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rccResetI2C2(); |
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@@ -590,19 +742,23 @@ void i2c_lld_start(I2CDriver *i2cp) { |
| 301 |
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, |
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(void *)i2cp);
|
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osalDbgAssert(!b, "stream already allocated");
|
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+#endif /* STM32_I2C_USE_DMA */
|
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rccEnableI2C2(FALSE); |
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nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); |
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nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); |
| 308 |
|
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+#if STM32_I2C_USE_DMA
|
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); |
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i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); |
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+#endif /* STM32_I2C_USE_DMA */
|
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} |
| 316 |
#endif /* STM32_I2C_USE_I2C2 */ |
| 317 |
|
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#if STM32_I2C_USE_I2C3
|
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if (&I2CD3 == i2cp) {
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+#if STM32_I2C_USE_DMA
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bool b;
|
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|
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rccResetI2C3(); |
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@@ -616,26 +772,35 @@ void i2c_lld_start(I2CDriver *i2cp) { |
| 325 |
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, |
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(void *)i2cp);
|
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osalDbgAssert(!b, "stream already allocated");
|
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+#endif /* STM32_I2C_USE_DMA */
|
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rccEnableI2C3(FALSE); |
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nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); |
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nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); |
| 332 |
|
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+#if STM32_I2C_USE_DMA
|
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i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); |
| 336 |
i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) | |
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STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); |
| 338 |
+#endif /* STM32_I2C_USE_DMA */
|
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} |
| 340 |
#endif /* STM32_I2C_USE_I2C3 */ |
| 341 |
} |
| 342 |
|
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+#if STM32_I2C_USE_DMA
|
| 344 |
/* I2C registers pointed by the DMA.*/
|
| 345 |
dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); |
| 346 |
dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); |
| 347 |
+#endif /* STM32_I2C_USE_DMA */
|
| 348 |
|
| 349 |
/* Reset i2c peripheral.*/
|
| 350 |
dp->CR1 = I2C_CR1_SWRST; |
| 351 |
dp->CR1 = 0;
|
| 352 |
+#if STM32_I2C_USE_DMA
|
| 353 |
dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN; |
| 354 |
+#else
|
| 355 |
+ dp->CR2 = I2C_CR2_ITERREN;
|
| 356 |
+#endif /* STM32_I2C_USE_DMA */
|
| 357 |
|
| 358 |
/* Setup I2C parameters.*/
|
| 359 |
i2c_lld_set_clock(i2cp); |
| 360 |
@@ -659,8 +824,10 @@ void i2c_lld_stop(I2CDriver *i2cp) { |
| 361 |
|
| 362 |
/* I2C disable.*/
|
| 363 |
i2c_lld_abort_operation(i2cp); |
| 364 |
+#if STM32_I2C_USE_DMA
|
| 365 |
dmaStreamRelease(i2cp->dmatx); |
| 366 |
dmaStreamRelease(i2cp->dmarx); |
| 367 |
+#endif /* STM32_I2C_USE_DMA */
|
| 368 |
|
| 369 |
#if STM32_I2C_USE_I2C1
|
| 370 |
if (&I2CD1 == i2cp) {
|
| 371 |
@@ -730,10 +897,15 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
| 372 |
/* Releases the lock from high level driver.*/
|
| 373 |
osalSysUnlock(); |
| 374 |
|
| 375 |
+#if STM32_I2C_USE_DMA
|
| 376 |
/* RX DMA setup.*/
|
| 377 |
dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); |
| 378 |
dmaStreamSetMemory0(i2cp->dmarx, rxbuf); |
| 379 |
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); |
| 380 |
+#else
|
| 381 |
+ i2cp->rxbuf = rxbuf;
|
| 382 |
+ i2cp->rxbytes = rxbytes;
|
| 383 |
+#endif /* STM32_I2C_USE_DMA */
|
| 384 |
|
| 385 |
/* Calculating the time window for the timeout on the busy bus condition.*/
|
| 386 |
start = osalOsGetSystemTimeX(); |
| 387 |
@@ -810,6 +982,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
| 388 |
/* Releases the lock from high level driver.*/
|
| 389 |
osalSysUnlock(); |
| 390 |
|
| 391 |
+#if STM32_I2C_USE_DMA
|
| 392 |
/* TX DMA setup.*/
|
| 393 |
dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); |
| 394 |
dmaStreamSetMemory0(i2cp->dmatx, txbuf); |
| 395 |
@@ -819,6 +992,12 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
| 396 |
dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); |
| 397 |
dmaStreamSetMemory0(i2cp->dmarx, rxbuf); |
| 398 |
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); |
| 399 |
+#else
|
| 400 |
+ i2cp->txbuf = txbuf;
|
| 401 |
+ i2cp->txbytes = txbytes;
|
| 402 |
+ i2cp->rxbuf = rxbuf;
|
| 403 |
+ i2cp->rxbytes = rxbytes;
|
| 404 |
+#endif /* STM32_I2C_USE_DMA */
|
| 405 |
|
| 406 |
/* Calculating the time window for the timeout on the busy bus condition.*/
|
| 407 |
start = osalOsGetSystemTimeX(); |
| 408 |
diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
|
| 409 |
index a812ceb..127c708 100644
|
| 410 |
--- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
|
| 411 |
+++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.h
|
| 412 |
@@ -76,6 +76,15 @@
|
| 413 |
#endif
|
| 414 |
|
| 415 |
/**
|
| 416 |
+ * @brief I2C data transfer use dma switch.
|
| 417 |
+ * @details If set to @p TRUE the support for I2C DMA is included.
|
| 418 |
+ * @note The default is @p FALSE.
|
| 419 |
+ */
|
| 420 |
+#if !defined(STM32_I2C_USE_DMA) || defined(__DOXYGEN__)
|
| 421 |
+#define STM32_I2C_USE_DMA TRUE
|
| 422 |
+#endif
|
| 423 |
+
|
| 424 |
+/**
|
| 425 |
* @brief I2C timeout on busy condition in milliseconds.
|
| 426 |
*/ |
| 427 |
#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
|
| 428 |
@@ -249,6 +258,7 @@
|
| 429 |
#error "Invalid IRQ priority assigned to I2C3" |
| 430 |
#endif
|
| 431 |
|
| 432 |
+#if STM32_I2C_USE_DMA
|
| 433 |
#if STM32_I2C_USE_I2C1 && \ |
| 434 |
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY) |
| 435 |
#error "Invalid DMA priority assigned to I2C1" |
| 436 |
@@ -319,6 +329,7 @@
|
| 437 |
#if !defined(STM32_DMA_REQUIRED)
|
| 438 |
#define STM32_DMA_REQUIRED
|
| 439 |
#endif
|
| 440 |
+#endif /* STM32_I2C_USE_DMA */
|
| 441 |
|
| 442 |
/* Check clock range. */
|
| 443 |
#if defined(STM32F4XX)
|
| 444 |
@@ -436,6 +447,7 @@ struct I2CDriver { |
| 445 |
* @brief Current slave address without R/W bit.
|
| 446 |
*/ |
| 447 |
i2caddr_t addr; |
| 448 |
+#if STM32_I2C_USE_DMA
|
| 449 |
/**
|
| 450 |
* @brief RX DMA mode bit mask.
|
| 451 |
*/ |
| 452 |
@@ -452,6 +464,24 @@ struct I2CDriver { |
| 453 |
* @brief Transmit DMA channel.
|
| 454 |
*/ |
| 455 |
const stm32_dma_stream_t *dmatx;
|
| 456 |
+#else
|
| 457 |
+ /**
|
| 458 |
+ * @brief Receive buffer.
|
| 459 |
+ */
|
| 460 |
+ uint8_t *rxbuf;
|
| 461 |
+ /**
|
| 462 |
+ * @brief Receive buffer size.
|
| 463 |
+ */
|
| 464 |
+ size_t rxbytes;
|
| 465 |
+ /**
|
| 466 |
+ * @brief Transmit buffer.
|
| 467 |
+ */
|
| 468 |
+ const uint8_t *txbuf;
|
| 469 |
+ /**
|
| 470 |
+ * @brief Transmit buffer size.
|
| 471 |
+ */
|
| 472 |
+ size_t txbytes;
|
| 473 |
+#endif /* STM32_I2C_USE_DMA */
|
| 474 |
/**
|
| 475 |
* @brief Pointer to the I2Cx registers block.
|
| 476 |
*/ |
| 477 |
--
|
| 478 |
2.7.4
|
| 479 |
|