Revision 88f4bcc5
| modules/NUCLEO-L476RG/Makefile | ||
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################################################################################ |
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# AMiRo-OS is an operating system designed for the Autonomous Mini Robot # |
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# (AMiRo) platform. # |
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# Copyright (C) 2016..2019 Thomas Schöpping et al. # |
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# # |
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# This program is free software: you can redistribute it and/or modify # |
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# it under the terms of the GNU General Public License as published by # |
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# the Free Software Foundation, either version 3 of the License, or # |
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# (at your option) any later version. # |
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# # |
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# This program is distributed in the hope that it will be useful, # |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of # |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # |
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# GNU General Public License for more details. # |
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# # |
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# You should have received a copy of the GNU General Public License # |
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# along with this program. If not, see <http://www.gnu.org/licenses/>. # |
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# # |
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# This research/work was supported by the Cluster of Excellence Cognitive # |
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# Interaction Technology 'CITEC' (EXC 277) at Bielefeld University, which is # |
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# funded by the German Research Foundation (DFG). # |
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################################################################################ |
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################################################################################ |
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# Build global options # |
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# NOTE: Can be overridden externally. # |
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# # |
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# Compiler options here. |
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ifeq ($(USE_OPT),) |
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USE_OPT = -O2 -fomit-frame-pointer -falign-functions=16 -fstack-usage |
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endif |
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# C specific options here (added to USE_OPT). |
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ifeq ($(USE_COPT),) |
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USE_COPT = -std=c11 |
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endif |
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# C++ specific options here (added to USE_OPT). |
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ifeq ($(USE_CPPOPT),) |
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USE_CPPOPT = -fno-rtti -std=c++17 |
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endif |
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# Enable this if you want the linker to remove unused code and data |
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ifeq ($(USE_LINK_GC),) |
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USE_LINK_GC = yes |
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endif |
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# Linker extra options here. |
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ifeq ($(USE_LDOPT),) |
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USE_LDOPT = |
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endif |
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# Enable this if you want link time optimizations (LTO) |
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ifeq ($(USE_LTO),) |
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USE_LTO = yes |
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endif |
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# If enabled, this option allows to compile the application in THUMB mode. |
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ifeq ($(USE_THUMB),) |
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USE_THUMB = yes |
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endif |
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# Enable this if you want to see the full log while compiling. |
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ifeq ($(USE_VERBOSE_COMPILE),) |
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USE_VERBOSE_COMPILE = no |
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endif |
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# If enabled, this option makes the build process faster by not compiling |
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# modules not used in the current configuration. |
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ifeq ($(USE_SMART_BUILD),) |
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USE_SMART_BUILD = no |
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endif |
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# # |
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# Build global options # |
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################################################################################ |
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################################################################################ |
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# Architecture or project specific options # |
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# # |
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# Stack size to be allocated to the Cortex-M process stack. This stack is |
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# the stack used by the main() thread. |
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ifeq ($(USE_PROCESS_STACKSIZE),) |
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USE_PROCESS_STACKSIZE = 0x400 |
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endif |
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# Stack size to the allocated to the Cortex-M main/exceptions stack. This |
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# stack is used for processing interrupts and exceptions. |
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ifeq ($(USE_EXCEPTIONS_STACKSIZE),) |
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USE_EXCEPTIONS_STACKSIZE = 0x400 |
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endif |
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# Enables the use of FPU on Cortex-M4. |
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# Possible selections are: |
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# no - no FPU is used (probably equals 'soft') |
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# soft - does not use the FPU, thus all floating point operations are emulated |
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# softfp - uses the FPU, but uses the integer registers only |
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# hard - uses the FPU and passes data via the FPU registers |
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ifeq ($(USE_FPU),) |
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USE_FPU = softfp |
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endif |
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# # |
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# Architecture or project specific options # |
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################################################################################ |
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################################################################################ |
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# Project, sources and paths # |
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# # |
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# Define project name here |
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PROJECT := $(patsubst $(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST))))..)/%,%,$(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST)))))) |
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# Imported source files and paths |
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include ../../kernel/kernel.mk |
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CHIBIOS := $(AMIROOS_KERNEL) |
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AMIROOS = ../.. |
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# Licensing files |
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include $(CHIBIOS)/os/license/license.mk |
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# Startup files |
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk |
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# HAL-OSAL files |
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include $(CHIBIOS)/os/hal/hal.mk |
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include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk |
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk |
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# RTOS files |
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include $(CHIBIOS)/os/rt/rt.mk |
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk |
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# Other files (optional). |
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include $(CHIBIOS)/test/lib/test.mk |
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include $(CHIBIOS)/test/rt/rt_test.mk |
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include $(CHIBIOS)/test/oslib/oslib_test.mk |
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# AMiRo-BLT files |
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include ../../bootloader/bootloader.mk |
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# AMiRo-LLD files |
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include ../../periphery-lld/periphery-lld.mk |
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# AMiRo-OS files |
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include ../modules.mk |
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include $(AMIROOS)/core/core.mk |
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include $(AMIROOS)/unittests/unittests.mk |
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# Define linker script file here |
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LDSCRIPT= STM32L476xG.ld |
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# C sources that can be compiled in ARM or THUMB mode depending on the global |
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# setting. |
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CSRC = $(LICSRC) \ |
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$(STARTUPSRC) \ |
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$(KERNSRC) \ |
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$(PORTSRC) \ |
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$(OSALSRC) \ |
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$(HALSRC) \ |
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$(PLATFORMSRC) \ |
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$(MODULESCSRC) \ |
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$(TESTSRC) \ |
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$(PERIPHERYLLDCSRC) \ |
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$(AMIROOSCORECSRC) \ |
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$(UNITTESTSCSRC) \ |
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$(CHIBIOS)/os/various/evtimer.c \ |
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$(CHIBIOS)/os/various/syscalls.c \ |
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$(CHIBIOS)/os/hal/lib/streams/chprintf.c \ |
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board.c \ |
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module.c \ |
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$(APPSCSRC) |
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global |
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# setting. |
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CPPSRC = $(AMIROOSCORECPPSRC) \ |
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$(CHIBIOS)/os/various/cpp_wrappers/syscalls_cpp.cpp \ |
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$(APPSCPPSRC) |
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# C sources to be compiled in ARM mode regardless of the global setting. |
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler |
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# option that results in lower performance and larger code size. |
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ACSRC = $(APPSACSRC) |
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# C++ sources to be compiled in ARM mode regardless of the global setting. |
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler |
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# option that results in lower performance and larger code size. |
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ACPPSRC = $(APPSACPPSRC) |
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# C sources to be compiled in THUMB mode regardless of the global setting. |
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler |
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# option that results in lower performance and larger code size. |
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TCSRC = $(APPSTCSRC) |
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# C sources to be compiled in THUMB mode regardless of the global setting. |
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler |
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# option that results in lower performance and larger code size. |
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TCPPSRC = $(APPSTCPPSRC) |
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# List ASM source files here |
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ASMSRC = $(APPSASMSRC) |
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ASMXSRC = $(STARTUPASM) \ |
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$(PORTASM) \ |
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$(OSALASM) \ |
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$(APPSASMXSRC) |
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INCDIR = $(LICINC) \ |
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$(STARTUPINC) \ |
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$(KERNINC) \ |
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$(PORTINC) \ |
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$(OSALINC) \ |
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$(HALINC) \ |
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$(PLATFORMINC) \ |
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$(MODULESINC) \ |
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$(TESTINC) \ |
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$(BOOTLOADERINC) \ |
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$(CHIBIOS)/os/hal/lib/streams \ |
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$(PERIPHERYLLDINC) \ |
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$(AMIROOS) \ |
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$(AMIROOSCOREINC) \ |
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$(UNITTESTSINC) \ |
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$(APPSINC) |
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# # |
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# Project, sources and paths # |
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################################################################################ |
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################################################################################ |
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# Compiler settings # |
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# NOTE: Some can be overridden externally. # |
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# # |
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MCU = cortex-m4 |
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#TRGT = arm-elf- |
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TRGT = arm-none-eabi- |
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CC = $(TRGT)gcc |
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CPPC = $(TRGT)g++ |
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# Enable loading with g++ only if you need C++ runtime support. |
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# NOTE: You can use C++ even without C++ support if you are careful. C++ |
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# runtime support makes code size explode. |
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LD = $(TRGT)gcc |
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#LD = $(TRGT)g++ |
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CP = $(TRGT)objcopy |
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AS = $(TRGT)gcc -x assembler-with-cpp |
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AR = $(TRGT)ar |
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OD = $(TRGT)objdump |
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SZ = $(TRGT)size |
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HEX = $(CP) -O ihex |
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BIN = $(CP) -O binary |
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SREC = $(CP) -O srec --srec-len=248 |
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# ARM-specific options here |
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ifeq ($(AOPT),) |
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AOPT = |
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endif |
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# THUMB-specific options here |
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ifeq ($(TOPT),) |
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TOPT = -mthumb -DTHUMB |
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endif |
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# Define C warning options here |
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ifeq ($(CWARN),) |
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CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes |
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endif |
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# Define C++ warning options here |
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ifeq ($(CPPWARN),) |
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CPPWARN = -Wall -Wextra -Wundef |
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endif |
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# # |
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# Compiler settings # |
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################################################################################ |
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################################################################################ |
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# Start of user section # |
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# # |
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# List all user C define here, like -D_DEBUG=1 |
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UDEFS += |
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# Define ASM defines here |
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UADEFS += |
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# List all user directories here |
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UINCDIR += |
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# List the user directory to look for the libraries here |
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ULIBDIR += |
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# List all user libraries here |
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ULIBS += |
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# # |
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# End of user defines # |
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################################################################################ |
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################################################################################ |
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# Start of targets section # |
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# # |
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# all and its dependencies |
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ifeq ($(BUILDDIR),) |
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BUILDDIR = ./build |
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endif |
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RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC |
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include $(RULESPATH)/rules.mk |
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# flash |
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include $(AMIROOS)/bootloader/bootloader.mk |
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flash: $(BUILDDIR)/$(PROJECT).elf |
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openocd -f interface/stlink-v2-1.cfg -c "set WORKAREASIZE 0x2000" -f target/stm32l4x.cfg -c "program build/$(PROJECT).elf verify reset exit" |
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# # |
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# End of targets section # |
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################################################################################ |
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| modules/NUCLEO-L476RG/STM32L476xG.ld | ||
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/* |
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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/* |
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* STM32L476xG memory setup. |
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*/ |
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MEMORY |
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{
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flash0 : org = 0x08000000, len = 1M |
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flash1 : org = 0x00000000, len = 0 |
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flash2 : org = 0x00000000, len = 0 |
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flash3 : org = 0x00000000, len = 0 |
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flash4 : org = 0x00000000, len = 0 |
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flash5 : org = 0x00000000, len = 0 |
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flash6 : org = 0x00000000, len = 0 |
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flash7 : org = 0x00000000, len = 0 |
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ram0 : org = 0x20000000, len = 96k |
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ram1 : org = 0x00000000, len = 0 |
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ram2 : org = 0x00000000, len = 0 |
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ram3 : org = 0x00000000, len = 0 |
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ram4 : org = 0x10000000, len = 32k |
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ram5 : org = 0x00000000, len = 0 |
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ram6 : org = 0x00000000, len = 0 |
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ram7 : org = 0x00000000, len = 0 |
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} |
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/* For each data/text section two region are defined, a virtual region |
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and a load region (_LMA suffix).*/ |
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/* Flash region to be used for exception vectors.*/ |
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/ |
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/ |
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/ |
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/ |
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/ |
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing |
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of all exceptions and interrupts.*/ |
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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/* RAM region to be used for the process stack. This is the stack used by |
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the main() function.*/ |
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
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/* RAM region to be used for data segment.*/ |
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/ |
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/ |
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Generic rules inclusion.*/ |
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INCLUDE rules.ld |
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| modules/NUCLEO-L476RG/alldconf.h | ||
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/* |
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
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Copyright (C) 2016..2019 Thomas Schöpping et al. |
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|
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This program is free software: you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation, either version 3 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief AMiRo-LLD configuration file for the STM32L476RG-NUCLEO64 module. |
|
| 22 |
* @details Contains the application specific AMiRo-LLD settings. |
|
| 23 |
* |
|
| 24 |
* @addtogroup STM32L476RG-NUCLEO64_config |
|
| 25 |
* @{
|
|
| 26 |
*/ |
|
| 27 |
|
|
| 28 |
#ifndef ALLDCONF_H |
|
| 29 |
#define ALLDCONF_H |
|
| 30 |
|
|
| 31 |
/* |
|
| 32 |
* compatibility guards |
|
| 33 |
*/ |
|
| 34 |
#define _AMIRO_LLD_CFG_ |
|
| 35 |
#define AMIRO_LLD_CFG_VERSION_MAJOR 1 |
|
| 36 |
#define AMIRO_LLD_CFG_VERSION_MINOR 0 |
|
| 37 |
|
|
| 38 |
/** |
|
| 39 |
* @brief Width of the apalTime_t data type. |
|
| 40 |
* |
|
| 41 |
* @details Possible values are 8, 16, 32, and 64 bits. |
|
| 42 |
* By definition time is represented at microsecond precision. |
|
| 43 |
*/ |
|
| 44 |
#define AMIROLLD_CFG_TIME_SIZE 32 |
|
| 45 |
|
|
| 46 |
#endif /* ALLDCONF_H */ |
|
| 47 |
|
|
| 48 |
/** @} */ |
|
| modules/NUCLEO-L476RG/aosconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief AMiRo-OS Configuration file for the STM32L476RG-NUCLEO64 module. |
|
| 22 |
* @details Contains the application specific AMiRo-OS settings. |
|
| 23 |
* |
|
| 24 |
* @addtogroup STM32L476RG-NUCLEO64_aos_config |
|
| 25 |
* @{
|
|
| 26 |
*/ |
|
| 27 |
|
|
| 28 |
#ifndef AOSCONF_H |
|
| 29 |
#define AOSCONF_H |
|
| 30 |
|
|
| 31 |
/* |
|
| 32 |
* compatibility guards |
|
| 33 |
*/ |
|
| 34 |
#define _AMIRO_OS_CFG_ |
|
| 35 |
#define AMIRO_OS_CFG_VERSION_MAJOR 2 |
|
| 36 |
#define AMIRO_OS_CFG_VERSION_MINOR 0 |
|
| 37 |
|
|
| 38 |
#include <stdbool.h> |
|
| 39 |
|
|
| 40 |
/* |
|
| 41 |
* Include an external configuration file to override the following default settings only if required. |
|
| 42 |
*/ |
|
| 43 |
#if defined(AMIRO_APPS) && (AMIRO_APPS == true) |
|
| 44 |
#include <osconf.h> |
|
| 45 |
#endif |
|
| 46 |
|
|
| 47 |
/*===========================================================================*/ |
|
| 48 |
/** |
|
| 49 |
* @name Kernel parameters and options |
|
| 50 |
* @{
|
|
| 51 |
*/ |
|
| 52 |
/*===========================================================================*/ |
|
| 53 |
|
|
| 54 |
/** |
|
| 55 |
* @brief Flag to enable/disable debug API and logic. |
|
| 56 |
*/ |
|
| 57 |
#if !defined(OS_CFG_DBG) |
|
| 58 |
#define AMIROOS_CFG_DBG true |
|
| 59 |
#else |
|
| 60 |
#define AMIROOS_CFG_DBG OS_CFG_DBG |
|
| 61 |
#endif |
|
| 62 |
|
|
| 63 |
/** |
|
| 64 |
* @brief Flag to enable/disable unit tests. |
|
| 65 |
* @note Setting this flag will implicitely enable the shell. |
|
| 66 |
*/ |
|
| 67 |
#if !defined(OS_CFG_TESTS_ENABLE) |
|
| 68 |
#define AMIROOS_CFG_TESTS_ENABLE true |
|
| 69 |
#else |
|
| 70 |
#define AMIROOS_CFG_TESTS_ENABLE OS_CFG_TESTS_ENABLE |
|
| 71 |
#endif |
|
| 72 |
|
|
| 73 |
/** |
|
| 74 |
* @brief Flag to enable/disable profiling API and logic. |
|
| 75 |
*/ |
|
| 76 |
#if !defined(OS_CFG_PROFILE) |
|
| 77 |
#define AMIROOS_CFG_PROFILE true |
|
| 78 |
#else |
|
| 79 |
#define AMIROOS_CFG_PROFILE OS_CFG_PROFILE |
|
| 80 |
#endif |
|
| 81 |
|
|
| 82 |
/** |
|
| 83 |
* @brief Mask for the control thread to listen to certain IO events. |
|
| 84 |
* @note Any mandatory events (e.g. for SSSP) are enabled implicitely despite this configuration. |
|
| 85 |
*/ |
|
| 86 |
#if !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) |
|
| 87 |
#define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK MODULE_OS_IOEVENTFLAGS_USERBUTTON |
|
| 88 |
#else |
|
| 89 |
#define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK OS_CFG_MAIN_LOOP_IOEVENT_MASK |
|
| 90 |
#endif |
|
| 91 |
|
|
| 92 |
/** |
|
| 93 |
* @brief Timeout value when waiting for events in the main loop in microseconds. |
|
| 94 |
* @details A value of 0 deactivates the timeout. |
|
| 95 |
*/ |
|
| 96 |
#if !defined(OS_CFG_MAIN_LOOP_TIMEOUT) |
|
| 97 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT 0 |
|
| 98 |
#else |
|
| 99 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT OS_CFG_MAIN_LOOP_TIMEOUT |
|
| 100 |
#endif |
|
| 101 |
|
|
| 102 |
/** @} */ |
|
| 103 |
|
|
| 104 |
/*===========================================================================*/ |
|
| 105 |
/** |
|
| 106 |
* @name SSSP (Startup Shutdown Synchronization Protocol) configuration. |
|
| 107 |
* @{
|
|
| 108 |
*/ |
|
| 109 |
/*===========================================================================*/ |
|
| 110 |
|
|
| 111 |
/** |
|
| 112 |
* @brief Flag to enable SSSP. |
|
| 113 |
*/ |
|
| 114 |
#if !defined(OS_CFG_SSSP_ENABLE) |
|
| 115 |
#define AMIROOS_CFG_SSSP_ENABLE false |
|
| 116 |
#else |
|
| 117 |
#define AMIROOS_CFG_SSSP_ENABLE OS_CFG_SSSP_ENABLE |
|
| 118 |
#endif |
|
| 119 |
|
|
| 120 |
/** |
|
| 121 |
* @brief Flag to set the module as SSSP master. |
|
| 122 |
* @details There must be only one module with this flag set to true in a system. |
|
| 123 |
*/ |
|
| 124 |
#if !defined(OS_CFG_SSSP_MASTER) |
|
| 125 |
#define AMIROOS_CFG_SSSP_MASTER false |
|
| 126 |
#else |
|
| 127 |
#define AMIROOS_CFG_SSSP_MASTER OS_CFG_SSSP_MASTER |
|
| 128 |
#endif |
|
| 129 |
|
|
| 130 |
/** |
|
| 131 |
* @brief Flag to set the module to be the first in the stack. |
|
| 132 |
* @details There must be only one module with this flag set to true in a system. |
|
| 133 |
*/ |
|
| 134 |
#if !defined(OS_CFG_SSSP_STACK_START) |
|
| 135 |
#define AMIROOS_CFG_SSSP_STACK_START false |
|
| 136 |
#else |
|
| 137 |
#define AMIROOS_CFG_SSSP_STACK_START OS_CFG_SSSP_STACK_START |
|
| 138 |
#endif |
|
| 139 |
|
|
| 140 |
/** |
|
| 141 |
* @brief Flag to set the module to be the last in the stack. |
|
| 142 |
* @details There must be only one module with this flag set to true in a system. |
|
| 143 |
*/ |
|
| 144 |
#if !defined(OS_CFG_SSSP_STACK_END) |
|
| 145 |
#define AMIROOS_CFG_SSSP_STACK_END false |
|
| 146 |
#else |
|
| 147 |
#define AMIROOS_CFG_SSSP_STACK_END OS_CFG_SSSP_STACK_END |
|
| 148 |
#endif |
|
| 149 |
|
|
| 150 |
/** |
|
| 151 |
* @brief Delay time (in microseconds) how long a SSSP signal must be active. |
|
| 152 |
*/ |
|
| 153 |
#if !defined(OS_CFG_SSSP_SIGNALDELAY) |
|
| 154 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY 1000 |
|
| 155 |
#else |
|
| 156 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY OS_CFG_SSSP_SIGNALDELAY |
|
| 157 |
#endif |
|
| 158 |
|
|
| 159 |
/** |
|
| 160 |
* @brief Time boundary for robot wide clock synchronization in microseconds. |
|
| 161 |
* @details Whenever the SSSP S (snychronization) signal gets logically deactivated, |
|
| 162 |
* All modules need to align their local uptime to the nearest multiple of this value. |
|
| 163 |
*/ |
|
| 164 |
#if !defined(OS_CFG_SSSP_SYSSYNCPERIOD) |
|
| 165 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD 1000000 |
|
| 166 |
#else |
|
| 167 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD OS_CFG_SSSP_SYSSYNCPERIOD |
|
| 168 |
#endif |
|
| 169 |
|
|
| 170 |
/** @} */ |
|
| 171 |
|
|
| 172 |
/*===========================================================================*/ |
|
| 173 |
/** |
|
| 174 |
* @name System shell options |
|
| 175 |
* @{
|
|
| 176 |
*/ |
|
| 177 |
/*===========================================================================*/ |
|
| 178 |
|
|
| 179 |
/** |
|
| 180 |
* @brief Shell enable flag. |
|
| 181 |
*/ |
|
| 182 |
#if !defined(OS_CFG_SHELL_ENABLE) |
|
| 183 |
#define AMIROOS_CFG_SHELL_ENABLE true |
|
| 184 |
#else |
|
| 185 |
#define AMIROOS_CFG_SHELL_ENABLE OS_CFG_SHELL_ENABLE |
|
| 186 |
#endif |
|
| 187 |
|
|
| 188 |
/** |
|
| 189 |
* @brief Shell thread stack size. |
|
| 190 |
*/ |
|
| 191 |
#if !defined(OS_CFG_SHELL_STACKSIZE) |
|
| 192 |
#define AMIROOS_CFG_SHELL_STACKSIZE 1024 |
|
| 193 |
#else |
|
| 194 |
#define AMIROOS_CFG_SHELL_STACKSIZE OS_CFG_SHELL_STACKSIZE |
|
| 195 |
#endif |
|
| 196 |
|
|
| 197 |
/** |
|
| 198 |
* @brief Shell thread priority. |
|
| 199 |
* @details Thread priorities are specified as an integer value. |
|
| 200 |
* Predefined ranges are: |
|
| 201 |
* lowest ┌ THD_LOWPRIO_MIN |
|
| 202 |
* │ ... |
|
| 203 |
* â”” THD_LOWPRIO_MAX |
|
| 204 |
* ┌ THD_NORMALPRIO_MIN |
|
| 205 |
* │ ... |
|
| 206 |
* â”” THD_NORMALPRIO_MAX |
|
| 207 |
* ┌ THD_HIGHPRIO_MIN |
|
| 208 |
* │ ... |
|
| 209 |
* â”” THD_HIGHPRIO_MAX |
|
| 210 |
* ┌ THD_RTPRIO_MIN |
|
| 211 |
* │ ... |
|
| 212 |
* highest â”” THD_RTPRIO_MAX |
|
| 213 |
*/ |
|
| 214 |
#if !defined(OS_CFG_SHELL_THREADPRIO) |
|
| 215 |
#define AMIROOS_CFG_SHELL_THREADPRIO AOS_THD_NORMALPRIO_MIN |
|
| 216 |
#else |
|
| 217 |
#define AMIROOS_CFG_SHELL_THREADPRIO OS_CFG_SHELL_THREADPRIO |
|
| 218 |
#endif |
|
| 219 |
|
|
| 220 |
/** |
|
| 221 |
* @brief Shell maximum input line length. |
|
| 222 |
*/ |
|
| 223 |
#if !defined(OS_CFG_SHELL_LINEWIDTH) |
|
| 224 |
#define AMIROOS_CFG_SHELL_LINEWIDTH 64 |
|
| 225 |
#else |
|
| 226 |
#define AMIROOS_CFG_SHELL_LINEWIDTH OS_CFG_SHELL_LINEWIDTH |
|
| 227 |
#endif |
|
| 228 |
|
|
| 229 |
/** |
|
| 230 |
* @brief Shell maximum number of arguments. |
|
| 231 |
*/ |
|
| 232 |
#if !defined(OS_CFG_SHELL_MAXARGS) |
|
| 233 |
#define AMIROOS_CFG_SHELL_MAXARGS 4 |
|
| 234 |
#else |
|
| 235 |
#define AMIROOS_CFG_SHELL_MAXARGS OS_CFG_SHELL_MAXARGS |
|
| 236 |
#endif |
|
| 237 |
|
|
| 238 |
/** @} */ |
|
| 239 |
|
|
| 240 |
#endif /* AOSCONF_H */ |
|
| 241 |
|
|
| 242 |
/** @} */ |
|
| modules/NUCLEO-L476RG/board.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
|
| 3 |
|
|
| 4 |
Licensed under the Apache License, Version 2.0 (the "License"); |
|
| 5 |
you may not use this file except in compliance with the License. |
|
| 6 |
You may obtain a copy of the License at |
|
| 7 |
|
|
| 8 |
http://www.apache.org/licenses/LICENSE-2.0 |
|
| 9 |
|
|
| 10 |
Unless required by applicable law or agreed to in writing, software |
|
| 11 |
distributed under the License is distributed on an "AS IS" BASIS, |
|
| 12 |
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|
| 13 |
See the License for the specific language governing permissions and |
|
| 14 |
limitations under the License. |
|
| 15 |
*/ |
|
| 16 |
|
|
| 17 |
/* |
|
| 18 |
* This file has been automatically generated using ChibiStudio board |
|
| 19 |
* generator plugin. Do not edit manually. |
|
| 20 |
*/ |
|
| 21 |
|
|
| 22 |
#include "hal.h" |
|
| 23 |
#include "stm32_gpio.h" |
|
| 24 |
|
|
| 25 |
/*===========================================================================*/ |
|
| 26 |
/* Driver local definitions. */ |
|
| 27 |
/*===========================================================================*/ |
|
| 28 |
|
|
| 29 |
/*===========================================================================*/ |
|
| 30 |
/* Driver exported variables. */ |
|
| 31 |
/*===========================================================================*/ |
|
| 32 |
|
|
| 33 |
/*===========================================================================*/ |
|
| 34 |
/* Driver local variables and types. */ |
|
| 35 |
/*===========================================================================*/ |
|
| 36 |
|
|
| 37 |
/** |
|
| 38 |
* @brief Type of STM32 GPIO port setup. |
|
| 39 |
*/ |
|
| 40 |
typedef struct {
|
|
| 41 |
uint32_t moder; |
|
| 42 |
uint32_t otyper; |
|
| 43 |
uint32_t ospeedr; |
|
| 44 |
uint32_t pupdr; |
|
| 45 |
uint32_t odr; |
|
| 46 |
uint32_t afrl; |
|
| 47 |
uint32_t afrh; |
|
| 48 |
uint32_t ascr; |
|
| 49 |
uint32_t lockr; |
|
| 50 |
} gpio_setup_t; |
|
| 51 |
|
|
| 52 |
/** |
|
| 53 |
* @brief Type of STM32 GPIO initialization data. |
|
| 54 |
*/ |
|
| 55 |
typedef struct {
|
|
| 56 |
#if STM32_HAS_GPIOA || defined(__DOXYGEN__) |
|
| 57 |
gpio_setup_t PAData; |
|
| 58 |
#endif |
|
| 59 |
#if STM32_HAS_GPIOB || defined(__DOXYGEN__) |
|
| 60 |
gpio_setup_t PBData; |
|
| 61 |
#endif |
|
| 62 |
#if STM32_HAS_GPIOC || defined(__DOXYGEN__) |
|
| 63 |
gpio_setup_t PCData; |
|
| 64 |
#endif |
|
| 65 |
#if STM32_HAS_GPIOD || defined(__DOXYGEN__) |
|
| 66 |
gpio_setup_t PDData; |
|
| 67 |
#endif |
|
| 68 |
#if STM32_HAS_GPIOE || defined(__DOXYGEN__) |
|
| 69 |
gpio_setup_t PEData; |
|
| 70 |
#endif |
|
| 71 |
#if STM32_HAS_GPIOF || defined(__DOXYGEN__) |
|
| 72 |
gpio_setup_t PFData; |
|
| 73 |
#endif |
|
| 74 |
#if STM32_HAS_GPIOG || defined(__DOXYGEN__) |
|
| 75 |
gpio_setup_t PGData; |
|
| 76 |
#endif |
|
| 77 |
#if STM32_HAS_GPIOH || defined(__DOXYGEN__) |
|
| 78 |
gpio_setup_t PHData; |
|
| 79 |
#endif |
|
| 80 |
#if STM32_HAS_GPIOI || defined(__DOXYGEN__) |
|
| 81 |
gpio_setup_t PIData; |
|
| 82 |
#endif |
|
| 83 |
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) |
|
| 84 |
gpio_setup_t PJData; |
|
| 85 |
#endif |
|
| 86 |
#if STM32_HAS_GPIOK || defined(__DOXYGEN__) |
|
| 87 |
gpio_setup_t PKData; |
|
| 88 |
#endif |
|
| 89 |
} gpio_config_t; |
|
| 90 |
|
|
| 91 |
/** |
|
| 92 |
* @brief STM32 GPIO static initialization data. |
|
| 93 |
*/ |
|
| 94 |
static const gpio_config_t gpio_default_config = {
|
|
| 95 |
#if STM32_HAS_GPIOA |
|
| 96 |
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
|
| 97 |
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, |
|
| 98 |
VAL_GPIOA_LOCKR}, |
|
| 99 |
#endif |
|
| 100 |
#if STM32_HAS_GPIOB |
|
| 101 |
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
|
| 102 |
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, |
|
| 103 |
VAL_GPIOB_LOCKR}, |
|
| 104 |
#endif |
|
| 105 |
#if STM32_HAS_GPIOC |
|
| 106 |
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
|
| 107 |
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, |
|
| 108 |
VAL_GPIOC_LOCKR}, |
|
| 109 |
#endif |
|
| 110 |
#if STM32_HAS_GPIOD |
|
| 111 |
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
|
| 112 |
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, |
|
| 113 |
VAL_GPIOD_LOCKR}, |
|
| 114 |
#endif |
|
| 115 |
#if STM32_HAS_GPIOE |
|
| 116 |
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
|
| 117 |
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, |
|
| 118 |
VAL_GPIOE_LOCKR}, |
|
| 119 |
#endif |
|
| 120 |
#if STM32_HAS_GPIOF |
|
| 121 |
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
|
| 122 |
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, |
|
| 123 |
VAL_GPIOF_LOCKR}, |
|
| 124 |
#endif |
|
| 125 |
#if STM32_HAS_GPIOG |
|
| 126 |
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
|
| 127 |
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, |
|
| 128 |
VAL_GPIOG_LOCKR}, |
|
| 129 |
#endif |
|
| 130 |
#if STM32_HAS_GPIOH |
|
| 131 |
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
|
| 132 |
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, |
|
| 133 |
VAL_GPIOH_LOCKR}, |
|
| 134 |
#endif |
|
| 135 |
#if STM32_HAS_GPIOI |
|
| 136 |
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
|
| 137 |
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, |
|
| 138 |
VAL_GPIOI_LOCKR}, |
|
| 139 |
#endif |
|
| 140 |
#if STM32_HAS_GPIOJ |
|
| 141 |
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
|
| 142 |
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, |
|
| 143 |
VAL_GPIOJ_LOCKR}, |
|
| 144 |
#endif |
|
| 145 |
#if STM32_HAS_GPIOK |
|
| 146 |
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
|
| 147 |
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, |
|
| 148 |
VAL_GPIOK_LOCKR} |
|
| 149 |
#endif |
|
| 150 |
}; |
|
| 151 |
|
|
| 152 |
/*===========================================================================*/ |
|
| 153 |
/* Driver local functions. */ |
|
| 154 |
/*===========================================================================*/ |
|
| 155 |
|
|
| 156 |
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
|
| 157 |
|
|
| 158 |
gpiop->OTYPER = config->otyper; |
|
| 159 |
gpiop->ASCR = config->ascr; |
|
| 160 |
gpiop->OSPEEDR = config->ospeedr; |
|
| 161 |
gpiop->PUPDR = config->pupdr; |
|
| 162 |
gpiop->ODR = config->odr; |
|
| 163 |
gpiop->AFRL = config->afrl; |
|
| 164 |
gpiop->AFRH = config->afrh; |
|
| 165 |
gpiop->MODER = config->moder; |
|
| 166 |
gpiop->LOCKR = config->lockr; |
|
| 167 |
} |
|
| 168 |
|
|
| 169 |
static void stm32_gpio_init(void) {
|
|
| 170 |
|
|
| 171 |
/* Enabling GPIO-related clocks, the mask comes from the |
|
| 172 |
registry header file.*/ |
|
| 173 |
rccResetAHB2(STM32_GPIO_EN_MASK); |
|
| 174 |
rccEnableAHB2(STM32_GPIO_EN_MASK, true); |
|
| 175 |
|
|
| 176 |
/* Initializing all the defined GPIO ports.*/ |
|
| 177 |
#if STM32_HAS_GPIOA |
|
| 178 |
gpio_init(GPIOA, &gpio_default_config.PAData); |
|
| 179 |
#endif |
|
| 180 |
#if STM32_HAS_GPIOB |
|
| 181 |
gpio_init(GPIOB, &gpio_default_config.PBData); |
|
| 182 |
#endif |
|
| 183 |
#if STM32_HAS_GPIOC |
|
| 184 |
gpio_init(GPIOC, &gpio_default_config.PCData); |
|
| 185 |
#endif |
|
| 186 |
#if STM32_HAS_GPIOD |
|
| 187 |
gpio_init(GPIOD, &gpio_default_config.PDData); |
|
| 188 |
#endif |
|
| 189 |
#if STM32_HAS_GPIOE |
|
| 190 |
gpio_init(GPIOE, &gpio_default_config.PEData); |
|
| 191 |
#endif |
|
| 192 |
#if STM32_HAS_GPIOF |
|
| 193 |
gpio_init(GPIOF, &gpio_default_config.PFData); |
|
| 194 |
#endif |
|
| 195 |
#if STM32_HAS_GPIOG |
|
| 196 |
gpio_init(GPIOG, &gpio_default_config.PGData); |
|
| 197 |
#endif |
|
| 198 |
#if STM32_HAS_GPIOH |
|
| 199 |
gpio_init(GPIOH, &gpio_default_config.PHData); |
|
| 200 |
#endif |
|
| 201 |
#if STM32_HAS_GPIOI |
|
| 202 |
gpio_init(GPIOI, &gpio_default_config.PIData); |
|
| 203 |
#endif |
|
| 204 |
#if STM32_HAS_GPIOJ |
|
| 205 |
gpio_init(GPIOJ, &gpio_default_config.PJData); |
|
| 206 |
#endif |
|
| 207 |
#if STM32_HAS_GPIOK |
|
| 208 |
gpio_init(GPIOK, &gpio_default_config.PKData); |
|
| 209 |
#endif |
|
| 210 |
} |
|
| 211 |
|
|
| 212 |
/*===========================================================================*/ |
|
| 213 |
/* Driver interrupt handlers. */ |
|
| 214 |
/*===========================================================================*/ |
|
| 215 |
|
|
| 216 |
/*===========================================================================*/ |
|
| 217 |
/* Driver exported functions. */ |
|
| 218 |
/*===========================================================================*/ |
|
| 219 |
|
|
| 220 |
/** |
|
| 221 |
* @brief Early initialization code. |
|
| 222 |
* @details GPIO ports and system clocks are initialized before everything |
|
| 223 |
* else. |
|
| 224 |
*/ |
|
| 225 |
void __early_init(void) {
|
|
| 226 |
|
|
| 227 |
stm32_gpio_init(); |
|
| 228 |
stm32_clock_init(); |
|
| 229 |
} |
|
| 230 |
|
|
| 231 |
#if HAL_USE_SDC || defined(__DOXYGEN__) |
|
| 232 |
/** |
|
| 233 |
* @brief SDC card detection. |
|
| 234 |
*/ |
|
| 235 |
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
|
| 236 |
|
|
| 237 |
(void)sdcp; |
|
| 238 |
/* TODO: Fill the implementation.*/ |
|
| 239 |
return true; |
|
| 240 |
} |
|
| 241 |
|
|
| 242 |
/** |
|
| 243 |
* @brief SDC card write protection detection. |
|
| 244 |
*/ |
|
| 245 |
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
|
| 246 |
|
|
| 247 |
(void)sdcp; |
|
| 248 |
/* TODO: Fill the implementation.*/ |
|
| 249 |
return false; |
|
| 250 |
} |
|
| 251 |
#endif /* HAL_USE_SDC */ |
|
| 252 |
|
|
| 253 |
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) |
|
| 254 |
/** |
|
| 255 |
* @brief MMC_SPI card detection. |
|
| 256 |
*/ |
|
| 257 |
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
|
| 258 |
|
|
| 259 |
(void)mmcp; |
|
| 260 |
/* TODO: Fill the implementation.*/ |
|
| 261 |
return true; |
|
| 262 |
} |
|
| 263 |
|
|
| 264 |
/** |
|
| 265 |
* @brief MMC_SPI card write protection detection. |
|
| 266 |
*/ |
|
| 267 |
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
|
| 268 |
|
|
| 269 |
(void)mmcp; |
|
| 270 |
/* TODO: Fill the implementation.*/ |
|
| 271 |
return false; |
|
| 272 |
} |
|
| 273 |
#endif |
|
| 274 |
|
|
| 275 |
/** |
|
| 276 |
* @brief Board-specific initialization code. |
|
| 277 |
* @todo Add your board-specific code, if any. |
|
| 278 |
*/ |
|
| 279 |
void boardInit(void) {
|
|
| 280 |
|
|
| 281 |
} |
|
| modules/NUCLEO-L476RG/board.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
|
| 3 |
|
|
| 4 |
Licensed under the Apache License, Version 2.0 (the "License"); |
|
| 5 |
you may not use this file except in compliance with the License. |
|
| 6 |
You may obtain a copy of the License at |
|
| 7 |
|
|
| 8 |
http://www.apache.org/licenses/LICENSE-2.0 |
|
| 9 |
|
|
| 10 |
Unless required by applicable law or agreed to in writing, software |
|
| 11 |
distributed under the License is distributed on an "AS IS" BASIS, |
|
| 12 |
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|
| 13 |
See the License for the specific language governing permissions and |
|
| 14 |
limitations under the License. |
|
| 15 |
*/ |
|
| 16 |
|
|
| 17 |
/* |
|
| 18 |
* This file has been automatically generated using ChibiStudio board |
|
| 19 |
* generator plugin. Do not edit manually. |
|
| 20 |
*/ |
|
| 21 |
|
|
| 22 |
#ifndef BOARD_H |
|
| 23 |
#define BOARD_H |
|
| 24 |
|
|
| 25 |
/*===========================================================================*/ |
|
| 26 |
/* Driver constants. */ |
|
| 27 |
/*===========================================================================*/ |
|
| 28 |
|
|
| 29 |
/* |
|
| 30 |
* Setup for STMicroelectronics STM32 Nucleo64-L476RG board. |
|
| 31 |
*/ |
|
| 32 |
|
|
| 33 |
/* |
|
| 34 |
* Board identifier. |
|
| 35 |
*/ |
|
| 36 |
#define BOARD_ST_NUCLEO64_L476RG |
|
| 37 |
#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG" |
|
| 38 |
#define BOARD_VERSION "1.0" |
|
| 39 |
|
|
| 40 |
/* |
|
| 41 |
* Board oscillators-related settings. |
|
| 42 |
*/ |
|
| 43 |
#if !defined(STM32_LSECLK) |
|
| 44 |
#define STM32_LSECLK 32768U |
|
| 45 |
#endif |
|
| 46 |
|
|
| 47 |
#define STM32_LSEDRV (3U << 3U) |
|
| 48 |
|
|
| 49 |
#if !defined(STM32_HSECLK) |
|
| 50 |
#define STM32_HSECLK 8000000U |
|
| 51 |
#endif |
|
| 52 |
|
|
| 53 |
#define STM32_HSE_BYPASS |
|
| 54 |
|
|
| 55 |
/* |
|
| 56 |
* Board voltages. |
|
| 57 |
* Required for performance limits calculation. |
|
| 58 |
*/ |
|
| 59 |
#define STM32_VDD 300U |
|
| 60 |
|
|
| 61 |
/* |
|
| 62 |
* MCU type as defined in the ST header. |
|
| 63 |
*/ |
|
| 64 |
#define STM32L476xx |
|
| 65 |
|
|
| 66 |
/* |
|
| 67 |
* IO pins assignments. |
|
| 68 |
*/ |
|
| 69 |
#define GPIOA_ARD_A0 0U |
|
| 70 |
#define GPIOA_ACD12_IN5 0U |
|
| 71 |
#define GPIOA_ARD_A1 1U |
|
| 72 |
#define GPIOA_ACD12_IN6 1U |
|
| 73 |
#define GPIOA_ARD_D1 2U |
|
| 74 |
#define GPIOA_USART2_TX 2U |
|
| 75 |
#define GPIOA_ARD_D0 3U |
|
| 76 |
#define GPIOA_USART2_RX 3U |
|
| 77 |
#define GPIOA_ARD_A2 4U |
|
| 78 |
#define GPIOA_ACD12_IN9 4U |
|
| 79 |
#define GPIOA_ARD_D13 5U |
|
| 80 |
#define GPIOA_LED_GREEN 5U |
|
| 81 |
#define GPIOA_ARD_D12 6U |
|
| 82 |
#define GPIOA_ARD_D11 7U |
|
| 83 |
#define GPIOA_ARD_D7 8U |
|
| 84 |
#define GPIOA_ARD_D8 9U |
|
| 85 |
#define GPIOA_ARD_D2 10U |
|
| 86 |
#define GPIOA_PIN11 11U |
|
| 87 |
#define GPIOA_PIN12 12U |
|
| 88 |
#define GPIOA_SWDIO 13U |
|
| 89 |
#define GPIOA_SWCLK 14U |
|
| 90 |
#define GPIOA_PIN15 15U |
|
| 91 |
|
|
| 92 |
#define GPIOB_ARD_A3 0U |
|
| 93 |
#define GPIOB_ACD12_IN15 0U |
|
| 94 |
#define GPIOB_PIN1 1U |
|
| 95 |
#define GPIOB_PIN2 2U |
|
| 96 |
#define GPIOB_ARD_D3 3U |
|
| 97 |
#define GPIOB_SWO 3U |
|
| 98 |
#define GPIOB_ARD_D5 4U |
|
| 99 |
#define GPIOB_ARD_D4 5U |
|
| 100 |
#define GPIOB_ARD_D10 6U |
|
| 101 |
#define GPIOB_PIN7 7U |
|
| 102 |
#define GPIOB_ARD_D15 8U |
|
| 103 |
#define GPIOB_ARD_D14 9U |
|
| 104 |
#define GPIOB_ARD_D6 10U |
|
| 105 |
#define GPIOB_PIN11 11U |
|
| 106 |
#define GPIOB_PIN12 12U |
|
| 107 |
#define GPIOB_PIN13 13U |
|
| 108 |
#define GPIOB_PIN14 14U |
|
| 109 |
#define GPIOB_PIN15 15U |
|
| 110 |
|
|
| 111 |
#define GPIOC_ARD_A5 0U |
|
| 112 |
#define GPIOC_ACD123_IN1 0U |
|
| 113 |
#define GPIOC_ARD_A4 1U |
|
| 114 |
#define GPIOC_ACD123_IN2 1U |
|
| 115 |
#define GPIOC_PIN2 2U |
|
| 116 |
#define GPIOC_PIN3 3U |
|
| 117 |
#define GPIOC_PIN4 4U |
|
| 118 |
#define GPIOC_PIN5 5U |
|
| 119 |
#define GPIOC_PIN6 6U |
|
| 120 |
#define GPIOC_ARD_D9 7U |
|
| 121 |
#define GPIOC_PIN8 8U |
|
| 122 |
#define GPIOC_PIN9 9U |
|
| 123 |
#define GPIOC_PIN10 10U |
|
| 124 |
#define GPIOC_PIN11 11U |
|
| 125 |
#define GPIOC_PIN12 12U |
|
| 126 |
#define GPIOC_BUTTON 13U |
|
| 127 |
#define GPIOC_OSC32_IN 14U |
|
| 128 |
#define GPIOC_OSC32_OUT 15U |
|
| 129 |
|
|
| 130 |
#define GPIOD_PIN0 0U |
|
| 131 |
#define GPIOD_PIN1 1U |
|
| 132 |
#define GPIOD_PIN2 2U |
|
| 133 |
#define GPIOD_PIN3 3U |
|
| 134 |
#define GPIOD_PIN4 4U |
|
| 135 |
#define GPIOD_PIN5 5U |
|
| 136 |
#define GPIOD_PIN6 6U |
|
| 137 |
#define GPIOD_PIN7 7U |
|
| 138 |
#define GPIOD_PIN8 8U |
|
| 139 |
#define GPIOD_PIN9 9U |
|
| 140 |
#define GPIOD_PIN10 10U |
|
| 141 |
#define GPIOD_PIN11 11U |
|
| 142 |
#define GPIOD_PIN12 12U |
|
| 143 |
#define GPIOD_PIN13 13U |
|
| 144 |
#define GPIOD_PIN14 14U |
|
| 145 |
#define GPIOD_PIN15 15U |
|
| 146 |
|
|
| 147 |
#define GPIOE_PIN0 0U |
|
| 148 |
#define GPIOE_PIN1 1U |
|
| 149 |
#define GPIOE_PIN2 2U |
|
| 150 |
#define GPIOE_PIN3 3U |
|
| 151 |
#define GPIOE_PIN4 4U |
|
| 152 |
#define GPIOE_PIN5 5U |
|
| 153 |
#define GPIOE_PIN6 6U |
|
| 154 |
#define GPIOE_PIN7 7U |
|
| 155 |
#define GPIOE_PIN8 8U |
|
| 156 |
#define GPIOE_PIN9 9U |
|
| 157 |
#define GPIOE_PIN10 10U |
|
| 158 |
#define GPIOE_PIN11 11U |
|
| 159 |
#define GPIOE_PIN12 12U |
|
| 160 |
#define GPIOE_PIN13 13U |
|
| 161 |
#define GPIOE_PIN14 14U |
|
| 162 |
#define GPIOE_PIN15 15U |
|
| 163 |
|
|
| 164 |
#define GPIOF_PIN0 0U |
|
| 165 |
#define GPIOF_PIN1 1U |
|
| 166 |
#define GPIOF_PIN2 2U |
|
| 167 |
#define GPIOF_PIN3 3U |
|
| 168 |
#define GPIOF_PIN4 4U |
|
| 169 |
#define GPIOF_PIN5 5U |
|
| 170 |
#define GPIOF_PIN6 6U |
|
| 171 |
#define GPIOF_PIN7 7U |
|
| 172 |
#define GPIOF_PIN8 8U |
|
| 173 |
#define GPIOF_PIN9 9U |
|
| 174 |
#define GPIOF_PIN10 10U |
|
| 175 |
#define GPIOF_PIN11 11U |
|
| 176 |
#define GPIOF_PIN12 12U |
|
| 177 |
#define GPIOF_PIN13 13U |
|
| 178 |
#define GPIOF_PIN14 14U |
|
| 179 |
#define GPIOF_PIN15 15U |
|
| 180 |
|
|
| 181 |
#define GPIOG_PIN0 0U |
|
| 182 |
#define GPIOG_PIN1 1U |
|
| 183 |
#define GPIOG_PIN2 2U |
|
| 184 |
#define GPIOG_PIN3 3U |
|
| 185 |
#define GPIOG_PIN4 4U |
|
| 186 |
#define GPIOG_PIN5 5U |
|
| 187 |
#define GPIOG_PIN6 6U |
|
| 188 |
#define GPIOG_PIN7 7U |
|
| 189 |
#define GPIOG_PIN8 8U |
|
| 190 |
#define GPIOG_PIN9 9U |
|
| 191 |
#define GPIOG_PIN10 10U |
|
| 192 |
#define GPIOG_PIN11 11U |
|
| 193 |
#define GPIOG_PIN12 12U |
|
| 194 |
#define GPIOG_PIN13 13U |
|
| 195 |
#define GPIOG_PIN14 14U |
|
| 196 |
#define GPIOG_PIN15 15U |
|
| 197 |
|
|
| 198 |
#define GPIOH_OSC_IN 0U |
|
| 199 |
#define GPIOH_OSC_OUT 1U |
|
| 200 |
#define GPIOH_PIN2 2U |
|
| 201 |
#define GPIOH_PIN3 3U |
|
| 202 |
#define GPIOH_PIN4 4U |
|
| 203 |
#define GPIOH_PIN5 5U |
|
| 204 |
#define GPIOH_PIN6 6U |
|
| 205 |
#define GPIOH_PIN7 7U |
|
| 206 |
#define GPIOH_PIN8 8U |
|
| 207 |
#define GPIOH_PIN9 9U |
|
| 208 |
#define GPIOH_PIN10 10U |
|
| 209 |
#define GPIOH_PIN11 11U |
|
| 210 |
#define GPIOH_PIN12 12U |
|
| 211 |
#define GPIOH_PIN13 13U |
|
| 212 |
#define GPIOH_PIN14 14U |
|
| 213 |
#define GPIOH_PIN15 15U |
|
| 214 |
|
|
| 215 |
/* |
|
| 216 |
* IO lines assignments. |
|
| 217 |
*/ |
|
| 218 |
#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) |
|
| 219 |
#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U) |
|
| 220 |
#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) |
|
| 221 |
#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U) |
|
| 222 |
#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) |
|
| 223 |
#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) |
|
| 224 |
#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) |
|
| 225 |
#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) |
|
| 226 |
#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) |
|
| 227 |
#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U) |
|
| 228 |
#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) |
|
| 229 |
#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) |
|
| 230 |
#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) |
|
| 231 |
#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) |
|
| 232 |
#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) |
|
| 233 |
#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) |
|
| 234 |
#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) |
|
| 235 |
#define LINE_SWDIO PAL_LINE(GPIOA, 13U) |
|
| 236 |
#define LINE_SWCLK PAL_LINE(GPIOA, 14U) |
|
| 237 |
#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) |
|
| 238 |
#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U) |
|
| 239 |
#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) |
|
| 240 |
#define LINE_SWO PAL_LINE(GPIOB, 3U) |
|
| 241 |
#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) |
|
| 242 |
#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) |
|
| 243 |
#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) |
|
| 244 |
#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) |
|
| 245 |
#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) |
|
| 246 |
#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) |
|
| 247 |
#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) |
|
| 248 |
#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U) |
|
| 249 |
#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) |
|
| 250 |
#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U) |
|
| 251 |
#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) |
|
| 252 |
#define LINE_BUTTON PAL_LINE(GPIOC, 13U) |
|
| 253 |
#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) |
|
| 254 |
#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) |
|
| 255 |
#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) |
|
| 256 |
#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) |
|
| 257 |
|
|
| 258 |
/*===========================================================================*/ |
|
| 259 |
/* Driver pre-compile time settings. */ |
|
| 260 |
/*===========================================================================*/ |
|
| 261 |
|
|
| 262 |
/*===========================================================================*/ |
|
| 263 |
/* Derived constants and error checks. */ |
|
| 264 |
/*===========================================================================*/ |
|
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/*===========================================================================*/ |
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/* Driver data structures and types. */ |
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/*===========================================================================*/ |
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/*===========================================================================*/ |
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/* Driver macros. */ |
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/*===========================================================================*/ |
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/* |
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* I/O ports initial setup, this configuration is established soon after reset |
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* in the initialization code. |
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* Please refer to the STM32 Reference Manual for details. |
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*/ |
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
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#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
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#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) |
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#define PIN_ODR_LOW(n) (0U << (n)) |
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#define PIN_ODR_HIGH(n) (1U << (n)) |
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#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
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#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
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#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) |
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#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) |
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#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) |
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#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) |
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#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) |
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#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) |
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#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) |
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#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) |
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#define PIN_ASCR_DISABLED(n) (0U << (n)) |
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#define PIN_ASCR_ENABLED(n) (1U << (n)) |
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#define PIN_LOCKR_DISABLED(n) (0U << (n)) |
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#define PIN_LOCKR_ENABLED(n) (1U << (n)) |
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/* |
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* GPIOA setup: |
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* |
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* PA0 - ARD_A0 ACD12_IN5 (analog). |
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* PA1 - ARD_A1 ACD12_IN6 (analog). |
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* PA2 - ARD_D1 USART2_TX (alternate 7). |
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* PA3 - ARD_D0 USART2_RX (alternate 7). |
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* PA4 - ARD_A2 ACD12_IN9 (analog). |
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* PA5 - ARD_D13 LED_GREEN (output pushpull maximum). |
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* PA6 - ARD_D12 (analog). |
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* PA7 - ARD_D11 (analog). |
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* PA8 - ARD_D7 (analog). |
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* PA9 - ARD_D8 (analog). |
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* PA10 - ARD_D2 (analog). |
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* PA11 - PIN11 (analog). |
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* PA12 - PIN12 (analog). |
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* PA13 - SWDIO (alternate 0). |
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* PA14 - SWCLK (alternate 0). |
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* PA15 - PIN15 (analog). |
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*/ |
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#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_A1) | \ |
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PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ |
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PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_A2) | \ |
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PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D12) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D11) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D7) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D8) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D2) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN11) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN12) | \ |
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PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ |
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PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN15)) |
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#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) |
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#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ |
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ |
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN11) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN12) | \ |
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PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ |
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PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN15)) |
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#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ |
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PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ |
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PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN15)) |
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#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_A1) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D1) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D0) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_A2) | \ |
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PIN_ODR_LOW(GPIOA_ARD_D13) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D12) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D11) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D7) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D8) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D2) | \ |
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PIN_ODR_HIGH(GPIOA_PIN11) | \ |
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PIN_ODR_HIGH(GPIOA_PIN12) | \ |
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PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
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PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
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PIN_ODR_HIGH(GPIOA_PIN15)) |
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#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D11, 0U)) |
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ |
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PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ |
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PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ |
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PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ |
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PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ |
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PIN_AFIO_AF(GPIOA_PIN15, 0U)) |
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#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \ |
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PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ |
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PIN_ASCR_DISABLED(GPIOA_PIN11) | \ |
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PIN_ASCR_DISABLED(GPIOA_PIN12) | \ |
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PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ |
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PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ |
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PIN_ASCR_DISABLED(GPIOA_PIN15)) |
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#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \ |
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PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ |
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PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ |
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PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ |
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PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ |
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PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ |
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PIN_LOCKR_DISABLED(GPIOA_PIN15)) |
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/* |
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* GPIOB setup: |
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* |
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* PB0 - ARD_A3 ACD12_IN15 (analog). |
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* PB1 - PIN1 (analog). |
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* PB2 - PIN2 (analog). |
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* PB3 - ARD_D3 SWO (analog). |
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* PB4 - ARD_D5 (analog). |
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* PB5 - ARD_D4 (analog). |
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* PB6 - ARD_D10 (analog). |
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* PB7 - PIN7 (analog). |
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* PB8 - ARD_D15 (analog). |
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* PB9 - ARD_D14 (analog). |
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* PB10 - ARD_D6 (analog). |
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* PB11 - PIN11 (analog). |
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* PB12 - PIN12 (analog). |
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* PB13 - PIN13 (analog). |
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* PB14 - PIN14 (analog). |
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* PB15 - PIN15 (analog). |
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*/ |
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#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN1) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN2) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D3) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D10) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN7) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D15) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D14) | \ |
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PIN_MODE_ANALOG(GPIOB_ARD_D6) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN11) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN12) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN13) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN14) | \ |
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PIN_MODE_ANALOG(GPIOB_PIN15)) |
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#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ |
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