amiro-os / modules / NUCLEO-L476RG / board.h @ 88f4bcc5
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* This file has been automatically generated using ChibiStudio board
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* generator plugin. Do not edit manually.
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*/
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#ifndef BOARD_H
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#define BOARD_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*
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* Setup for STMicroelectronics STM32 Nucleo64-L476RG board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_ST_NUCLEO64_L476RG
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#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG" |
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#define BOARD_VERSION "1.0" |
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/*
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* Board oscillators-related settings.
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*/
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 32768U |
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#endif
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#define STM32_LSEDRV (3U << 3U) |
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U |
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#endif
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#define STM32_HSE_BYPASS
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/*
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* Board voltages.
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* Required for performance limits calculation.
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*/
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#define STM32_VDD 300U |
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/*
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* MCU type as defined in the ST header.
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*/
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#define STM32L476xx
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/*
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* IO pins assignments.
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*/
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#define GPIOA_ARD_A0 0U |
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#define GPIOA_ACD12_IN5 0U |
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#define GPIOA_ARD_A1 1U |
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#define GPIOA_ACD12_IN6 1U |
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#define GPIOA_ARD_D1 2U |
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#define GPIOA_USART2_TX 2U |
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#define GPIOA_ARD_D0 3U |
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#define GPIOA_USART2_RX 3U |
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#define GPIOA_ARD_A2 4U |
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#define GPIOA_ACD12_IN9 4U |
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#define GPIOA_ARD_D13 5U |
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#define GPIOA_LED_GREEN 5U |
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#define GPIOA_ARD_D12 6U |
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#define GPIOA_ARD_D11 7U |
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#define GPIOA_ARD_D7 8U |
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#define GPIOA_ARD_D8 9U |
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#define GPIOA_ARD_D2 10U |
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#define GPIOA_PIN11 11U |
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#define GPIOA_PIN12 12U |
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#define GPIOA_SWDIO 13U |
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#define GPIOA_SWCLK 14U |
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#define GPIOA_PIN15 15U |
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#define GPIOB_ARD_A3 0U |
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#define GPIOB_ACD12_IN15 0U |
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#define GPIOB_PIN1 1U |
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#define GPIOB_PIN2 2U |
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#define GPIOB_ARD_D3 3U |
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#define GPIOB_SWO 3U |
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#define GPIOB_ARD_D5 4U |
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#define GPIOB_ARD_D4 5U |
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#define GPIOB_ARD_D10 6U |
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#define GPIOB_PIN7 7U |
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#define GPIOB_ARD_D15 8U |
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#define GPIOB_ARD_D14 9U |
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#define GPIOB_ARD_D6 10U |
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#define GPIOB_PIN11 11U |
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#define GPIOB_PIN12 12U |
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#define GPIOB_PIN13 13U |
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#define GPIOB_PIN14 14U |
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#define GPIOB_PIN15 15U |
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#define GPIOC_ARD_A5 0U |
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#define GPIOC_ACD123_IN1 0U |
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#define GPIOC_ARD_A4 1U |
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#define GPIOC_ACD123_IN2 1U |
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#define GPIOC_PIN2 2U |
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#define GPIOC_PIN3 3U |
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#define GPIOC_PIN4 4U |
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#define GPIOC_PIN5 5U |
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#define GPIOC_PIN6 6U |
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#define GPIOC_ARD_D9 7U |
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#define GPIOC_PIN8 8U |
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#define GPIOC_PIN9 9U |
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#define GPIOC_PIN10 10U |
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#define GPIOC_PIN11 11U |
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#define GPIOC_PIN12 12U |
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#define GPIOC_BUTTON 13U |
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#define GPIOC_OSC32_IN 14U |
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#define GPIOC_OSC32_OUT 15U |
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#define GPIOD_PIN0 0U |
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#define GPIOD_PIN1 1U |
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#define GPIOD_PIN2 2U |
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#define GPIOD_PIN3 3U |
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#define GPIOD_PIN4 4U |
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#define GPIOD_PIN5 5U |
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#define GPIOD_PIN6 6U |
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#define GPIOD_PIN7 7U |
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#define GPIOD_PIN8 8U |
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#define GPIOD_PIN9 9U |
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#define GPIOD_PIN10 10U |
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#define GPIOD_PIN11 11U |
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#define GPIOD_PIN12 12U |
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#define GPIOD_PIN13 13U |
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#define GPIOD_PIN14 14U |
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#define GPIOD_PIN15 15U |
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#define GPIOE_PIN0 0U |
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#define GPIOE_PIN1 1U |
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#define GPIOE_PIN2 2U |
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#define GPIOE_PIN3 3U |
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#define GPIOE_PIN4 4U |
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#define GPIOE_PIN5 5U |
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#define GPIOE_PIN6 6U |
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#define GPIOE_PIN7 7U |
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#define GPIOE_PIN8 8U |
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#define GPIOE_PIN9 9U |
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#define GPIOE_PIN10 10U |
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#define GPIOE_PIN11 11U |
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#define GPIOE_PIN12 12U |
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#define GPIOE_PIN13 13U |
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#define GPIOE_PIN14 14U |
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#define GPIOE_PIN15 15U |
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#define GPIOF_PIN0 0U |
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#define GPIOF_PIN1 1U |
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#define GPIOF_PIN2 2U |
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#define GPIOF_PIN3 3U |
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#define GPIOF_PIN4 4U |
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#define GPIOF_PIN5 5U |
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#define GPIOF_PIN6 6U |
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#define GPIOF_PIN7 7U |
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#define GPIOF_PIN8 8U |
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#define GPIOF_PIN9 9U |
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#define GPIOF_PIN10 10U |
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#define GPIOF_PIN11 11U |
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#define GPIOF_PIN12 12U |
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#define GPIOF_PIN13 13U |
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#define GPIOF_PIN14 14U |
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#define GPIOF_PIN15 15U |
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#define GPIOG_PIN0 0U |
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#define GPIOG_PIN1 1U |
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#define GPIOG_PIN2 2U |
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#define GPIOG_PIN3 3U |
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#define GPIOG_PIN4 4U |
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#define GPIOG_PIN5 5U |
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#define GPIOG_PIN6 6U |
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#define GPIOG_PIN7 7U |
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#define GPIOG_PIN8 8U |
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#define GPIOG_PIN9 9U |
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#define GPIOG_PIN10 10U |
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#define GPIOG_PIN11 11U |
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#define GPIOG_PIN12 12U |
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#define GPIOG_PIN13 13U |
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#define GPIOG_PIN14 14U |
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#define GPIOG_PIN15 15U |
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#define GPIOH_OSC_IN 0U |
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#define GPIOH_OSC_OUT 1U |
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#define GPIOH_PIN2 2U |
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#define GPIOH_PIN3 3U |
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#define GPIOH_PIN4 4U |
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#define GPIOH_PIN5 5U |
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#define GPIOH_PIN6 6U |
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#define GPIOH_PIN7 7U |
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#define GPIOH_PIN8 8U |
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#define GPIOH_PIN9 9U |
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#define GPIOH_PIN10 10U |
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#define GPIOH_PIN11 11U |
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#define GPIOH_PIN12 12U |
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#define GPIOH_PIN13 13U |
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#define GPIOH_PIN14 14U |
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#define GPIOH_PIN15 15U |
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/*
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* IO lines assignments.
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*/
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#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) |
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#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U) |
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#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) |
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#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U) |
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#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) |
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#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) |
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#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) |
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#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) |
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#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) |
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#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U) |
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#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) |
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#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) |
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#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) |
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#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) |
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#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) |
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#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) |
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#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) |
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#define LINE_SWDIO PAL_LINE(GPIOA, 13U) |
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#define LINE_SWCLK PAL_LINE(GPIOA, 14U) |
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#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) |
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#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U) |
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#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) |
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#define LINE_SWO PAL_LINE(GPIOB, 3U) |
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#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) |
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#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) |
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#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) |
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#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) |
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#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) |
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#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) |
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#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) |
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#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U) |
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#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) |
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#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U) |
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#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) |
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#define LINE_BUTTON PAL_LINE(GPIOC, 13U) |
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#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) |
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#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) |
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#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) |
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#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) |
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
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#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
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#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) |
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#define PIN_ODR_LOW(n) (0U << (n)) |
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#define PIN_ODR_HIGH(n) (1U << (n)) |
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#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
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#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
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#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) |
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#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) |
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#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) |
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#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) |
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#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) |
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#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) |
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#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) |
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#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) |
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#define PIN_ASCR_DISABLED(n) (0U << (n)) |
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#define PIN_ASCR_ENABLED(n) (1U << (n)) |
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#define PIN_LOCKR_DISABLED(n) (0U << (n)) |
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#define PIN_LOCKR_ENABLED(n) (1U << (n)) |
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/*
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* GPIOA setup:
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*
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* PA0 - ARD_A0 ACD12_IN5 (analog).
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* PA1 - ARD_A1 ACD12_IN6 (analog).
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* PA2 - ARD_D1 USART2_TX (alternate 7).
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* PA3 - ARD_D0 USART2_RX (alternate 7).
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* PA4 - ARD_A2 ACD12_IN9 (analog).
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* PA5 - ARD_D13 LED_GREEN (output pushpull maximum).
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* PA6 - ARD_D12 (analog).
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* PA7 - ARD_D11 (analog).
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* PA8 - ARD_D7 (analog).
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* PA9 - ARD_D8 (analog).
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* PA10 - ARD_D2 (analog).
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* PA11 - PIN11 (analog).
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* PA12 - PIN12 (analog).
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* PA13 - SWDIO (alternate 0).
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* PA14 - SWCLK (alternate 0).
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* PA15 - PIN15 (analog).
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*/
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#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \
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PIN_MODE_ANALOG(GPIOA_ARD_A1) | \ |
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PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ |
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PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_A2) | \ |
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PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D12) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D11) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D7) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D8) | \ |
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PIN_MODE_ANALOG(GPIOA_ARD_D2) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN11) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN12) | \ |
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PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ |
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PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ |
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PIN_MODE_ANALOG(GPIOA_PIN15)) |
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#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ |
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PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) |
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#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
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PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ |
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ |
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PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ |
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PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN11) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN12) | \ |
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PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ |
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PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ |
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PIN_OSPEED_HIGH(GPIOA_PIN15)) |
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#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \
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PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \ |
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PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ |
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PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ |
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PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ |
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PIN_PUPDR_FLOATING(GPIOA_PIN15)) |
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#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
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PIN_ODR_HIGH(GPIOA_ARD_A1) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D1) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D0) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_A2) | \ |
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PIN_ODR_LOW(GPIOA_ARD_D13) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D12) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D11) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D7) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D8) | \ |
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PIN_ODR_HIGH(GPIOA_ARD_D2) | \ |
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PIN_ODR_HIGH(GPIOA_PIN11) | \ |
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PIN_ODR_HIGH(GPIOA_PIN12) | \ |
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PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
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PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
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PIN_ODR_HIGH(GPIOA_PIN15)) |
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#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \
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PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \
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PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ |
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PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
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PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
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PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
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PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
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PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
|
414 |
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
|
415 |
PIN_AFIO_AF(GPIOA_PIN15, 0U))
|
416 |
#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \
|
417 |
PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ |
418 |
PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ |
419 |
PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ |
420 |
PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ |
421 |
PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \ |
422 |
PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \ |
423 |
PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \ |
424 |
PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \ |
425 |
PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \ |
426 |
PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ |
427 |
PIN_ASCR_DISABLED(GPIOA_PIN11) | \ |
428 |
PIN_ASCR_DISABLED(GPIOA_PIN12) | \ |
429 |
PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ |
430 |
PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ |
431 |
PIN_ASCR_DISABLED(GPIOA_PIN15)) |
432 |
#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \
|
433 |
PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ |
434 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ |
435 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ |
436 |
PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ |
437 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \ |
438 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \ |
439 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \ |
440 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \ |
441 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \ |
442 |
PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ |
443 |
PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ |
444 |
PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ |
445 |
PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ |
446 |
PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ |
447 |
PIN_LOCKR_DISABLED(GPIOA_PIN15)) |
448 |
|
449 |
/*
|
450 |
* GPIOB setup:
|
451 |
*
|
452 |
* PB0 - ARD_A3 ACD12_IN15 (analog).
|
453 |
* PB1 - PIN1 (analog).
|
454 |
* PB2 - PIN2 (analog).
|
455 |
* PB3 - ARD_D3 SWO (analog).
|
456 |
* PB4 - ARD_D5 (analog).
|
457 |
* PB5 - ARD_D4 (analog).
|
458 |
* PB6 - ARD_D10 (analog).
|
459 |
* PB7 - PIN7 (analog).
|
460 |
* PB8 - ARD_D15 (analog).
|
461 |
* PB9 - ARD_D14 (analog).
|
462 |
* PB10 - ARD_D6 (analog).
|
463 |
* PB11 - PIN11 (analog).
|
464 |
* PB12 - PIN12 (analog).
|
465 |
* PB13 - PIN13 (analog).
|
466 |
* PB14 - PIN14 (analog).
|
467 |
* PB15 - PIN15 (analog).
|
468 |
*/
|
469 |
#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \
|
470 |
PIN_MODE_ANALOG(GPIOB_PIN1) | \ |
471 |
PIN_MODE_ANALOG(GPIOB_PIN2) | \ |
472 |
PIN_MODE_ANALOG(GPIOB_ARD_D3) | \ |
473 |
PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ |
474 |
PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ |
475 |
PIN_MODE_ANALOG(GPIOB_ARD_D10) | \ |
476 |
PIN_MODE_ANALOG(GPIOB_PIN7) | \ |
477 |
PIN_MODE_ANALOG(GPIOB_ARD_D15) | \ |
478 |
PIN_MODE_ANALOG(GPIOB_ARD_D14) | \ |
479 |
PIN_MODE_ANALOG(GPIOB_ARD_D6) | \ |
480 |
PIN_MODE_ANALOG(GPIOB_PIN11) | \ |
481 |
PIN_MODE_ANALOG(GPIOB_PIN12) | \ |
482 |
PIN_MODE_ANALOG(GPIOB_PIN13) | \ |
483 |
PIN_MODE_ANALOG(GPIOB_PIN14) | \ |
484 |
PIN_MODE_ANALOG(GPIOB_PIN15)) |
485 |
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \
|
486 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ |
487 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ |
488 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ |
489 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ |
490 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ |
491 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \ |
492 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ |
493 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ |
494 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ |
495 |
PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ |
496 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ |
497 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ |
498 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ |
499 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ |
500 |
PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) |
501 |
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \
|
502 |
PIN_OSPEED_HIGH(GPIOB_PIN1) | \ |
503 |
PIN_OSPEED_HIGH(GPIOB_PIN2) | \ |
504 |
PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ |
505 |
PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ |
506 |
PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ |
507 |
PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \ |
508 |
PIN_OSPEED_HIGH(GPIOB_PIN7) | \ |
509 |
PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ |
510 |
PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ |
511 |
PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ |
512 |
PIN_OSPEED_HIGH(GPIOB_PIN11) | \ |
513 |
PIN_OSPEED_HIGH(GPIOB_PIN12) | \ |
514 |
PIN_OSPEED_HIGH(GPIOB_PIN13) | \ |
515 |
PIN_OSPEED_HIGH(GPIOB_PIN14) | \ |
516 |
PIN_OSPEED_HIGH(GPIOB_PIN15)) |
517 |
#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \
|
518 |
PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ |
519 |
PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ |
520 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \ |
521 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \ |
522 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \ |
523 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \ |
524 |
PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ |
525 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ |
526 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ |
527 |
PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \ |
528 |
PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ |
529 |
PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ |
530 |
PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ |
531 |
PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ |
532 |
PIN_PUPDR_FLOATING(GPIOB_PIN15)) |
533 |
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \
|
534 |
PIN_ODR_HIGH(GPIOB_PIN1) | \ |
535 |
PIN_ODR_HIGH(GPIOB_PIN2) | \ |
536 |
PIN_ODR_HIGH(GPIOB_ARD_D3) | \ |
537 |
PIN_ODR_HIGH(GPIOB_ARD_D5) | \ |
538 |
PIN_ODR_HIGH(GPIOB_ARD_D4) | \ |
539 |
PIN_ODR_HIGH(GPIOB_ARD_D10) | \ |
540 |
PIN_ODR_HIGH(GPIOB_PIN7) | \ |
541 |
PIN_ODR_HIGH(GPIOB_ARD_D15) | \ |
542 |
PIN_ODR_HIGH(GPIOB_ARD_D14) | \ |
543 |
PIN_ODR_HIGH(GPIOB_ARD_D6) | \ |
544 |
PIN_ODR_HIGH(GPIOB_PIN11) | \ |
545 |
PIN_ODR_HIGH(GPIOB_PIN12) | \ |
546 |
PIN_ODR_HIGH(GPIOB_PIN13) | \ |
547 |
PIN_ODR_HIGH(GPIOB_PIN14) | \ |
548 |
PIN_ODR_HIGH(GPIOB_PIN15)) |
549 |
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ |
550 |
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
|
551 |
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
|
552 |
PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \
|
553 |
PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
|
554 |
PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
|
555 |
PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
|
556 |
PIN_AFIO_AF(GPIOB_PIN7, 0U))
|
557 |
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \ |
558 |
PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
|
559 |
PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
|
560 |
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
|
561 |
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
|
562 |
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
|
563 |
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
|
564 |
PIN_AFIO_AF(GPIOB_PIN15, 0U))
|
565 |
#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \
|
566 |
PIN_ASCR_DISABLED(GPIOB_PIN1) | \ |
567 |
PIN_ASCR_DISABLED(GPIOB_PIN2) | \ |
568 |
PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \ |
569 |
PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \ |
570 |
PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \ |
571 |
PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \ |
572 |
PIN_ASCR_DISABLED(GPIOB_PIN7) | \ |
573 |
PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \ |
574 |
PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \ |
575 |
PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \ |
576 |
PIN_ASCR_DISABLED(GPIOB_PIN11) | \ |
577 |
PIN_ASCR_DISABLED(GPIOB_PIN12) | \ |
578 |
PIN_ASCR_DISABLED(GPIOB_PIN13) | \ |
579 |
PIN_ASCR_DISABLED(GPIOB_PIN14) | \ |
580 |
PIN_ASCR_DISABLED(GPIOB_PIN15)) |
581 |
#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \
|
582 |
PIN_LOCKR_DISABLED(GPIOB_PIN1) | \ |
583 |
PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ |
584 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \ |
585 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \ |
586 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \ |
587 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \ |
588 |
PIN_LOCKR_DISABLED(GPIOB_PIN7) | \ |
589 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \ |
590 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \ |
591 |
PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \ |
592 |
PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ |
593 |
PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ |
594 |
PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ |
595 |
PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ |
596 |
PIN_LOCKR_DISABLED(GPIOB_PIN15)) |
597 |
|
598 |
/*
|
599 |
* GPIOC setup:
|
600 |
*
|
601 |
* PC0 - ARD_A5 ACD123_IN1 (analog).
|
602 |
* PC1 - ARD_A4 ACD123_IN2 (analog).
|
603 |
* PC2 - PIN2 (analog).
|
604 |
* PC3 - PIN3 (analog).
|
605 |
* PC4 - PIN4 (analog).
|
606 |
* PC5 - PIN5 (analog).
|
607 |
* PC6 - PIN6 (analog).
|
608 |
* PC7 - ARD_D9 (analog).
|
609 |
* PC8 - PIN8 (analog).
|
610 |
* PC9 - PIN9 (analog).
|
611 |
* PC10 - PIN10 (analog).
|
612 |
* PC11 - PIN11 (analog).
|
613 |
* PC12 - PIN12 (analog).
|
614 |
* PC13 - BUTTON (input floating).
|
615 |
* PC14 - OSC32_IN (input floating).
|
616 |
* PC15 - OSC32_OUT (input floating).
|
617 |
*/
|
618 |
#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \
|
619 |
PIN_MODE_ANALOG(GPIOC_ARD_A4) | \ |
620 |
PIN_MODE_ANALOG(GPIOC_PIN2) | \ |
621 |
PIN_MODE_ANALOG(GPIOC_PIN3) | \ |
622 |
PIN_MODE_ANALOG(GPIOC_PIN4) | \ |
623 |
PIN_MODE_ANALOG(GPIOC_PIN5) | \ |
624 |
PIN_MODE_ANALOG(GPIOC_PIN6) | \ |
625 |
PIN_MODE_ANALOG(GPIOC_ARD_D9) | \ |
626 |
PIN_MODE_ANALOG(GPIOC_PIN8) | \ |
627 |
PIN_MODE_ANALOG(GPIOC_PIN9) | \ |
628 |
PIN_MODE_ANALOG(GPIOC_PIN10) | \ |
629 |
PIN_MODE_ANALOG(GPIOC_PIN11) | \ |
630 |
PIN_MODE_ANALOG(GPIOC_PIN12) | \ |
631 |
PIN_MODE_INPUT(GPIOC_BUTTON) | \ |
632 |
PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ |
633 |
PIN_MODE_INPUT(GPIOC_OSC32_OUT)) |
634 |
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
|
635 |
PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ |
636 |
PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ |
637 |
PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ |
638 |
PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ |
63 |