amiro-os / boards / PowerManagement / board.h @ 8dced1c9
History | View | Annotate | Download (16.87 KB)
1 |
#ifndef _BOARD_H_
|
---|---|
2 |
#define _BOARD_H_
|
3 |
|
4 |
/*
|
5 |
* Setup for AMiRo PowerManagement board.
|
6 |
*/
|
7 |
|
8 |
/*
|
9 |
* Board identifier.
|
10 |
*/
|
11 |
#define BOARD_POWER_MANAGEMENT
|
12 |
#define BOARD_NAME "AMiRo PowerManagement" |
13 |
#define BOARD_VERSION "1.1" |
14 |
|
15 |
/*
|
16 |
* Board frequencies.
|
17 |
*/
|
18 |
#define STM32_LSECLK 0 |
19 |
#define STM32_HSECLK 8000000 |
20 |
|
21 |
/*
|
22 |
* Board voltages.
|
23 |
* Required for performance limits calculation.
|
24 |
*/
|
25 |
#define STM32_VDD 330 |
26 |
|
27 |
/*
|
28 |
* MCU type as defined in the ST header file stm32f4xx.h.
|
29 |
*/
|
30 |
#define STM32F40_41xxx
|
31 |
|
32 |
/*
|
33 |
* IO pins assignments.
|
34 |
*/
|
35 |
#define GPIOA_WKUP 0 |
36 |
#define GPIOA_SYS_UART_TX 2 |
37 |
#define GPIOA_SYS_UART_RX 3 |
38 |
#define GPIOA_SYS_SPI_SS0_N 4 |
39 |
#define GPIOA_SYS_SPI_SCLK 5 |
40 |
#define GPIOA_SYS_SPI_MISO 6 |
41 |
#define GPIOA_SYS_SPI_MOSI 7 |
42 |
#define GPIOA_SYS_REG_EN 8 |
43 |
#define GPIOA_PROG_RX 9 |
44 |
#define GPIOA_PROG_TX 10 |
45 |
#define GPIOA_CAN_RX 11 |
46 |
#define GPIOA_CAN_TX 12 |
47 |
#define GPIOA_SYS_SPI_SS1_N 15 |
48 |
|
49 |
#define GPIOB_IR_INT1_N 0 |
50 |
#define GPIOB_VSYS_SENSE 1 |
51 |
#define GPIOB_POWER_EN 2 |
52 |
#define GPIOB_SYS_UART_DN 3 |
53 |
#define GPIOB_CHARGE_STAT2A 4 |
54 |
#define GPIOB_BUZZER 5 |
55 |
#define GPIOB_GAUGE_BATLOW2 6 |
56 |
#define GPIOB_GAUGE_BATGD2_N 7 |
57 |
#define GPIOB_GAUGE_SCL2 8 |
58 |
#define GPIOB_GAUGE_SDA2 9 |
59 |
#define GPIOB_GAUGE_SCL1 10 |
60 |
#define GPIOB_GAUGE_SDA1 11 |
61 |
#define GPIOB_LED 12 |
62 |
#define GPIOB_BT_RTS 13 |
63 |
#define GPIOB_BT_CTS 14 |
64 |
#define GPIOB_SYS_UART_UP 15 |
65 |
|
66 |
#define GPIOC_CHARGE_STAT1A 0 |
67 |
#define GPIOC_GAUGE_BATLOW1 1 |
68 |
#define GPIOC_GAUGE_BATGD1_N 2 |
69 |
#define GPIOC_CHARGE_EN1_N 3 |
70 |
#define GPIOC_IR_INT2_N 4 |
71 |
#define GPIOC_TOUCH_INT_N 5 |
72 |
#define GPIOC_SYS_DONE 6 |
73 |
#define GPIOC_SYS_PROG_N 7 |
74 |
#define GPIOC_PATH_DC 8 |
75 |
#define GPIOC_SYS_SPI_DIR 9 |
76 |
#define GPIOC_BT_RX 10 |
77 |
#define GPIOC_BT_TX 11 |
78 |
#define GPIOC_SYS_INT_N 12 |
79 |
#define GPIOC_SYS_PD_N 13 |
80 |
#define GPIOC_SYS_WARMRST_N 14 |
81 |
#define GPIOC_BT_RST 15 |
82 |
|
83 |
#define GPIOD_CHARGE_EN2_N 2 |
84 |
|
85 |
#define GPIOH_OSC_IN 0 |
86 |
#define GPIOH_OSC_OUT 1 |
87 |
|
88 |
/*
|
89 |
* I/O ports initial setup, this configuration is established soon after reset
|
90 |
* in the initialization code.
|
91 |
*/
|
92 |
#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) |
93 |
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) |
94 |
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) |
95 |
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) |
96 |
#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
97 |
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
98 |
#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) |
99 |
#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) |
100 |
#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) |
101 |
#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) |
102 |
#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) |
103 |
#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) |
104 |
#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) |
105 |
#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) |
106 |
|
107 |
/*
|
108 |
* Port A setup.
|
109 |
*/
|
110 |
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP) | \
|
111 |
PIN_MODE_INPUT(1) | \
|
112 |
PIN_MODE_ALTERNATE(GPIOA_SYS_UART_TX) | \ |
113 |
PIN_MODE_ALTERNATE(GPIOA_SYS_UART_RX) | \ |
114 |
PIN_MODE_INPUT(GPIOA_SYS_SPI_SS0_N) | \ |
115 |
PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_SCLK) | \ |
116 |
PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MOSI) | \ |
117 |
PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MISO) | \ |
118 |
PIN_MODE_INPUT(GPIOA_SYS_SPI_SS1_N) | \ |
119 |
PIN_MODE_ALTERNATE(GPIOA_PROG_RX) | \ |
120 |
PIN_MODE_ALTERNATE(GPIOA_PROG_TX) | \ |
121 |
PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \ |
122 |
PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \ |
123 |
PIN_MODE_INPUT(13) | \
|
124 |
PIN_MODE_INPUT(14) | \
|
125 |
PIN_MODE_OUTPUT(GPIOA_SYS_REG_EN)) |
126 |
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_SYS_UART_TX) | \
|
127 |
PIN_OTYPE_PUSHPULL(GPIOA_SYS_SPI_SS0_N) | \ |
128 |
PIN_OTYPE_PUSHPULL(GPIOA_PROG_RX) | \ |
129 |
PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \ |
130 |
PIN_OTYPE_PUSHPULL(GPIOA_SYS_REG_EN)) |
131 |
#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF |
132 |
#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_WKUP) | \
|
133 |
PIN_PUDR_PULLUP(1) | \
|
134 |
PIN_PUDR_FLOATING(GPIOA_SYS_UART_TX) | \ |
135 |
PIN_PUDR_FLOATING(GPIOA_SYS_UART_RX) | \ |
136 |
PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS0_N) | \ |
137 |
PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SCLK) | \ |
138 |
PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MOSI) | \ |
139 |
PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MISO) | \ |
140 |
PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS1_N) | \ |
141 |
PIN_PUDR_FLOATING(GPIOA_PROG_RX) | \ |
142 |
PIN_PUDR_PULLUP(GPIOA_PROG_TX) | \ |
143 |
PIN_PUDR_FLOATING(GPIOA_CAN_RX) | \ |
144 |
PIN_PUDR_FLOATING(GPIOA_CAN_TX) | \ |
145 |
PIN_PUDR_PULLUP(13) | \
|
146 |
PIN_PUDR_PULLUP(14) | \
|
147 |
PIN_PUDR_FLOATING(GPIOA_SYS_REG_EN)) |
148 |
|
149 |
#define VAL_GPIOA_ODR 0xFFFF |
150 |
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_SYS_UART_TX, 7) | \ |
151 |
PIN_AFIO_AF(GPIOA_SYS_UART_RX, 7) | \
|
152 |
PIN_AFIO_AF(GPIOA_SYS_SPI_SCLK, 5) | \
|
153 |
PIN_AFIO_AF(GPIOA_SYS_SPI_MISO, 5) | \
|
154 |
PIN_AFIO_AF(GPIOA_SYS_SPI_MOSI, 5))
|
155 |
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PROG_RX, 7) | \ |
156 |
PIN_AFIO_AF(GPIOA_PROG_TX, 7) | \
|
157 |
PIN_AFIO_AF(GPIOA_CAN_RX, 9) | \
|
158 |
PIN_AFIO_AF(GPIOA_CAN_TX, 9))
|
159 |
|
160 |
/*
|
161 |
* Port B setup.
|
162 |
*/
|
163 |
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_IR_INT1_N) | \
|
164 |
PIN_MODE_ANALOG(GPIOB_VSYS_SENSE) | \ |
165 |
PIN_MODE_OUTPUT(GPIOB_POWER_EN) | \ |
166 |
PIN_MODE_OUTPUT(GPIOB_SYS_UART_DN) | \ |
167 |
PIN_MODE_INPUT(GPIOB_CHARGE_STAT2A) | \ |
168 |
PIN_MODE_ALTERNATE(GPIOB_BUZZER) | \ |
169 |
PIN_MODE_INPUT(GPIOB_GAUGE_BATLOW2) | \ |
170 |
PIN_MODE_INPUT(GPIOB_GAUGE_BATGD2_N) | \ |
171 |
PIN_MODE_ALTERNATE(GPIOB_GAUGE_SCL2) | \ |
172 |
PIN_MODE_ALTERNATE(GPIOB_GAUGE_SDA2) | \ |
173 |
PIN_MODE_ALTERNATE(GPIOB_GAUGE_SCL1) | \ |
174 |
PIN_MODE_ALTERNATE(GPIOB_GAUGE_SDA1) | \ |
175 |
PIN_MODE_OUTPUT(GPIOB_LED) | \ |
176 |
PIN_MODE_ALTERNATE(GPIOB_BT_RTS) | \ |
177 |
PIN_MODE_ALTERNATE(GPIOB_BT_CTS) | \ |
178 |
PIN_MODE_OUTPUT(GPIOB_SYS_UART_UP)) |
179 |
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_POWER_EN) | \
|
180 |
PIN_OTYPE_OPENDRAIN(GPIOB_SYS_UART_DN) | \ |
181 |
PIN_OTYPE_PUSHPULL(GPIOB_BUZZER) | \ |
182 |
PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SCL2) | \ |
183 |
PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SDA2) | \ |
184 |
PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SCL1) | \ |
185 |
PIN_OTYPE_OPENDRAIN(GPIOB_GAUGE_SDA1) | \ |
186 |
PIN_OTYPE_OPENDRAIN(GPIOB_LED) | \ |
187 |
PIN_OTYPE_PUSHPULL(GPIOB_BT_CTS) | \ |
188 |
PIN_OTYPE_OPENDRAIN(GPIOB_SYS_UART_UP)) |
189 |
#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF |
190 |
#define VAL_GPIOB_PUPDR 0x00000000 |
191 |
#define VAL_GPIOB_ODR 0xFFFF |
192 |
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_BUZZER, 2)) |
193 |
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_GAUGE_SCL2, 4) | \ |
194 |
PIN_AFIO_AF(GPIOB_GAUGE_SDA2, 4) | \
|
195 |
PIN_AFIO_AF(GPIOB_GAUGE_SCL1, 4) | \
|
196 |
PIN_AFIO_AF(GPIOB_GAUGE_SDA1, 4) | \
|
197 |
PIN_AFIO_AF(GPIOB_BT_RTS, 7) | \
|
198 |
PIN_AFIO_AF(GPIOB_BT_CTS, 7))
|
199 |
|
200 |
/*
|
201 |
* Port C setup.
|
202 |
*/
|
203 |
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_CHARGE_STAT1A) | \
|
204 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATLOW1) | \ |
205 |
PIN_MODE_INPUT(GPIOC_GAUGE_BATGD1_N) | \ |
206 |
PIN_MODE_OUTPUT(GPIOC_CHARGE_EN1_N) | \ |
207 |
PIN_MODE_INPUT(GPIOC_IR_INT2_N) | \ |
208 |
PIN_MODE_INPUT(GPIOC_TOUCH_INT_N) | \ |
209 |
PIN_MODE_INPUT(GPIOC_SYS_DONE) | \ |
210 |
PIN_MODE_OUTPUT(GPIOC_SYS_PROG_N) | \ |
211 |
PIN_MODE_INPUT(GPIOC_PATH_DC) | \ |
212 |
PIN_MODE_OUTPUT(GPIOC_SYS_SPI_DIR) | \ |
213 |
PIN_MODE_ALTERNATE(GPIOC_BT_RX) | \ |
214 |
PIN_MODE_ALTERNATE(GPIOC_BT_TX) | \ |
215 |
PIN_MODE_OUTPUT(GPIOC_SYS_INT_N) | \ |
216 |
PIN_MODE_OUTPUT(GPIOC_SYS_PD_N) | \ |
217 |
PIN_MODE_OUTPUT(GPIOC_SYS_WARMRST_N) | \ |
218 |
PIN_MODE_OUTPUT(GPIOC_BT_RST)) |
219 |
#define VAL_GPIOC_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOC_CHARGE_EN1_N) | \
|
220 |
PIN_OTYPE_OPENDRAIN(GPIOC_SYS_PROG_N) | \ |
221 |
PIN_OTYPE_OPENDRAIN(GPIOC_SYS_SPI_DIR) | \ |
222 |
PIN_OTYPE_PUSHPULL(GPIOC_BT_RX) | \ |
223 |
PIN_OTYPE_OPENDRAIN(GPIOC_SYS_INT_N) | \ |
224 |
PIN_OTYPE_OPENDRAIN(GPIOC_SYS_PD_N) | \ |
225 |
PIN_OTYPE_OPENDRAIN(GPIOC_SYS_WARMRST_N) | \ |
226 |
PIN_OTYPE_OPENDRAIN(GPIOC_BT_RST)) |
227 |
#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF |
228 |
#define VAL_GPIOC_PUPDR 0x00000000 |
229 |
#define VAL_GPIOC_ODR 0xEEFF /* emulate open drain for PATH_DC. This is required to prevent accidental shortcuts. Furthermore, pull down SYS_INT_N to indicate the OS is starting */ |
230 |
#define VAL_GPIOC_AFRL 0x00000000 |
231 |
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_BT_RX, 7) | \ |
232 |
PIN_AFIO_AF(GPIOC_BT_TX, 7))
|
233 |
|
234 |
/*
|
235 |
* Port D setup.
|
236 |
*/
|
237 |
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \ |
238 |
PIN_MODE_INPUT(1) | \
|
239 |
PIN_MODE_OUTPUT(GPIOD_CHARGE_EN2_N) | \ |
240 |
PIN_MODE_INPUT(3) | \
|
241 |
PIN_MODE_INPUT(4) | \
|
242 |
PIN_MODE_INPUT(5) | \
|
243 |
PIN_MODE_INPUT(6) | \
|
244 |
PIN_MODE_INPUT(7) | \
|
245 |
PIN_MODE_INPUT(8) | \
|
246 |
PIN_MODE_INPUT(9) | \
|
247 |
PIN_MODE_INPUT(10) | \
|
248 |
PIN_MODE_INPUT(11) | \
|
249 |
PIN_MODE_INPUT(12) | \
|
250 |
PIN_MODE_INPUT(13) | \
|
251 |
PIN_MODE_INPUT(14) | \
|
252 |
PIN_MODE_INPUT(15))
|
253 |
#define VAL_GPIOD_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOD_CHARGE_EN2_N))
|
254 |
#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF |
255 |
#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \ |
256 |
PIN_PUDR_PULLUP(1) | \
|
257 |
PIN_PUDR_FLOATING(GPIOD_CHARGE_EN2_N) | \ |
258 |
PIN_PUDR_PULLUP(3) | \
|
259 |
PIN_PUDR_PULLUP(4) | \
|
260 |
PIN_PUDR_PULLUP(5) | \
|
261 |
PIN_PUDR_PULLUP(6) | \
|
262 |
PIN_PUDR_PULLUP(7) | \
|
263 |
PIN_PUDR_PULLUP(8) | \
|
264 |
PIN_PUDR_PULLUP(9) | \
|
265 |
PIN_PUDR_PULLUP(10) | \
|
266 |
PIN_PUDR_PULLUP(11) | \
|
267 |
PIN_PUDR_PULLUP(12) | \
|
268 |
PIN_PUDR_PULLUP(13) | \
|
269 |
PIN_PUDR_PULLUP(14) | \
|
270 |
PIN_PUDR_PULLUP(15))
|
271 |
#define VAL_GPIOD_ODR 0x0FFF |
272 |
#define VAL_GPIOD_AFRL 0x00000000 |
273 |
#define VAL_GPIOD_AFRH 0x00000000 |
274 |
|
275 |
/*
|
276 |
* Port E setup.
|
277 |
*/
|
278 |
#define VAL_GPIOE_MODER 0x00000000 |
279 |
#define VAL_GPIOE_OTYPER 0x00000000 |
280 |
#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF |
281 |
#define VAL_GPIOE_PUPDR 0xFFFFFFFF |
282 |
#define VAL_GPIOE_ODR 0xFFFF |
283 |
#define VAL_GPIOE_AFRL 0x00000000 |
284 |
#define VAL_GPIOE_AFRH 0x00000000 |
285 |
|
286 |
/*
|
287 |
* Port F setup.
|
288 |
* All input with pull-up.
|
289 |
*/
|
290 |
#define VAL_GPIOF_MODER 0x00000000 |
291 |
#define VAL_GPIOF_OTYPER 0x00000000 |
292 |
#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF |
293 |
#define VAL_GPIOF_PUPDR 0xFFFFFFFF |
294 |
#define VAL_GPIOF_ODR 0xFFFF |
295 |
#define VAL_GPIOF_AFRL 0x00000000 |
296 |
#define VAL_GPIOF_AFRH 0x00000000 |
297 |
|
298 |
/*
|
299 |
* Port G setup.
|
300 |
* All input with pull-up.
|
301 |
*/
|
302 |
#define VAL_GPIOG_MODER 0x00000000 |
303 |
#define VAL_GPIOG_OTYPER 0x00000000 |
304 |
#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF |
305 |
#define VAL_GPIOG_PUPDR 0xFFFFFFFF |
306 |
#define VAL_GPIOG_ODR 0xFFFF |
307 |
#define VAL_GPIOG_AFRL 0x00000000 |
308 |
#define VAL_GPIOG_AFRH 0x00000000 |
309 |
|
310 |
/*
|
311 |
* Port H setup.
|
312 |
*/
|
313 |
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
|
314 |
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ |
315 |
PIN_MODE_INPUT(2) | \
|
316 |
PIN_MODE_INPUT(3) | \
|
317 |
PIN_MODE_INPUT(4) | \
|
318 |
PIN_MODE_INPUT(5) | \
|
319 |
PIN_MODE_INPUT(6) | \
|
320 |
PIN_MODE_INPUT(7) | \
|
321 |
PIN_MODE_INPUT(8) | \
|
322 |
PIN_MODE_INPUT(9) | \
|
323 |
PIN_MODE_INPUT(10) | \
|
324 |
PIN_MODE_INPUT(11) | \
|
325 |
PIN_MODE_INPUT(12) | \
|
326 |
PIN_MODE_INPUT(13) | \
|
327 |
PIN_MODE_INPUT(14) | \
|
328 |
PIN_MODE_INPUT(15))
|
329 |
#define VAL_GPIOH_OTYPER 0x00000000 |
330 |
#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF |
331 |
#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
|
332 |
PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \ |
333 |
PIN_PUDR_PULLUP(2) | \
|
334 |
PIN_PUDR_PULLUP(3) | \
|
335 |
PIN_PUDR_PULLUP(4) | \
|
336 |
PIN_PUDR_PULLUP(5) | \
|
337 |
PIN_PUDR_PULLUP(6) | \
|
338 |
PIN_PUDR_PULLUP(7) | \
|
339 |
PIN_PUDR_PULLUP(8) | \
|
340 |
PIN_PUDR_PULLUP(9) | \
|
341 |
PIN_PUDR_PULLUP(10) | \
|
342 |
PIN_PUDR_PULLUP(11) | \
|
343 |
PIN_PUDR_PULLUP(12) | \
|
344 |
PIN_PUDR_PULLUP(13) | \
|
345 |
PIN_PUDR_PULLUP(14) | \
|
346 |
PIN_PUDR_PULLUP(15))
|
347 |
#define VAL_GPIOH_ODR 0xFFFF |
348 |
#define VAL_GPIOH_AFRL 0x00000000 |
349 |
#define VAL_GPIOH_AFRH 0x00000000 |
350 |
|
351 |
/*
|
352 |
* Port I setup.
|
353 |
* All input with pull-up.
|
354 |
*/
|
355 |
#define VAL_GPIOI_MODER 0x00000000 |
356 |
#define VAL_GPIOI_OTYPER 0x00000000 |
357 |
#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF |
358 |
#define VAL_GPIOI_PUPDR 0xFFFFFFFF |
359 |
#define VAL_GPIOI_ODR 0xFFFF |
360 |
#define VAL_GPIOI_AFRL 0x00000000 |
361 |
#define VAL_GPIOI_AFRH 0x00000000 |
362 |
|
363 |
#if !defined(_FROM_ASM_)
|
364 |
#ifdef __cplusplus
|
365 |
extern "C" { |
366 |
#endif
|
367 |
void boardInit(void); |
368 |
void boardWriteIoPower(int value); |
369 |
void boardWriteLed(int value); |
370 |
void boardWriteSystemPower(int value); |
371 |
void boardWriteWarmRestart(const uint8_t value); |
372 |
void boardChargerSetState(uint8_t chrg_mask, uint8_t state);
|
373 |
void boardBluetoothSetState(uint8_t state);
|
374 |
void boardRequestShutdown(void); |
375 |
void boardStandby(void); |
376 |
void boardStop(const uint8_t lpds, const uint8_t fpds); |
377 |
void boardWakeup(void); |
378 |
void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad); |
379 |
void boardResetBQ27500I2C(const uint8_t scl_pad, const uint8_t sda_pad); |
380 |
#ifdef __cplusplus
|
381 |
} |
382 |
#endif
|
383 |
#endif /* _FROM_ASM_ */ |
384 |
|
385 |
#endif /* _BOARD_H_ */ |