amiro-os / modules / RT-STM32L476RG-NUCLEO64 / mcuconf.h @ 960338cc
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1 | 27d0378b | Simon Welzel | /*
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2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License");
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5 | you may not use this file except in compliance with the License.
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6 | You may obtain a copy of the License at
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7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0
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9 | |||
10 | Unless required by applicable law or agreed to in writing, software
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11 | distributed under the License is distributed on an "AS IS" BASIS,
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12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | See the License for the specific language governing permissions and
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14 | limitations under the License.
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15 | */
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16 | |||
17 | #ifndef MCUCONF_H
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18 | #define MCUCONF_H
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19 | |||
20 | /*
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21 | * STM32L1xx drivers configuration.
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22 | * The following settings override the default settings present in
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23 | * the various device driver implementation headers.
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24 | * Note that the settings for each driver only have effect if the whole
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25 | * driver is enabled in halconf.h.
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26 | *
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27 | * IRQ priorities:
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28 | * 15...0 Lowest...Highest.
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29 | *
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30 | * DMA priorities:
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31 | * 0...3 Lowest...Highest.
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32 | */
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33 | |||
34 | #define STM32L4xx_MCUCONF
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35 | |||
36 | /*
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37 | * HAL driver system settings.
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38 | */
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39 | #define STM32_NO_INIT FALSE
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40 | #define STM32_VOS STM32_VOS_RANGE1
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41 | #define STM32_PVD_ENABLE FALSE
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42 | #define STM32_PLS STM32_PLS_LEV0
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43 | #define STM32_HSI16_ENABLED FALSE
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44 | #define STM32_LSI_ENABLED TRUE
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45 | #define STM32_HSE_ENABLED FALSE
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46 | #define STM32_LSE_ENABLED TRUE
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47 | #define STM32_MSIPLL_ENABLED TRUE
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48 | #define STM32_ADC_CLOCK_ENABLED TRUE
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49 | #define STM32_USB_CLOCK_ENABLED TRUE
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50 | #define STM32_SAI1_CLOCK_ENABLED TRUE
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51 | #define STM32_SAI2_CLOCK_ENABLED TRUE
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52 | #define STM32_MSIRANGE STM32_MSIRANGE_4M
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53 | #define STM32_MSISRANGE STM32_MSISRANGE_4M
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54 | #define STM32_SW STM32_SW_PLL
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55 | #define STM32_PLLSRC STM32_PLLSRC_MSI
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56 | #define STM32_PLLM_VALUE 1 |
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57 | #define STM32_PLLN_VALUE 80 |
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58 | #define STM32_PLLP_VALUE 7 |
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59 | #define STM32_PLLQ_VALUE 6 |
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60 | #define STM32_PLLR_VALUE 4 |
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61 | #define STM32_HPRE STM32_HPRE_DIV1
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62 | #define STM32_PPRE1 STM32_PPRE1_DIV1
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63 | #define STM32_PPRE2 STM32_PPRE2_DIV1
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64 | #define STM32_STOPWUCK STM32_STOPWUCK_MSI
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65 | #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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66 | #define STM32_MCOPRE STM32_MCOPRE_DIV1
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67 | #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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68 | #define STM32_PLLSAI1N_VALUE 72 |
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69 | #define STM32_PLLSAI1P_VALUE 7 |
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70 | #define STM32_PLLSAI1Q_VALUE 6 |
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71 | #define STM32_PLLSAI1R_VALUE 6 |
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72 | #define STM32_PLLSAI2N_VALUE 72 |
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73 | #define STM32_PLLSAI2P_VALUE 7 |
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74 | #define STM32_PLLSAI2R_VALUE 6 |
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75 | #define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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76 | #define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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77 | #define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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78 | #define STM32_UART4SEL STM32_UART4SEL_SYSCLK
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79 | #define STM32_UART5SEL STM32_UART5SEL_SYSCLK
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80 | #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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81 | #define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
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82 | #define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
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83 | #define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
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84 | #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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85 | #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
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86 | #define STM32_SAI1SEL STM32_SAI1SEL_OFF
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87 | #define STM32_SAI2SEL STM32_SAI2SEL_OFF
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88 | #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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89 | #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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90 | #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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91 | #define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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92 | #define STM32_RTCSEL STM32_RTCSEL_LSI
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93 | |||
94 | /*
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95 | * IRQ system settings.
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96 | */
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97 | #define STM32_IRQ_EXTI0_PRIORITY 6 |
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98 | #define STM32_IRQ_EXTI1_PRIORITY 6 |
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99 | #define STM32_IRQ_EXTI2_PRIORITY 6 |
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100 | #define STM32_IRQ_EXTI3_PRIORITY 6 |
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101 | #define STM32_IRQ_EXTI4_PRIORITY 6 |
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102 | #define STM32_IRQ_EXTI5_9_PRIORITY 6 |
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103 | #define STM32_IRQ_EXTI10_15_PRIORITY 6 |
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104 | #define STM32_IRQ_EXTI1635_38_PRIORITY 6 |
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105 | #define STM32_IRQ_EXTI18_PRIORITY 6 |
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106 | #define STM32_IRQ_EXTI19_PRIORITY 6 |
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107 | #define STM32_IRQ_EXTI20_PRIORITY 6 |
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108 | #define STM32_IRQ_EXTI21_22_PRIORITY 15 |
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109 | |||
110 | /*
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111 | * ADC driver system settings.
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112 | */
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113 | #define STM32_ADC_DUAL_MODE FALSE
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114 | #define STM32_ADC_COMPACT_SAMPLES FALSE
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115 | #define STM32_ADC_USE_ADC1 FALSE
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116 | #define STM32_ADC_USE_ADC2 FALSE
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117 | #define STM32_ADC_USE_ADC3 FALSE
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118 | #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
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119 | #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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120 | #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
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121 | #define STM32_ADC_ADC1_DMA_PRIORITY 2 |
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122 | #define STM32_ADC_ADC2_DMA_PRIORITY 2 |
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123 | #define STM32_ADC_ADC3_DMA_PRIORITY 2 |
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124 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
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125 | #define STM32_ADC_ADC3_IRQ_PRIORITY 5 |
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126 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
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127 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
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128 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
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129 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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130 | |||
131 | /*
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132 | * CAN driver system settings.
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133 | */
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134 | #define STM32_CAN_USE_CAN1 TRUE
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135 | #define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
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136 | |||
137 | /*
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138 | * DAC driver system settings.
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139 | */
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140 | #define STM32_DAC_DUAL_MODE FALSE
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141 | #define STM32_DAC_USE_DAC1_CH1 FALSE
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142 | #define STM32_DAC_USE_DAC1_CH2 FALSE
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143 | #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
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144 | #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
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145 | #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
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146 | #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
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147 | #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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148 | #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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149 | |||
150 | /*
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151 | * GPT driver system settings.
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152 | */
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153 | #define STM32_GPT_USE_TIM1 FALSE
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154 | #define STM32_GPT_USE_TIM2 FALSE
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155 | #define STM32_GPT_USE_TIM3 FALSE
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156 | #define STM32_GPT_USE_TIM4 FALSE
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157 | #define STM32_GPT_USE_TIM5 FALSE
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158 | #define STM32_GPT_USE_TIM6 FALSE
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159 | #define STM32_GPT_USE_TIM7 FALSE
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160 | #define STM32_GPT_USE_TIM8 FALSE
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161 | #define STM32_GPT_USE_TIM15 FALSE
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162 | #define STM32_GPT_USE_TIM16 FALSE
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163 | #define STM32_GPT_USE_TIM17 FALSE
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164 | #define STM32_GPT_TIM1_IRQ_PRIORITY 7 |
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165 | #define STM32_GPT_TIM2_IRQ_PRIORITY 7 |
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166 | #define STM32_GPT_TIM3_IRQ_PRIORITY 7 |
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167 | #define STM32_GPT_TIM4_IRQ_PRIORITY 7 |
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168 | #define STM32_GPT_TIM5_IRQ_PRIORITY 7 |
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169 | #define STM32_GPT_TIM6_IRQ_PRIORITY 7 |
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170 | #define STM32_GPT_TIM7_IRQ_PRIORITY 7 |
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171 | #define STM32_GPT_TIM8_IRQ_PRIORITY 7 |
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172 | #define STM32_GPT_TIM15_IRQ_PRIORITY 7 |
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173 | #define STM32_GPT_TIM16_IRQ_PRIORITY 7 |
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174 | #define STM32_GPT_TIM17_IRQ_PRIORITY 7 |
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175 | |||
176 | /*
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177 | * I2C driver system settings.
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178 | */
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179 | #define STM32_I2C_USE_I2C1 FALSE
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180 | #define STM32_I2C_USE_I2C2 FALSE
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181 | #define STM32_I2C_USE_I2C3 FALSE
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182 | #define STM32_I2C_BUSY_TIMEOUT 50 |
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183 | #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
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184 | #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
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185 | #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
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186 | #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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187 | #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
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188 | #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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189 | #define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
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190 | #define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
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191 | #define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
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192 | #define STM32_I2C_I2C1_DMA_PRIORITY 3 |
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193 | #define STM32_I2C_I2C2_DMA_PRIORITY 3 |
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194 | #define STM32_I2C_I2C3_DMA_PRIORITY 3 |
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195 | #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
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196 | |||
197 | /*
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198 | * ICU driver system settings.
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199 | */
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200 | #define STM32_ICU_USE_TIM1 FALSE
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201 | #define STM32_ICU_USE_TIM2 FALSE
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202 | #define STM32_ICU_USE_TIM3 FALSE
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203 | #define STM32_ICU_USE_TIM4 FALSE
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204 | #define STM32_ICU_USE_TIM5 FALSE
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205 | #define STM32_ICU_USE_TIM8 FALSE
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206 | #define STM32_ICU_TIM1_IRQ_PRIORITY 7 |
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207 | #define STM32_ICU_TIM2_IRQ_PRIORITY 7 |
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208 | #define STM32_ICU_TIM3_IRQ_PRIORITY 7 |
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209 | #define STM32_ICU_TIM4_IRQ_PRIORITY 7 |
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210 | #define STM32_ICU_TIM5_IRQ_PRIORITY 7 |
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211 | #define STM32_ICU_TIM8_IRQ_PRIORITY 7 |
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212 | |||
213 | /*
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214 | * PWM driver system settings.
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215 | */
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216 | #define STM32_PWM_USE_ADVANCED FALSE
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217 | #define STM32_PWM_USE_TIM1 FALSE
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218 | #define STM32_PWM_USE_TIM2 FALSE
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219 | #define STM32_PWM_USE_TIM3 FALSE
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220 | #define STM32_PWM_USE_TIM4 FALSE
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221 | #define STM32_PWM_USE_TIM5 FALSE
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222 | #define STM32_PWM_USE_TIM8 FALSE
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223 | #define STM32_PWM_TIM1_IRQ_PRIORITY 7 |
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224 | #define STM32_PWM_TIM2_IRQ_PRIORITY 7 |
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225 | #define STM32_PWM_TIM3_IRQ_PRIORITY 7 |
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226 | #define STM32_PWM_TIM4_IRQ_PRIORITY 7 |
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227 | #define STM32_PWM_TIM5_IRQ_PRIORITY 7 |
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228 | #define STM32_PWM_TIM8_IRQ_PRIORITY 7 |
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229 | |||
230 | /*
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231 | * QSPI driver system settings.
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232 | */
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233 | #define STM32_QSPI_USE_QUADSPI1 FALSE
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234 | #define STM32_QSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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235 | |||
236 | /*
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237 | * SDC driver system settings.
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238 | */
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239 | #define STM32_SDC_USE_SDMMC1 FALSE
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240 | #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
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241 | #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 |
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242 | #define STM32_SDC_SDMMC_READ_TIMEOUT 1000 |
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243 | #define STM32_SDC_SDMMC_CLOCK_DELAY 10 |
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244 | #define STM32_SDC_SDMMC1_DMA_PRIORITY 3 |
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245 | #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 |
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246 | #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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247 | |||
248 | /*
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249 | * SERIAL driver system settings.
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250 | */
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251 | #define STM32_SERIAL_USE_USART1 FALSE
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252 | #define STM32_SERIAL_USE_USART2 TRUE
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253 | #define STM32_SERIAL_USE_USART3 FALSE
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254 | #define STM32_SERIAL_USE_LPUART1 FALSE
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255 | #define STM32_SERIAL_USART1_PRIORITY 12 |
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256 | #define STM32_SERIAL_USART2_PRIORITY 12 |
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257 | #define STM32_SERIAL_USART3_PRIORITY 12 |
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258 | #define STM32_SERIAL_LPUART1_PRIORITY 12 |
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259 | |||
260 | /*
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261 | * SPI driver system settings.
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262 | */
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263 | #define STM32_SPI_USE_SPI1 FALSE
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264 | #define STM32_SPI_USE_SPI2 FALSE
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265 | #define STM32_SPI_USE_SPI3 FALSE
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266 | #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
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267 | #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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268 | #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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269 | #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
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270 | #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
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271 | #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
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272 | #define STM32_SPI_SPI1_DMA_PRIORITY 1 |
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273 | #define STM32_SPI_SPI2_DMA_PRIORITY 1 |
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274 | #define STM32_SPI_SPI3_DMA_PRIORITY 1 |
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275 | #define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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276 | #define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
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277 | #define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
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278 | #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
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279 | |||
280 | /*
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281 | * ST driver system settings.
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282 | */
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283 | #define STM32_ST_IRQ_PRIORITY 8 |
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284 | #define STM32_ST_USE_TIMER 2 |
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285 | |||
286 | /*
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287 | * UART driver system settings.
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288 | */
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289 | #define STM32_UART_USE_USART1 FALSE
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290 | #define STM32_UART_USE_USART2 TRUE
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291 | #define STM32_UART_USE_USART3 FALSE
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292 | #define STM32_UART_USE_UART4 FALSE
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293 | #define STM32_UART_USE_UART5 FALSE
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294 | #define STM32_UART_USE_LPUART1 FALSE
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295 | #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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296 | #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) |
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297 | #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
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298 | #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
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299 | #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
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300 | #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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301 | #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) |
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302 | #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
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303 | #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
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304 | #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
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305 | #define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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306 | #define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) |
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307 | #define STM32_UART_USART1_IRQ_PRIORITY 12 |
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308 | #define STM32_UART_USART2_IRQ_PRIORITY 12 |
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309 | #define STM32_UART_USART3_IRQ_PRIORITY 12 |
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310 | #define STM32_UART_UART4_IRQ_PRIORITY 12 |
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311 | #define STM32_UART_UART5_IRQ_PRIORITY 12 |
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312 | #define STM32_UART_USART1_DMA_PRIORITY 0 |
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313 | #define STM32_UART_USART2_DMA_PRIORITY 0 |
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314 | #define STM32_UART_USART3_DMA_PRIORITY 0 |
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315 | #define STM32_UART_UART4_DMA_PRIORITY 0 |
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316 | #define STM32_UART_UART5_DMA_PRIORITY 0 |
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317 | #define STM32_UART_LPUART1_DMA_PRIORITY 0 |
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318 | #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
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319 | |||
320 | /*
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321 | * USB driver system settings.
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322 | */
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323 | #define STM32_USB_USE_OTG1 FALSE
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324 | #define STM32_USB_OTG1_IRQ_PRIORITY 14 |
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325 | #define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
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326 | #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
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327 | #define STM32_USB_OTG_THREAD_STACK_SIZE 128 |
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328 | #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 |
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329 | |||
330 | /*
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331 | * WDG driver system settings.
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332 | */
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333 | #define STM32_WDG_USE_IWDG FALSE
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334 | |||
335 | #endif /* MCUCONF_H */ |