amiro-os / hal / platforms / STM32 / qei_lld.h @ a3c54343
History | View | Annotate | Download (7.388 KB)
| 1 |
/**
|
|---|---|
| 2 |
* @file STM32/qei_lld.h
|
| 3 |
* @brief STM32 QEI subsystem low level driver header.
|
| 4 |
*
|
| 5 |
* @addtogroup QEI
|
| 6 |
* @{
|
| 7 |
*/
|
| 8 |
|
| 9 |
#ifndef _QEI_LLD_H_
|
| 10 |
#define _QEI_LLD_H_
|
| 11 |
|
| 12 |
#include "stm32_tim.h" |
| 13 |
|
| 14 |
#if HAL_USE_QEI || defined(__DOXYGEN__)
|
| 15 |
|
| 16 |
/*===========================================================================*/
|
| 17 |
/* Driver constants. */
|
| 18 |
/*===========================================================================*/
|
| 19 |
|
| 20 |
/**
|
| 21 |
* @brief Number of input channels per QEI driver.
|
| 22 |
*/
|
| 23 |
#define QEI_CHANNELS 2 |
| 24 |
|
| 25 |
/*===========================================================================*/
|
| 26 |
/* Driver pre-compile time settings. */
|
| 27 |
/*===========================================================================*/
|
| 28 |
|
| 29 |
/**
|
| 30 |
* @name Configuration options
|
| 31 |
* @{
|
| 32 |
*/
|
| 33 |
/**
|
| 34 |
* @brief QEID1 driver enable switch.
|
| 35 |
* @details If set to @p TRUE the support for QEID1 is included.
|
| 36 |
* @note The default is @p TRUE.
|
| 37 |
*/
|
| 38 |
#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__)
|
| 39 |
#define STM32_QEI_USE_TIM1 TRUE
|
| 40 |
#endif
|
| 41 |
|
| 42 |
/**
|
| 43 |
* @brief QEID2 driver enable switch.
|
| 44 |
* @details If set to @p TRUE the support for QEID2 is included.
|
| 45 |
* @note The default is @p TRUE.
|
| 46 |
*/
|
| 47 |
#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__)
|
| 48 |
#define STM32_QEI_USE_TIM2 TRUE
|
| 49 |
#endif
|
| 50 |
|
| 51 |
/**
|
| 52 |
* @brief QEID3 driver enable switch.
|
| 53 |
* @details If set to @p TRUE the support for QEID3 is included.
|
| 54 |
* @note The default is @p TRUE.
|
| 55 |
*/
|
| 56 |
#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__)
|
| 57 |
#define STM32_QEI_USE_TIM3 TRUE
|
| 58 |
#endif
|
| 59 |
|
| 60 |
/**
|
| 61 |
* @brief QEID4 driver enable switch.
|
| 62 |
* @details If set to @p TRUE the support for QEID4 is included.
|
| 63 |
* @note The default is @p TRUE.
|
| 64 |
*/
|
| 65 |
#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__)
|
| 66 |
#define STM32_QEI_USE_TIM4 TRUE
|
| 67 |
#endif
|
| 68 |
|
| 69 |
/**
|
| 70 |
* @brief QEID5 driver enable switch.
|
| 71 |
* @details If set to @p TRUE the support for QEID5 is included.
|
| 72 |
* @note The default is @p TRUE.
|
| 73 |
*/
|
| 74 |
#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__)
|
| 75 |
#define STM32_QEI_USE_TIM5 TRUE
|
| 76 |
#endif
|
| 77 |
|
| 78 |
/**
|
| 79 |
* @brief QEID8 driver enable switch.
|
| 80 |
* @details If set to @p TRUE the support for QEID8 is included.
|
| 81 |
* @note The default is @p TRUE.
|
| 82 |
*/
|
| 83 |
#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__)
|
| 84 |
#define STM32_QEI_USE_TIM8 TRUE
|
| 85 |
#endif
|
| 86 |
/** @} */
|
| 87 |
|
| 88 |
/*===========================================================================*/
|
| 89 |
/* Derived constants and error checks. */
|
| 90 |
/*===========================================================================*/
|
| 91 |
|
| 92 |
#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1
|
| 93 |
#error "TIM1 not present in the selected device" |
| 94 |
#endif
|
| 95 |
|
| 96 |
#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2
|
| 97 |
#error "TIM2 not present in the selected device" |
| 98 |
#endif
|
| 99 |
|
| 100 |
#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3
|
| 101 |
#error "TIM3 not present in the selected device" |
| 102 |
#endif
|
| 103 |
|
| 104 |
#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4
|
| 105 |
#error "TIM4 not present in the selected device" |
| 106 |
#endif
|
| 107 |
|
| 108 |
#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5
|
| 109 |
#error "TIM5 not present in the selected device" |
| 110 |
#endif
|
| 111 |
|
| 112 |
#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8
|
| 113 |
#error "TIM8 not present in the selected device" |
| 114 |
#endif
|
| 115 |
|
| 116 |
#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \
|
| 117 |
!STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \ |
| 118 |
!STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8 |
| 119 |
#error "QEI driver activated but no TIM peripheral assigned" |
| 120 |
#endif
|
| 121 |
|
| 122 |
/*===========================================================================*/
|
| 123 |
/* Driver data structures and types. */
|
| 124 |
/*===========================================================================*/
|
| 125 |
|
| 126 |
/**
|
| 127 |
* @brief QEI driver mode.
|
| 128 |
*/
|
| 129 |
typedef enum { |
| 130 |
QEI_COUNT_BOTH = 0,
|
| 131 |
QEI_COUNT_CH1 = 1,
|
| 132 |
QEI_COUNT_CH2 = 2,
|
| 133 |
} qeimode_t; |
| 134 |
|
| 135 |
/**
|
| 136 |
* @brief QEI input mode.
|
| 137 |
*/
|
| 138 |
typedef enum { |
| 139 |
QEI_INPUT_NONINVERTED = 0, /**< Input channel noninverted.*/ |
| 140 |
QEI_INPUT_INVERTED = 1, /**< Input channel inverted.*/ |
| 141 |
} qeiinputmode_t; |
| 142 |
|
| 143 |
/**
|
| 144 |
* @brief QEI count type.
|
| 145 |
*/
|
| 146 |
typedef uint32_t qeicnt_t;
|
| 147 |
|
| 148 |
/**
|
| 149 |
* @brief Driver channel configuration structure.
|
| 150 |
*/
|
| 151 |
typedef struct { |
| 152 |
/**
|
| 153 |
* @brief Channel input logic.
|
| 154 |
*/
|
| 155 |
qeiinputmode_t mode; |
| 156 |
/* End of the mandatory fields.*/
|
| 157 |
} QEIChannelConfig; |
| 158 |
|
| 159 |
/**
|
| 160 |
* @brief Driver configuration structure.
|
| 161 |
*/
|
| 162 |
typedef struct { |
| 163 |
/**
|
| 164 |
* @brief Driver mode.
|
| 165 |
*/
|
| 166 |
qeimode_t mode; |
| 167 |
/**
|
| 168 |
* @brief Channels configurations.
|
| 169 |
*/
|
| 170 |
QEIChannelConfig channels[QEI_CHANNELS]; |
| 171 |
/**
|
| 172 |
* @brief Range in pulses.
|
| 173 |
*/
|
| 174 |
qeicnt_t range; |
| 175 |
/* End of the mandatory fields.*/
|
| 176 |
} QEIConfig; |
| 177 |
|
| 178 |
/**
|
| 179 |
* @brief Structure representing an QEI driver.
|
| 180 |
*/
|
| 181 |
struct QEIDriver {
|
| 182 |
/**
|
| 183 |
* @brief Driver state.
|
| 184 |
*/
|
| 185 |
qeistate_t state; |
| 186 |
/**
|
| 187 |
* @brief Current configuration data.
|
| 188 |
*/
|
| 189 |
const QEIConfig *config;
|
| 190 |
#if defined(QEI_DRIVER_EXT_FIELDS)
|
| 191 |
QEI_DRIVER_EXT_FIELDS |
| 192 |
#endif
|
| 193 |
/* End of the mandatory fields.*/
|
| 194 |
/**
|
| 195 |
* @brief Pointer to the TIMx registers block.
|
| 196 |
*/
|
| 197 |
stm32_tim_t *tim; |
| 198 |
}; |
| 199 |
|
| 200 |
/*===========================================================================*/
|
| 201 |
/* Driver macros. */
|
| 202 |
/*===========================================================================*/
|
| 203 |
|
| 204 |
/**
|
| 205 |
* @brief Returns the direction of the last transition.
|
| 206 |
* @details The direction is defined as boolean and is
|
| 207 |
* calculated at each transition on any input.
|
| 208 |
*
|
| 209 |
* @param[in] qeip pointer to the @p QEIDriver object
|
| 210 |
* @return The request direction.
|
| 211 |
* @retval FALSE Position counted up.
|
| 212 |
* @retval TRUE Position counted down.
|
| 213 |
*
|
| 214 |
* @iclass
|
| 215 |
*/
|
| 216 |
#define qei_lld_get_direction(qeip) !!((qeip)->tim->CR1 & TIM_CR1_DIR)
|
| 217 |
|
| 218 |
/**
|
| 219 |
* @brief Returns the position of the encoder.
|
| 220 |
* @details The position is defined as number of pulses since last reset.
|
| 221 |
*
|
| 222 |
* @param[in] qeip pointer to the @p QEIDriver object
|
| 223 |
* @return The number of pulses.
|
| 224 |
*
|
| 225 |
* @iclass
|
| 226 |
*/
|
| 227 |
#define qei_lld_get_position(qeip) ((qeip)->tim->CNT)
|
| 228 |
|
| 229 |
/**
|
| 230 |
* @brief Returns the range of the encoder.
|
| 231 |
* @details The range is defined as number of maximum pulse count.
|
| 232 |
*
|
| 233 |
* @param[in] qeip pointer to the @p QEIDriver object
|
| 234 |
* @return The number of pulses.
|
| 235 |
*
|
| 236 |
* @iclass
|
| 237 |
*/
|
| 238 |
#define qei_lld_get_range(qeip) ((qeip)->tim->ARR + 1) |
| 239 |
|
| 240 |
/*===========================================================================*/
|
| 241 |
/* External declarations. */
|
| 242 |
/*===========================================================================*/
|
| 243 |
|
| 244 |
#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__)
|
| 245 |
extern QEIDriver QEID1;
|
| 246 |
#endif
|
| 247 |
|
| 248 |
#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__)
|
| 249 |
extern QEIDriver QEID2;
|
| 250 |
#endif
|
| 251 |
|
| 252 |
#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__)
|
| 253 |
extern QEIDriver QEID3;
|
| 254 |
#endif
|
| 255 |
|
| 256 |
#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__)
|
| 257 |
extern QEIDriver QEID4;
|
| 258 |
#endif
|
| 259 |
|
| 260 |
#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__)
|
| 261 |
extern QEIDriver QEID5;
|
| 262 |
#endif
|
| 263 |
|
| 264 |
#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__)
|
| 265 |
extern QEIDriver QEID8;
|
| 266 |
#endif
|
| 267 |
|
| 268 |
#ifdef __cplusplus
|
| 269 |
extern "C" { |
| 270 |
#endif
|
| 271 |
void qei_lld_init(void); |
| 272 |
void qei_lld_start(QEIDriver *qeip);
|
| 273 |
void qei_lld_stop(QEIDriver *qeip);
|
| 274 |
void qei_lld_enable(QEIDriver *qeip);
|
| 275 |
void qei_lld_disable(QEIDriver *qeip);
|
| 276 |
#ifdef __cplusplus
|
| 277 |
} |
| 278 |
#endif
|
| 279 |
|
| 280 |
#endif /* HAL_USE_QEI */ |
| 281 |
|
| 282 |
#endif /* _QEI_LLD_H_ */ |
| 283 |
|
| 284 |
/** @} */
|