Revision abb8b3f4
| modules/DiWheelDrive_1-2/Makefile | ||
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################################################################################ |
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# AMiRo-OS is an operating system designed for the Autonomous Mini Robot # |
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# (AMiRo) platform. # |
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# Copyright (C) 2016..2019 Thomas Schöpping et al. # |
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# # |
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# This program is free software: you can redistribute it and/or modify # |
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# it under the terms of the GNU General Public License as published by # |
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# the Free Software Foundation, either version 3 of the License, or # |
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# (at your option) any later version. # |
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# # |
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# This program is distributed in the hope that it will be useful, # |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of # |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # |
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# GNU General Public License for more details. # |
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# # |
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# You should have received a copy of the GNU General Public License # |
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# along with this program. If not, see <http://www.gnu.org/licenses/>. # |
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# # |
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# This research/work was supported by the Cluster of Excellence Cognitive # |
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# Interaction Technology 'CITEC' (EXC 277) at Bielefeld University, which is # |
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# funded by the German Research Foundation (DFG). # |
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################################################################################ |
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################################################################################ |
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# Build global options # |
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# NOTE: Can be overridden externally. # |
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# # |
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# Compiler options here. |
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ifeq ($(USE_OPT),) |
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USE_OPT = -O2 -fstack-usage |
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endif |
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# C specific options here (added to USE_OPT). |
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ifeq ($(USE_COPT),) |
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USE_COPT = -std=c17 |
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endif |
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|
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# C++ specific options here (added to USE_OPT). |
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ifeq ($(USE_CPPOPT),) |
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USE_CPPOPT = -fno-rtti -std=c++17 |
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endif |
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|
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# Enable this if you want the linker to remove unused code and data. |
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ifeq ($(USE_LINK_GC),) |
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USE_LINK_GC = yes |
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endif |
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# Linker extra options here. |
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ifeq ($(USE_LDOPT),) |
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USE_LDOPT = |
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endif |
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# Enable this if you want link time optimizations (LTO). |
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ifeq ($(USE_LTO),) |
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USE_LTO = yes |
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endif |
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# Enable this if you want to see the full log while compiling. |
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ifeq ($(USE_VERBOSE_COMPILE),) |
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USE_VERBOSE_COMPILE = no |
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endif |
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# If enabled, this option makes the build process faster by not compiling |
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# modules not used in the current configuration. |
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ifeq ($(USE_SMART_BUILD),) |
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USE_SMART_BUILD = no |
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endif |
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# # |
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# Build global options # |
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################################################################################ |
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################################################################################ |
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# Architecture or project specific options # |
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# # |
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# Stack size to be allocated to the Cortex-M process stack. This stack is |
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# the stack used by the main() thread. |
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ifeq ($(USE_PROCESS_STACKSIZE),) |
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USE_PROCESS_STACKSIZE = 0x400 |
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endif |
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|
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# Stack size to the allocated to the Cortex-M main/exceptions stack. This |
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# stack is used for processing interrupts and exceptions. |
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ifeq ($(USE_EXCEPTIONS_STACKSIZE),) |
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USE_EXCEPTIONS_STACKSIZE = 0x400 |
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endif |
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# Enables the use of FPU. |
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# Possible selections are: |
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# no - no FPU is used (probably equals 'soft') |
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# soft - does not use the FPU, thus all floating point operations are emulated |
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# softfp - uses the FPU, but uses the integer registers only |
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# hard - uses the FPU and passes data via the FPU registers |
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ifeq ($(USE_FPU),) |
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USE_FPU = no |
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endif |
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# FPU-related options. |
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ifeq ($(USE_FPU_OPT),) |
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USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 |
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endif |
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# # |
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# Architecture or project specific options # |
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################################################################################ |
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################################################################################ |
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# Project, target, sources and paths # |
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# # |
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# Absolute path to the project |
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PROJECT_PATH := $(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST))))) |
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# Define project name here |
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PROJECT := $(patsubst $(abspath $(dir $(abspath $(lastword $(MAKEFILE_LIST))))..)/%,%,$(PROJECT_PATH)) |
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# Target settings. |
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MCU = cortex-m3 |
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# Imported source files and paths. |
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include ../../kernel/kernel.mk |
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CHIBIOS := $(AMIROOS_KERNEL) |
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CONFDIR := . |
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ifeq ($(BUILDDIR),) |
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BUILDDIR := $(PROJECT_PATH)/build |
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endif |
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DEPDIR := $(dir $(BUILDDIR)).dep |
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AMIROOS := ../.. |
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# Licensing files. |
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include $(CHIBIOS)/os/license/license.mk |
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# Startup files. |
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk |
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# HAL-OSAL files (optional). |
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include $(CHIBIOS)/os/hal/hal.mk |
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include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk |
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk |
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include $(CHIBIOS)/os/hal/lib/streams/streams.mk |
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# RTOS files (optional). |
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include $(CHIBIOS)/os/rt/rt.mk |
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk |
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# Auto-build files in ./source recursively. |
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include $(CHIBIOS)/tools/mk/autobuild.mk |
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# Other files (optional). |
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include $(CHIBIOS)/test/lib/test.mk |
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include $(CHIBIOS)/test/rt/rt_test.mk |
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include $(CHIBIOS)/test/oslib/oslib_test.mk |
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# AMiRo-BLT files |
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include ../../bootloader/bootloader.mk |
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# AMiRo-LLD files |
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include ../../periphery-lld/periphery-lld.mk |
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# AMiRo-OS files |
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include ../modules.mk |
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include $(AMIROOS)/core/core.mk |
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include $(AMIROOS)/unittests/unittests.mk |
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# Define linker script file here |
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LDSCRIPT= STM32F103xE.ld |
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# C sources that can be compiled in ARM or THUMB mode depending on the global |
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# setting. |
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CSRC = $(ALLCSRC) \ |
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$(CHIBIOS)/os/various/syscalls.c \ |
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$(CHIBIOS)/os/various/evtimer.c \ |
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$(TESTSRC) \ |
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board.c \ |
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$(PERIPHERYLLDCSRC) \ |
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$(UNITTESTSCSRC) \ |
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$(AMIROOSCORECSRC) \ |
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$(MODULESCSRC) \ |
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module.c \ |
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$(APPSCSRC) |
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global |
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# setting. |
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CPPSRC = $(ALLCPPSRC) \ |
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$(CHIBIOS)/os/various/cpp_wrappers/syscalls_cpp.cpp \ |
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$(AMIROOSCORECPPSRC) \ |
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$(APPSCPPSRC) |
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# List ASM source files here. |
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ASMSRC = $(ALLASMSRC) \ |
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$(APPSASMSRC) |
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# List ASM with preprocessor source files here. |
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ASMXSRC = $(ALLXASMSRC) \ |
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$(APPSASMXSRC) |
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# Inclusion directories. |
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INCDIR = $(CONFDIR) \ |
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$(ALLINC) \ |
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$(TESTINC) \ |
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$(CHIBIOS)/os/hal/lib/streams \ |
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$(BOOTLOADERINC) \ |
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$(PERIPHERYLLDINC) \ |
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$(AMIROOS) \ |
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$(UNITTESTSINC) \ |
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$(AMIROOSCOREINC) \ |
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$(MODULESINC) \ |
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$(APPSINC) |
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# Define C warning options here. |
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CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes |
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# Define C++ warning options here. |
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CPPWARN = -Wall -Wextra -Wundef |
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# Create an additional .srec image file. |
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SREC = $(CP) -O srec --srec-len=248 |
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# # |
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# Project, target, sources and paths # |
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################################################################################ |
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################################################################################ |
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# Start of user section # |
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# # |
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# List all user C define here, like -D_DEBUG=1 |
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UDEFS += |
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# Define ASM defines here |
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UADEFS += |
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# List all user directories here |
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UINCDIR += |
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# List the user directory to look for the libraries here |
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ULIBDIR += |
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# List all user libraries here |
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ULIBS += |
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# # |
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# End of user section # |
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################################################################################ |
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################################################################################ |
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# Common rules # |
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# # |
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RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk |
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include $(RULESPATH)/arm-none-eabi.mk |
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include $(RULESPATH)/rules.mk |
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# # |
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# Common rules # |
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################################################################################ |
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################################################################################ |
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# Custom rules # |
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# # |
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FLASH_MODULES = $(PROJECT) |
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FLASH_FILES = $(BUILDDIR)/$(PROJECT).$(FLASHTOOL_EXT) |
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flash: $(FLASH_FILES) |
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$(info ) |
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ifeq ($(FLASHTOOL),SerialBoot) |
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$(info Flashing ($(FLASHTOOL)):) |
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$(FLASHTOOL_CMD) $(FLASHTOOL_ARGS) |
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else |
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$(info ERROR: unable to flash the module (SerialBoot unavailable)) |
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endif |
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# # |
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# Custom rules # |
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################################################################################ |
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|
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| modules/DiWheelDrive_1-2/STM32F103xE.ld | ||
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/* |
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
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Copyright (C) 2016..2019 Thomas Schöpping et al. |
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|
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This program is free software: you can redistribute it and/or modify |
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| 6 |
it under the terms of the GNU General Public License as published by |
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| 7 |
the Free Software Foundation, either version 3 of the License, or |
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| 8 |
(at your option) any later version. |
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| 9 |
|
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| 10 |
This program is distributed in the hope that it will be useful, |
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| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
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| 15 |
You should have received a copy of the GNU General Public License |
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along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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/* |
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* ST32F103xE memory setup. |
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*/ |
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MEMORY |
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{
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flash0 : org = 0x08006000, len = 512k-24k |
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flash1 : org = 0x00000000, len = 0 |
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flash2 : org = 0x00000000, len = 0 |
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flash3 : org = 0x00000000, len = 0 |
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flash4 : org = 0x00000000, len = 0 |
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flash5 : org = 0x00000000, len = 0 |
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flash6 : org = 0x00000000, len = 0 |
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flash7 : org = 0x00000000, len = 0 |
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ram0 : org = 0x20000000, len = 64k |
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ram1 : org = 0x00000000, len = 0 |
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ram2 : org = 0x00000000, len = 0 |
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ram3 : org = 0x00000000, len = 0 |
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ram4 : org = 0x00000000, len = 0 |
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ram5 : org = 0x00000000, len = 0 |
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ram6 : org = 0x00000000, len = 0 |
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ram7 : org = 0x00000000, len = 0 |
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} |
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|
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/* For each data/text section two region are defined, a virtual region |
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and a load region (_LMA suffix).*/ |
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/* Flash region to be used for exception vectors.*/ |
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/ |
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/ |
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/ |
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/ |
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/ |
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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|
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/* RAM region to be used for Main stack. This stack accommodates the processing |
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of all exceptions and interrupts.*/ |
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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|
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/* RAM region to be used for the process stack. This is the stack used by |
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the main() function.*/ |
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
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|
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/* RAM region to be used for data segment.*/ |
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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|
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/* RAM region to be used for BSS segment.*/ |
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REGION_ALIAS("BSS_RAM", ram0);
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|
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/* RAM region to be used for the default heap.*/ |
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REGION_ALIAS("HEAP_RAM", ram0);
|
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|
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/* Generic rules inclusion.*/ |
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INCLUDE rules.ld |
|
| modules/DiWheelDrive_1-2/alldconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
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| 18 |
|
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/** |
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* @file |
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* @brief AMiRo-LLD configuration file for the DiWheelDrive v1.2 module. |
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| 22 |
* @details Contains the application specific AMiRo-LLD settings. |
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* |
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* @addtogroup diwheeldrive_lld_config |
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* @{
|
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*/ |
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|
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#ifndef ALLDCONF_H |
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#define ALLDCONF_H |
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|
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/* |
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* compatibility guards |
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*/ |
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#define _AMIRO_LLD_CFG_ |
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#define AMIRO_LLD_CFG_VERSION_MAJOR 1 |
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| 36 |
#define AMIRO_LLD_CFG_VERSION_MINOR 0 |
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| 37 |
|
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| 38 |
/** |
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| 39 |
* @brief Width of the apalTime_t data type. |
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| 40 |
* |
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| 41 |
* @details Possible values are 8, 16, 32, and 64 bits. |
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| 42 |
* By definition time is represented at microsecond precision. |
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| 43 |
*/ |
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| 44 |
#define AMIROLLD_CFG_TIME_SIZE 32 |
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| 45 |
|
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| 46 |
/** |
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| 47 |
* @brief Enable flag for the A3906 motor driver. |
|
| 48 |
*/ |
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| 49 |
#define AMIROLLD_CFG_A3906 1 |
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| 50 |
|
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| 51 |
/** |
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| 52 |
* @brief Enable flag for the AT24C01BN-SH-B EEPROM. |
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| 53 |
*/ |
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| 54 |
#define AMIROLLD_CFG_AT24C01B 1 |
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| 55 |
|
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| 56 |
/** |
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| 57 |
* @brief Enable flag for the BNO055 IMU. |
|
| 58 |
*/ |
|
| 59 |
#define AMIROLLD_CFG_BNO055 1 |
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| 60 |
|
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| 61 |
/** |
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| 62 |
* @brief Enable flag for the INA219 power monitor. |
|
| 63 |
*/ |
|
| 64 |
#define AMIROLLD_CFG_INA219 1 |
|
| 65 |
|
|
| 66 |
/** |
|
| 67 |
* @brief Enable flag for the status LED. |
|
| 68 |
*/ |
|
| 69 |
#define AMIROLLD_CFG_LED 1 |
|
| 70 |
|
|
| 71 |
/** |
|
| 72 |
* @brief Enable flag for the LTC4412 power path controller. |
|
| 73 |
*/ |
|
| 74 |
#define AMIROLLD_CFG_LTC4412 1 |
|
| 75 |
|
|
| 76 |
/** |
|
| 77 |
* @brief Enable flag for the PCA9544A I2C multiplexer. |
|
| 78 |
*/ |
|
| 79 |
#define AMIROLLD_CFG_PCA9544A 1 |
|
| 80 |
|
|
| 81 |
/** |
|
| 82 |
* @brief Enable flag for the TPS62113 step-down converter. |
|
| 83 |
*/ |
|
| 84 |
#define AMIROLLD_CFG_TPS6211x 1 |
|
| 85 |
|
|
| 86 |
/** |
|
| 87 |
* @brief Enable flag for the VCNL4020 proximity sensor. |
|
| 88 |
*/ |
|
| 89 |
#define AMIROLLD_CFG_VCNL4020 1 |
|
| 90 |
|
|
| 91 |
#endif /* ALLDCONF_H */ |
|
| 92 |
|
|
| 93 |
/** @} */ |
|
| modules/DiWheelDrive_1-2/aosconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief AMiRo-OS Configuration file for the DiWheelDrive v1.2 module. |
|
| 22 |
* @details Contains the application specific AMiRo-OS settings. |
|
| 23 |
* |
|
| 24 |
* @addtogroup diwheeldrive_aos_config |
|
| 25 |
* @{
|
|
| 26 |
*/ |
|
| 27 |
|
|
| 28 |
#ifndef AOSCONF_H |
|
| 29 |
#define AOSCONF_H |
|
| 30 |
|
|
| 31 |
/* |
|
| 32 |
* compatibility guards |
|
| 33 |
*/ |
|
| 34 |
#define _AMIRO_OS_CFG_ |
|
| 35 |
#define AMIRO_OS_CFG_VERSION_MAJOR 2 |
|
| 36 |
#define AMIRO_OS_CFG_VERSION_MINOR 0 |
|
| 37 |
|
|
| 38 |
#include <stdbool.h> |
|
| 39 |
|
|
| 40 |
/* |
|
| 41 |
* Include an external configuration file to override the following default settings only if required. |
|
| 42 |
*/ |
|
| 43 |
#if defined(AMIRO_APPS) && (AMIRO_APPS == true) |
|
| 44 |
#include <osconf.h> |
|
| 45 |
#endif /* defined(AMIRO_APPS) && (AMIRO_APPS == true) */ |
|
| 46 |
|
|
| 47 |
/*===========================================================================*/ |
|
| 48 |
/** |
|
| 49 |
* @name Kernel parameters and options |
|
| 50 |
* @{
|
|
| 51 |
*/ |
|
| 52 |
/*===========================================================================*/ |
|
| 53 |
|
|
| 54 |
/** |
|
| 55 |
* @brief Flag to enable/disable debug API and logic. |
|
| 56 |
*/ |
|
| 57 |
#if !defined(OS_CFG_DBG) |
|
| 58 |
#define AMIROOS_CFG_DBG true |
|
| 59 |
#else /* !defined(OS_CFG_DBG) */ |
|
| 60 |
#define AMIROOS_CFG_DBG OS_CFG_DBG |
|
| 61 |
#endif /* !defined(OS_CFG_DBG) */ |
|
| 62 |
|
|
| 63 |
/** |
|
| 64 |
* @brief Flag to enable/disable unit tests. |
|
| 65 |
* @note Setting this flag will implicitely enable the shell. |
|
| 66 |
*/ |
|
| 67 |
#if !defined(OS_CFG_TESTS_ENABLE) |
|
| 68 |
#define AMIROOS_CFG_TESTS_ENABLE true |
|
| 69 |
#else /* !defined(OS_CFG_TESTS_ENABLE) */ |
|
| 70 |
#define AMIROOS_CFG_TESTS_ENABLE OS_CFG_TESTS_ENABLE |
|
| 71 |
#endif /* !defined(OS_CFG_TESTS_ENABLE) */ |
|
| 72 |
|
|
| 73 |
/** |
|
| 74 |
* @brief Flag to enable/disable profiling API and logic. |
|
| 75 |
*/ |
|
| 76 |
#if !defined(OS_CFG_PROFILE) |
|
| 77 |
#define AMIROOS_CFG_PROFILE true |
|
| 78 |
#else /* !defined(OS_CFG_PROFILE) */ |
|
| 79 |
#define AMIROOS_CFG_PROFILE OS_CFG_PROFILE |
|
| 80 |
#endif /* !defined(OS_CFG_PROFILE) */ |
|
| 81 |
|
|
| 82 |
/** |
|
| 83 |
* @brief Mask for the control thread to listen to certain IO events. |
|
| 84 |
* @note Any mandatory events (e.g. for SSSP) are enabled implicitely despite this configuration. |
|
| 85 |
*/ |
|
| 86 |
#if !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) |
|
| 87 |
#define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK 0 |
|
| 88 |
#else /* !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) */ |
|
| 89 |
#define AMIROOS_CFG_MAIN_LOOP_IOEVENT_MASK OS_CFG_MAIN_LOOP_IOEVENT_MASK |
|
| 90 |
#endif /* !defined(OS_CFG_MAIN_LOOP_IOEVENT_MASK) */ |
|
| 91 |
|
|
| 92 |
/** |
|
| 93 |
* @brief Timeout value when waiting for events in the main loop in microseconds. |
|
| 94 |
* @details A value of 0 deactivates the timeout. |
|
| 95 |
*/ |
|
| 96 |
#if !defined(OS_CFG_MAIN_LOOP_TIMEOUT) |
|
| 97 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT 0 |
|
| 98 |
#else /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */ |
|
| 99 |
#define AMIROOS_CFG_MAIN_LOOP_TIMEOUT OS_CFG_MAIN_LOOP_TIMEOUT |
|
| 100 |
#endif /* !defined(OS_CFG_MAIN_LOOP_TIMEOUT) */ |
|
| 101 |
|
|
| 102 |
/** @} */ |
|
| 103 |
|
|
| 104 |
/*===========================================================================*/ |
|
| 105 |
/** |
|
| 106 |
* @name SSSP (Startup Shutdown Synchronization Protocol) configuration. |
|
| 107 |
* @{
|
|
| 108 |
*/ |
|
| 109 |
/*===========================================================================*/ |
|
| 110 |
|
|
| 111 |
/** |
|
| 112 |
* @brief Flag to enable SSSP. |
|
| 113 |
*/ |
|
| 114 |
#if !defined(OS_CFG_SSSP_ENABLE) |
|
| 115 |
#define AMIROOS_CFG_SSSP_ENABLE true |
|
| 116 |
#else /* !defined(OS_CFG_SSSP_ENABLE) */ |
|
| 117 |
#define AMIROOS_CFG_SSSP_ENABLE OS_CFG_SSSP_ENABLE |
|
| 118 |
#endif /* !defined(OS_CFG_SSSP_ENABLE) */ |
|
| 119 |
|
|
| 120 |
/** |
|
| 121 |
* @brief Flag to set the module as SSSP master. |
|
| 122 |
* @details There must be only one module with this flag set to true in a system. |
|
| 123 |
*/ |
|
| 124 |
#if !defined(OS_CFG_SSSP_MASTER) |
|
| 125 |
#define AMIROOS_CFG_SSSP_MASTER false |
|
| 126 |
#else /* !defined(OS_CFG_SSSP_MASTER) */ |
|
| 127 |
#define AMIROOS_CFG_SSSP_MASTER OS_CFG_SSSP_MASTER |
|
| 128 |
#endif /* !defined(OS_CFG_SSSP_MASTER) */ |
|
| 129 |
|
|
| 130 |
/** |
|
| 131 |
* @brief Flag to set the module to be the first in the stack. |
|
| 132 |
* @details There must be only one module with this flag set to true in a system. |
|
| 133 |
*/ |
|
| 134 |
#if !defined(OS_CFG_SSSP_STACK_START) |
|
| 135 |
#define AMIROOS_CFG_SSSP_STACK_START true |
|
| 136 |
#else /* !defined(OS_CFG_SSSP_STACK_START) */ |
|
| 137 |
#define AMIROOS_CFG_SSSP_STACK_START OS_CFG_SSSP_STACK_START |
|
| 138 |
#endif /* !defined(OS_CFG_SSSP_STACK_START) */ |
|
| 139 |
|
|
| 140 |
/** |
|
| 141 |
* @brief Flag to set the module to be the last in the stack. |
|
| 142 |
* @details There must be only one module with this flag set to true in a system. |
|
| 143 |
*/ |
|
| 144 |
#if !defined(OS_CFG_SSSP_STACK_END) |
|
| 145 |
#define AMIROOS_CFG_SSSP_STACK_END false |
|
| 146 |
#else /* !defined(OS_CFG_SSSP_STACK_END) */ |
|
| 147 |
#define AMIROOS_CFG_SSSP_STACK_END OS_CFG_SSSP_STACK_END |
|
| 148 |
#endif /* !defined(OS_CFG_SSSP_STACK_END) */ |
|
| 149 |
|
|
| 150 |
/** |
|
| 151 |
* @brief Delay time (in microseconds) how long a SSSP signal must be active. |
|
| 152 |
*/ |
|
| 153 |
#if !defined(OS_CFG_SSSP_SIGNALDELAY) |
|
| 154 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY 1000 |
|
| 155 |
#else /* !defined(OS_CFG_SSSP_SIGNALDELAY) */ |
|
| 156 |
#define AMIROOS_CFG_SSSP_SIGNALDELAY OS_CFG_SSSP_SIGNALDELAY |
|
| 157 |
#endif /* !defined(OS_CFG_SSSP_SIGNALDELAY) */ |
|
| 158 |
|
|
| 159 |
/** |
|
| 160 |
* @brief Time boundary for robot wide clock synchronization in microseconds. |
|
| 161 |
* @details Whenever the SSSP S (snychronization) signal gets logically deactivated, |
|
| 162 |
* All modules need to align their local uptime to the nearest multiple of this value. |
|
| 163 |
*/ |
|
| 164 |
#if !defined(OS_CFG_SSSP_SYSSYNCPERIOD) |
|
| 165 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD 1000000 |
|
| 166 |
#else /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */ |
|
| 167 |
#define AMIROOS_CFG_SSSP_SYSSYNCPERIOD OS_CFG_SSSP_SYSSYNCPERIOD |
|
| 168 |
#endif /* !defined(OS_CFG_SSSP_SYSSYNCPERIOD) */ |
|
| 169 |
|
|
| 170 |
/** @} */ |
|
| 171 |
|
|
| 172 |
/*===========================================================================*/ |
|
| 173 |
/** |
|
| 174 |
* @name System shell options |
|
| 175 |
* @{
|
|
| 176 |
*/ |
|
| 177 |
/*===========================================================================*/ |
|
| 178 |
|
|
| 179 |
/** |
|
| 180 |
* @brief Shell enable flag. |
|
| 181 |
*/ |
|
| 182 |
#if !defined(OS_CFG_SHELL_ENABLE) |
|
| 183 |
#define AMIROOS_CFG_SHELL_ENABLE true |
|
| 184 |
#else /* !defined(OS_CFG_SHELL_ENABLE) */ |
|
| 185 |
#define AMIROOS_CFG_SHELL_ENABLE OS_CFG_SHELL_ENABLE |
|
| 186 |
#endif /* !defined(OS_CFG_SHELL_ENABLE) */ |
|
| 187 |
|
|
| 188 |
/** |
|
| 189 |
* @brief Shell thread stack size. |
|
| 190 |
*/ |
|
| 191 |
#if !defined(OS_CFG_SHELL_STACKSIZE) |
|
| 192 |
#define AMIROOS_CFG_SHELL_STACKSIZE 1024 |
|
| 193 |
#else /* !defined(OS_CFG_SHELL_STACKSIZE) */ |
|
| 194 |
#define AMIROOS_CFG_SHELL_STACKSIZE OS_CFG_SHELL_STACKSIZE |
|
| 195 |
#endif /* !defined(OS_CFG_SHELL_STACKSIZE) */ |
|
| 196 |
|
|
| 197 |
/** |
|
| 198 |
* @brief Shell thread priority. |
|
| 199 |
* @details Thread priorities are specified as an integer value. |
|
| 200 |
* Predefined ranges are: |
|
| 201 |
* lowest ┌ THD_LOWPRIO_MIN |
|
| 202 |
* │ ... |
|
| 203 |
* └ THD_LOWPRIO_MAX |
|
| 204 |
* ┌ THD_NORMALPRIO_MIN |
|
| 205 |
* │ ... |
|
| 206 |
* └ THD_NORMALPRIO_MAX |
|
| 207 |
* ┌ THD_HIGHPRIO_MIN |
|
| 208 |
* │ ... |
|
| 209 |
* └ THD_HIGHPRIO_MAX |
|
| 210 |
* ┌ THD_RTPRIO_MIN |
|
| 211 |
* │ ... |
|
| 212 |
* highest └ THD_RTPRIO_MAX |
|
| 213 |
*/ |
|
| 214 |
#if !defined(OS_CFG_SHELL_THREADPRIO) |
|
| 215 |
#define AMIROOS_CFG_SHELL_THREADPRIO AOS_THD_NORMALPRIO_MIN |
|
| 216 |
#else /* !defined(OS_CFG_SHELL_THREADPRIO) */ |
|
| 217 |
#define AMIROOS_CFG_SHELL_THREADPRIO OS_CFG_SHELL_THREADPRIO |
|
| 218 |
#endif /* !defined(OS_CFG_SHELL_THREADPRIO) */ |
|
| 219 |
|
|
| 220 |
/** |
|
| 221 |
* @brief Shell maximum input line length. |
|
| 222 |
*/ |
|
| 223 |
#if !defined(OS_CFG_SHELL_LINEWIDTH) |
|
| 224 |
#define AMIROOS_CFG_SHELL_LINEWIDTH 128 |
|
| 225 |
#else /* !defined(OS_CFG_SHELL_LINEWIDTH) */ |
|
| 226 |
#define AMIROOS_CFG_SHELL_LINEWIDTH OS_CFG_SHELL_LINEWIDTH |
|
| 227 |
#endif /* !defined(OS_CFG_SHELL_LINEWIDTH) */ |
|
| 228 |
|
|
| 229 |
/** |
|
| 230 |
* @brief Shell maximum number of arguments. |
|
| 231 |
*/ |
|
| 232 |
#if !defined(OS_CFG_SHELL_MAXARGS) |
|
| 233 |
#define AMIROOS_CFG_SHELL_MAXARGS 16 |
|
| 234 |
#else /* !defined(OS_CFG_SHELL_MAXARGS) */ |
|
| 235 |
#define AMIROOS_CFG_SHELL_MAXARGS OS_CFG_SHELL_MAXARGS |
|
| 236 |
#endif /* !defined(OS_CFG_SHELL_MAXARGS) */ |
|
| 237 |
|
|
| 238 |
/** @} */ |
|
| 239 |
|
|
| 240 |
#endif /* AOSCONF_H */ |
|
| 241 |
|
|
| 242 |
/** @} */ |
|
| modules/DiWheelDrive_1-2/board.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief DiWheeDrive v1.1 Board specific initializations. |
|
| 22 |
* |
|
| 23 |
* @addtogroup diwheeldrive_board |
|
| 24 |
* @{
|
|
| 25 |
*/ |
|
| 26 |
|
|
| 27 |
#include <hal.h> |
|
| 28 |
|
|
| 29 |
#if HAL_USE_PAL || defined(__DOXYGEN__) |
|
| 30 |
/** |
|
| 31 |
* @brief PAL setup. |
|
| 32 |
* @details Digital I/O ports static configuration as defined in @p board.h. |
|
| 33 |
* This variable is used by the HAL when initializing the PAL driver. |
|
| 34 |
*/ |
|
| 35 |
const PALConfig pal_default_config = {
|
|
| 36 |
#if STM32_HAS_GPIOA |
|
| 37 |
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
|
|
| 38 |
#endif |
|
| 39 |
#if STM32_HAS_GPIOB |
|
| 40 |
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
|
|
| 41 |
#endif |
|
| 42 |
#if STM32_HAS_GPIOC |
|
| 43 |
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
|
|
| 44 |
#endif |
|
| 45 |
#if STM32_HAS_GPIOD |
|
| 46 |
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
|
|
| 47 |
#endif |
|
| 48 |
#if STM32_HAS_GPIOE |
|
| 49 |
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
|
|
| 50 |
#endif |
|
| 51 |
#if STM32_HAS_GPIOF |
|
| 52 |
{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
|
|
| 53 |
#endif |
|
| 54 |
#if STM32_HAS_GPIOG |
|
| 55 |
{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
|
|
| 56 |
#endif |
|
| 57 |
}; |
|
| 58 |
#endif |
|
| 59 |
|
|
| 60 |
/** |
|
| 61 |
* @brief Early initialization code. |
|
| 62 |
* @details This initialization must be performed just after stack setup |
|
| 63 |
* and before any other initialization. |
|
| 64 |
*/ |
|
| 65 |
void __early_init(void) {
|
|
| 66 |
|
|
| 67 |
stm32_clock_init(); |
|
| 68 |
} |
|
| 69 |
|
|
| 70 |
/** |
|
| 71 |
* @brief Board-specific initialization code. |
|
| 72 |
* @todo Add your board-specific code, if any. |
|
| 73 |
*/ |
|
| 74 |
void boardInit(void) {
|
|
| 75 |
/* |
|
| 76 |
* Several I/O pins are re-mapped: |
|
| 77 |
* JTAG disabled and SWJ enabled |
|
| 78 |
* TIM2 to the PA15/PB3/PA2/PA3 pins. |
|
| 79 |
* TIM3 to PC6/PC7 pins. |
|
| 80 |
* USART3 to the PC10/PC11 pins. |
|
| 81 |
* I2C1 to the PB8/PB9 pins. |
|
| 82 |
*/ |
|
| 83 |
AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE | |
|
| 84 |
AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | |
|
| 85 |
AFIO_MAPR_TIM3_REMAP_FULLREMAP | |
|
| 86 |
AFIO_MAPR_USART3_REMAP_PARTIALREMAP | |
|
| 87 |
AFIO_MAPR_I2C1_REMAP; |
|
| 88 |
} |
|
| 89 |
|
|
| 90 |
/** @} */ |
|
| modules/DiWheelDrive_1-2/board.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
|
|
| 5 |
This program is free software: you can redistribute it and/or modify |
|
| 6 |
it under the terms of the GNU General Public License as published by |
|
| 7 |
the Free Software Foundation, either version 3 of the License, or |
|
| 8 |
(at your option) any later version. |
|
| 9 |
|
|
| 10 |
This program is distributed in the hope that it will be useful, |
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 13 |
GNU General Public License for more details. |
|
| 14 |
|
|
| 15 |
You should have received a copy of the GNU General Public License |
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
| 17 |
*/ |
|
| 18 |
|
|
| 19 |
/** |
|
| 20 |
* @file |
|
| 21 |
* @brief DiWheeDrive v1.2 Board specific macros. |
|
| 22 |
* |
|
| 23 |
* @addtogroup diwheeldrive_board |
|
| 24 |
* @{
|
|
| 25 |
*/ |
|
| 26 |
|
|
| 27 |
#ifndef BOARD_H |
|
| 28 |
#define BOARD_H |
|
| 29 |
|
|
| 30 |
/* |
|
| 31 |
* Setup for AMiRo DiWheelDrive v1.2 board. |
|
| 32 |
*/ |
|
| 33 |
|
|
| 34 |
/* |
|
| 35 |
* Board identifier. |
|
| 36 |
*/ |
|
| 37 |
#define BOARD_DIWHEELDRIVE_1_2 |
|
| 38 |
#define BOARD_NAME "AMiRo DiWheelDrive v1.2" |
|
| 39 |
|
|
| 40 |
/* |
|
| 41 |
* Board oscillators-related settings. |
|
| 42 |
* NOTE: LSE not fitted. |
|
| 43 |
*/ |
|
| 44 |
#if !defined(STM32_LSECLK) |
|
| 45 |
#define STM32_LSECLK 0U |
|
| 46 |
#endif |
|
| 47 |
|
|
| 48 |
#if !defined(STM32_HSECLK) |
|
| 49 |
#define STM32_HSECLK 8000000U |
|
| 50 |
#endif |
|
| 51 |
|
|
| 52 |
/* |
|
| 53 |
* Board voltages. |
|
| 54 |
* Required for performance limits calculation. |
|
| 55 |
*/ |
|
| 56 |
#define STM32_VDD 330U |
|
| 57 |
|
|
| 58 |
/* |
|
| 59 |
* MCU type as defined in the ST header. |
|
| 60 |
*/ |
|
| 61 |
#define STM32F103xE |
|
| 62 |
|
|
| 63 |
/* |
|
| 64 |
* IO pins assignments. |
|
| 65 |
*/ |
|
| 66 |
#define GPIOA_WKUP 0U |
|
| 67 |
#define GPIOA_LED 1U |
|
| 68 |
#define GPIOA_DRIVE_PWM1A 2U |
|
| 69 |
#define GPIOA_DRIVE_PWM1B 3U |
|
| 70 |
#define GPIOA_PIN4 4U |
|
| 71 |
#define GPIOA_PIN5 5U |
|
| 72 |
#define GPIOA_PIN6 6U |
|
| 73 |
#define GPIOA_PIN7 7U |
|
| 74 |
#define GPIOA_PIN8 8U |
|
| 75 |
#define GPIOA_PROG_RX 9U |
|
| 76 |
#define GPIOA_PROG_TX 10U |
|
| 77 |
#define GPIOA_CAN_RX 11U |
|
| 78 |
#define GPIOA_CAN_TX 12U |
|
| 79 |
#define GPIOA_SWDIO 13U |
|
| 80 |
#define GPIOA_SWCLK 14U |
|
| 81 |
#define GPIOA_DRIVE_PWM2B 15U |
|
| 82 |
|
|
| 83 |
#define GPIOB_PIN0 0U |
|
| 84 |
#define GPIOB_DRIVE_SENSE2 1U |
|
| 85 |
#define GPIOB_POWER_EN 2U |
|
| 86 |
#define GPIOB_DRIVE_PWM2A 3U |
|
| 87 |
#define GPIOB_PIN4 4U |
|
| 88 |
#define GPIOB_PIN5 5U |
|
| 89 |
#define GPIOB_DRIVE_ENC1A 6U |
|
| 90 |
#define GPIOB_DRIVE_ENC1B 7U |
|
| 91 |
#define GPIOB_IMU_SCL 8U |
|
| 92 |
#define GPIOB_IMU_SDA 9U |
|
| 93 |
#define GPIOB_IR_SCL 10U |
|
| 94 |
#define GPIOB_IR_SDA 11U |
|
| 95 |
#define GPIOB_IR_INT 12U |
|
| 96 |
#define GPIOB_PIN13 13U |
|
| 97 |
#define GPIOB_SYS_UART_UP 14U |
|
| 98 |
#define GPIOB_IMU_INT 15U |
|
| 99 |
|
|
| 100 |
#define GPIOC_DRIVE_SENSE1 0U |
|
| 101 |
#define GPIOC_SYS_INT_N 1U |
|
| 102 |
#define GPIOC_IMU_RESET_N 2U |
|
| 103 |
#define GPIOC_PATH_DCSTAT 3U |
|
| 104 |
#define GPIOC_PIN4 4U |
|
| 105 |
#define GPIOC_PATH_DCEN 5U |
|
| 106 |
#define GPIOC_DRIVE_ENC2B 6U |
|
| 107 |
#define GPIOC_DRIVE_ENC2A 7U |
|
| 108 |
#define GPIOC_SYS_PD_N 8U |
|
| 109 |
#define GPIOC_SYS_REG_EN 9U |
|
| 110 |
#define GPIOC_SYS_UART_RX 10U |
|
| 111 |
#define GPIOC_SYS_UART_TX 11U |
|
| 112 |
#define GPIOC_IMU_BOOT_LOAD_N 12U |
|
| 113 |
#define GPIOC_PIN13 13U |
|
| 114 |
#define GPIOC_PIN14 14U |
|
| 115 |
#define GPIOC_IMU_BL_IND 15U |
|
| 116 |
|
|
| 117 |
#define GPIOD_OSC_IN 0U |
|
| 118 |
#define GPIOD_OSC_OUT 1U |
|
| 119 |
#define GPIOD_SYS_WARMRST_N 2U |
|
| 120 |
#define GPIOD_PIN3 3U |
|
| 121 |
#define GPIOD_PIN4 4U |
|
| 122 |
#define GPIOD_PIN5 5U |
|
| 123 |
#define GPIOD_PIN6 6U |
|
| 124 |
#define GPIOD_PIN7 7U |
|
| 125 |
#define GPIOD_PIN8 8U |
|
| 126 |
#define GPIOD_PIN9 9U |
|
| 127 |
#define GPIOD_PIN10 10U |
|
| 128 |
#define GPIOD_PIN11 11U |
|
| 129 |
#define GPIOD_PIN12 12U |
|
| 130 |
#define GPIOD_PIN13 13U |
|
| 131 |
#define GPIOD_PIN14 14U |
|
| 132 |
#define GPIOD_PIN15 15U |
|
| 133 |
|
|
| 134 |
#define GPIOE_PIN0 0U |
|
| 135 |
#define GPIOE_PIN1 1U |
|
| 136 |
#define GPIOE_PIN2 2U |
|
| 137 |
#define GPIOE_PIN3 3U |
|
| 138 |
#define GPIOE_PIN4 4U |
|
| 139 |
#define GPIOE_PIN5 5U |
|
| 140 |
#define GPIOE_PIN6 6U |
|
| 141 |
#define GPIOE_PIN7 7U |
|
| 142 |
#define GPIOE_PIN8 8U |
|
| 143 |
#define GPIOE_PIN9 9U |
|
| 144 |
#define GPIOE_PIN10 10U |
|
| 145 |
#define GPIOE_PIN11 11U |
|
| 146 |
#define GPIOE_PIN12 12U |
|
| 147 |
#define GPIOE_PIN13 13U |
|
| 148 |
#define GPIOE_PIN14 14U |
|
| 149 |
#define GPIOE_PIN15 15U |
|
| 150 |
|
|
| 151 |
#define GPIOF_PIN0 0U |
|
| 152 |
#define GPIOF_PIN1 1U |
|
| 153 |
#define GPIOF_PIN2 2U |
|
| 154 |
#define GPIOF_PIN3 3U |
|
| 155 |
#define GPIOF_PIN4 4U |
|
| 156 |
#define GPIOF_PIN5 5U |
|
| 157 |
#define GPIOF_PIN6 6U |
|
| 158 |
#define GPIOF_PIN7 7U |
|
| 159 |
#define GPIOF_PIN8 8U |
|
| 160 |
#define GPIOF_PIN9 9U |
|
| 161 |
#define GPIOF_PIN10 10U |
|
| 162 |
#define GPIOF_PIN11 11U |
|
| 163 |
#define GPIOF_PIN12 12U |
|
| 164 |
#define GPIOF_PIN13 13U |
|
| 165 |
#define GPIOF_PIN14 14U |
|
| 166 |
#define GPIOF_PIN15 15U |
|
| 167 |
|
|
| 168 |
#define GPIOG_PIN0 0U |
|
| 169 |
#define GPIOG_PIN1 1U |
|
| 170 |
#define GPIOG_PIN2 2U |
|
| 171 |
#define GPIOG_PIN3 3U |
|
| 172 |
#define GPIOG_PIN4 4U |
|
| 173 |
#define GPIOG_PIN5 5U |
|
| 174 |
#define GPIOG_PIN6 6U |
|
| 175 |
#define GPIOG_PIN7 7U |
|
| 176 |
#define GPIOG_PIN8 8U |
|
| 177 |
#define GPIOG_PIN9 9U |
|
| 178 |
#define GPIOG_PIN10 10U |
|
| 179 |
#define GPIOG_PIN11 11U |
|
| 180 |
#define GPIOG_PIN12 12U |
|
| 181 |
#define GPIOG_PIN13 13U |
|
| 182 |
#define GPIOG_PIN14 14U |
|
| 183 |
#define GPIOG_PIN15 15U |
|
| 184 |
|
|
| 185 |
/* |
|
| 186 |
* IO lines assignments. |
|
| 187 |
*/ |
|
| 188 |
#define LINE_WKUP PAL_LINE(GPIOA, GPIOA_WKUP) |
|
| 189 |
#define LINE_LED PAL_LINE(GPIOA, GPIOA_LED) |
|
| 190 |
#define LINE_DRIVE_PWM1A PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A) |
|
| 191 |
#define LINE_DRIVE_PWM1B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B) |
|
| 192 |
#define LINE_PROG_RX PAL_LINE(GPIOA, GPIOA_PROG_RX) |
|
| 193 |
#define LINE_PROG_TX PAL_LINE(GPIOA, GPIOA_PROG_TX) |
|
| 194 |
#define LINE_CAN_RX PAL_LINE(GPIOA, GPIOA_CAN_RX) |
|
| 195 |
#define LINE_CAN_TX PAL_LINE(GPIOA, GPIOA_CAN_TX) |
|
| 196 |
#define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO) |
|
| 197 |
#define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK) |
|
| 198 |
#define LINE_DRIVE_PWM2B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B) |
|
| 199 |
|
|
| 200 |
#define LINE_DRIVE_SENSE2 PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2) |
|
| 201 |
#define LINE_POWER_EN PAL_LINE(GPIOB, GPIOB_POWER_EN) |
|
| 202 |
#define LINE_DRIVE_PWM2A PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A) |
|
| 203 |
#define LINE_DRIVE_ENC1A PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A) |
|
| 204 |
#define LINE_DRIVE_ENC1B PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B) |
|
| 205 |
#define LINE_IMU_SCL PAL_LINE(GPIOB, GPIOB_IMU_SCL) |
|
| 206 |
#define LINE_IMU_SDA PAL_LINE(GPIOB, GPIOB_IMU_SDA) |
|
| 207 |
#define LINE_IR_SCL PAL_LINE(GPIOB, GPIOB_IR_SCL) |
|
| 208 |
#define LINE_IR_SDA PAL_LINE(GPIOB, GPIOB_IR_SDA) |
|
| 209 |
#define LINE_IR_INT PAL_LINE(GPIOB, GPIOB_IR_INT) |
|
| 210 |
#define LINE_SYS_UART_UP PAL_LINE(GPIOB, GPIOB_SYS_UART_UP) |
|
| 211 |
#define LINE_IMU_INT PAL_LINE(GPIOB, GPIOB_IMU_INT) |
|
| 212 |
|
|
| 213 |
#define LINE_DRIVE_SENSE1 PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1) |
|
| 214 |
#define LINE_SYS_INT_N PAL_LINE(GPIOC, GPIOC_SYS_INT_N) |
|
| 215 |
#define LINE_IMU_RESET_N PAL_LINE(GPIOC, GPIOC_IMU_RESET_N) |
|
| 216 |
#define LINE_PATH_DCSTAT PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT) |
|
| 217 |
#define LINE_PATH_DCEN PAL_LINE(GPIOC, GPIOC_PATH_DCEN) |
|
| 218 |
#define LINE_DRIVE_ENC2B PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B) |
|
| 219 |
#define LINE_DRIVE_ENC2A PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A) |
|
| 220 |
#define LINE_SYS_PD_N PAL_LINE(GPIOC, GPIOC_SYS_PD_N) |
|
| 221 |
#define LINE_SYS_REG_EN PAL_LINE(GPIOC, GPIOC_SYS_REG_EN) |
|
| 222 |
#define LINE_SYS_UART_RX PAL_LINE(GPIOC, GPIOC_SYS_UART_RX) |
|
| 223 |
#define LINE_SYS_UART_TX PAL_LINE(GPIOC, GPIOC_SYS_UART_TX) |
|
| 224 |
#define LINE_IMU_BOOT_LOAD_N PAL_LINE(GPIOC, GPIOC_IMU_BOOT_LOAD_N) |
|
| 225 |
#define LINE_IMU_BL_IND PAL_LINE(GPIOC, GPIOC_IMU_BL_IND) |
|
| 226 |
|
|
| 227 |
#define LINE_OSC_IN PAL_LINE(GPIOD, GPIOD_OSC_IN) |
|
| 228 |
#define LINE_OSC_OUT PAL_LINE(GPIOD, GPIOD_OSC_OUT) |
|
| 229 |
#define LINE_SYS_WARMRST_N PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N) |
|
| 230 |
|
|
| 231 |
/* |
|
| 232 |
* I/O ports initial setup, this configuration is established soon after reset |
|
| 233 |
* in the initialization code. |
|
| 234 |
* Please refer to the STM32 Reference Manual for details. |
|
| 235 |
*/ |
|
| 236 |
#define PIN_MODE_INPUT 0U |
|
| 237 |
#define PIN_MODE_OUTPUT_2M 2U |
|
| 238 |
#define PIN_MODE_OUTPUT_10M 1U |
|
| 239 |
#define PIN_MODE_OUTPUT_50M 3U |
|
| 240 |
#define PIN_CNF_INPUT_ANALOG 0U |
|
| 241 |
#define PIN_CNF_INPUT_FLOATING 1U |
|
| 242 |
#define PIN_CNF_INPUT_PULLX 2U |
|
| 243 |
#define PIN_CNF_OUTPUT_PUSHPULL 0U |
|
| 244 |
#define PIN_CNF_OUTPUT_OPENDRAIN 1U |
|
| 245 |
#define PIN_CNF_ALTERNATE_PUSHPULL 2U |
|
| 246 |
#define PIN_CNF_ALTERNATE_OPENDRAIN 3U |
|
| 247 |
#define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
|
| 248 |
#define PIN_ODR_LOW(n) (0U << (n)) |
|
| 249 |
#define PIN_ODR_HIGH(n) (1U << (n)) |
|
| 250 |
#define PIN_IGNORE(n) (1U << (n)) |
|
| 251 |
|
|
| 252 |
/* |
|
| 253 |
* GPIOA setup: |
|
| 254 |
* |
|
| 255 |
* PA0 - WKUP (input floating) |
|
| 256 |
* PA1 - LED (output opendrain high 50MHz) |
|
| 257 |
* PA2 - DRIVE_PWM1A (alternate pushpull 50MHz) |
|
| 258 |
* PA3 - DRIVE_PWM1B (alternate pushpull 50MHz) |
|
| 259 |
* PA4 - PIN4 (input floating) |
|
| 260 |
* PA5 - PIN5 (input floating) |
|
| 261 |
* PA6 - PIN6 (input floating) |
|
| 262 |
* PA7 - PIN7 (input floating) |
|
| 263 |
* PA8 - PIN8 (input floating) |
|
| 264 |
* PA9 - PROG_RX (alternate pushpull 50MHz) |
|
| 265 |
* PA10 - PROG_TX (input pullup) |
|
| 266 |
* PA11 - CAN_RX (input pullup) |
|
| 267 |
* PA12 - CAN_TX (alternate pushpull 50MHz) |
|
| 268 |
* PA13 - SWDIO (input pullup) |
|
| 269 |
* PA14 - SWCLK (input pullup) |
|
| 270 |
* PA15 - DRIVE_PWM2B (alternate pushpull 50MHz) |
|
| 271 |
*/ |
|
| 272 |
#define VAL_GPIOAIGN (PIN_IGNORE(GPIOA_LED)) & 0 |
|
| 273 |
#define VAL_GPIOACRL (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 274 |
PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 275 |
PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
|
| 276 |
PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
|
| 277 |
PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 278 |
PIN_CR(GPIOA_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 279 |
PIN_CR(GPIOA_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 280 |
PIN_CR(GPIOA_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 281 |
#define VAL_GPIOACRH (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 282 |
PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
|
| 283 |
PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
|
| 284 |
PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
|
| 285 |
PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
|
| 286 |
PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
|
| 287 |
PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
|
| 288 |
PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
|
| 289 |
#define VAL_GPIOAODR (PIN_ODR_HIGH(GPIOA_WKUP) | \ |
|
| 290 |
PIN_ODR_HIGH(GPIOA_LED) | \ |
|
| 291 |
PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) | \ |
|
| 292 |
PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) | \ |
|
| 293 |
PIN_ODR_LOW(GPIOA_PIN4) | \ |
|
| 294 |
PIN_ODR_LOW(GPIOA_PIN5) | \ |
|
| 295 |
PIN_ODR_LOW(GPIOA_PIN6) | \ |
|
| 296 |
PIN_ODR_LOW(GPIOA_PIN7) | \ |
|
| 297 |
PIN_ODR_LOW(GPIOA_PIN8) | \ |
|
| 298 |
PIN_ODR_HIGH(GPIOA_PROG_RX) | \ |
|
| 299 |
PIN_ODR_HIGH(GPIOA_PROG_TX) | \ |
|
| 300 |
PIN_ODR_HIGH(GPIOA_CAN_RX) | \ |
|
| 301 |
PIN_ODR_HIGH(GPIOA_CAN_TX) | \ |
|
| 302 |
PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
|
| 303 |
PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
|
| 304 |
PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B)) |
|
| 305 |
|
|
| 306 |
/* |
|
| 307 |
* GPIOB setup: |
|
| 308 |
* |
|
| 309 |
* PB0 - PIN0 (input floating) |
|
| 310 |
* PB1 - DRIVE_SENSE2 (input analog) |
|
| 311 |
* PB2 - POWER_EN (output pushpull low 50MHz) |
|
| 312 |
* PB3 - DRIVE_PWM2A (alternate pushpull 50MHz) |
|
| 313 |
* PB4 - PIN4 (input floating) |
|
| 314 |
* PB5 - PIN5 (input floating) |
|
| 315 |
* PB6 - DRIVE_ENC1A (input floating) |
|
| 316 |
* PB7 - DRIVE_ENC1B (input floating) |
|
| 317 |
* PB8 - IMU_SCL (alternate opendrain 50MHz) |
|
| 318 |
* PB9 - IMU_SDA (alternate opendrain 50MHz) |
|
| 319 |
* PB10 - IR_SCL (alternate opendrain 50MHz) |
|
| 320 |
* PB11 - IR_SDA (alternate opendrain 50MHz) |
|
| 321 |
* PB12 - IR_INT (input floating) |
|
| 322 |
* PB13 - PIN13 (input floating) |
|
| 323 |
* PB14 - SYS_UART_UP (output opendrain high 50MHz) |
|
| 324 |
* PB15 - IMU_INT (input floating) |
|
| 325 |
*/ |
|
| 326 |
#define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
|
| 327 |
#define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 328 |
PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
|
| 329 |
PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
|
| 330 |
PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
|
| 331 |
PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 332 |
PIN_CR(GPIOB_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 333 |
PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 334 |
PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 335 |
#define VAL_GPIOBCRH (PIN_CR(GPIOB_IMU_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
|
| 336 |
PIN_CR(GPIOB_IMU_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
|
| 337 |
PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
|
| 338 |
PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
|
| 339 |
PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 340 |
PIN_CR(GPIOB_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 341 |
PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 342 |
PIN_CR(GPIOB_IMU_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 343 |
#define VAL_GPIOBODR (PIN_ODR_LOW(GPIOB_PIN0) | \ |
|
| 344 |
PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) | \ |
|
| 345 |
PIN_ODR_LOW(GPIOB_POWER_EN) | \ |
|
| 346 |
PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) | \ |
|
| 347 |
PIN_ODR_LOW(GPIOB_PIN4) | \ |
|
| 348 |
PIN_ODR_LOW(GPIOB_PIN5) | \ |
|
| 349 |
PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) | \ |
|
| 350 |
PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) | \ |
|
| 351 |
PIN_ODR_HIGH(GPIOB_IMU_SCL) | \ |
|
| 352 |
PIN_ODR_HIGH(GPIOB_IMU_SDA) | \ |
|
| 353 |
PIN_ODR_HIGH(GPIOB_IR_SCL) | \ |
|
| 354 |
PIN_ODR_HIGH(GPIOB_IR_SDA) | \ |
|
| 355 |
PIN_ODR_HIGH(GPIOB_IR_INT) | \ |
|
| 356 |
PIN_ODR_LOW(GPIOB_PIN13) | \ |
|
| 357 |
PIN_ODR_HIGH(GPIOB_SYS_UART_UP) | \ |
|
| 358 |
PIN_ODR_LOW(GPIOB_IMU_INT)) |
|
| 359 |
|
|
| 360 |
/* |
|
| 361 |
* GPIOC setup: |
|
| 362 |
* |
|
| 363 |
* PC0 - DRIVE_SENSE1 (input analog) |
|
| 364 |
* PC1 - SYS_INT_N (output opendrain low 50MHz) |
|
| 365 |
* PC2 - IMU_RESET_N (output opendrain high 50MHz) |
|
| 366 |
* PC3 - PATH_DCSTAT (input floating) |
|
| 367 |
* PC4 - PIN4 (input floating) |
|
| 368 |
* PC5 - PATH_DCEN (output pushpull low 50MHz) |
|
| 369 |
* PC6 - DRIVE_ENC2B (input floating) |
|
| 370 |
* PC7 - DRIVE_ENC2A (input floating) |
|
| 371 |
* PC8 - SYS_PD_N (output opendrain high 50MHz) |
|
| 372 |
* PC9 - SYS_REG_EN (input floating) |
|
| 373 |
* PC10 - SYS_UART_RX (input floating) |
|
| 374 |
* PC11 - SYS_UART_TX (input floating) |
|
| 375 |
* PC12 - IMU_BOOT_LOAD_N (output opendrain high 50MHz) |
|
| 376 |
* PC13 - PIN13 (input floating) |
|
| 377 |
* PC14 - PIN14 (input floating) |
|
| 378 |
* PC15 - IMU_BL_IND (input floating) |
|
| 379 |
*/ |
|
| 380 |
#define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_INT_N) | \ |
|
| 381 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0 |
|
| 382 |
#define VAL_GPIOCCRL (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
|
| 383 |
PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 384 |
PIN_CR(GPIOC_IMU_RESET_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 385 |
PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 386 |
PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 387 |
PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
|
| 388 |
PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 389 |
PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 390 |
#define VAL_GPIOCCRH (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 391 |
PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 392 |
PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 393 |
PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 394 |
PIN_CR(GPIOC_IMU_BOOT_LOAD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 395 |
PIN_CR(GPIOC_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 396 |
PIN_CR(GPIOC_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 397 |
PIN_CR(GPIOC_IMU_BL_IND, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 398 |
#define VAL_GPIOCODR (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) | \ |
|
| 399 |
PIN_ODR_LOW(GPIOC_SYS_INT_N) | \ |
|
| 400 |
PIN_ODR_HIGH(GPIOC_IMU_RESET_N) | \ |
|
| 401 |
PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) | \ |
|
| 402 |
PIN_ODR_LOW(GPIOC_PIN4) | \ |
|
| 403 |
PIN_ODR_LOW(GPIOC_PATH_DCEN) | \ |
|
| 404 |
PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) | \ |
|
| 405 |
PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) | \ |
|
| 406 |
PIN_ODR_HIGH(GPIOC_SYS_PD_N) | \ |
|
| 407 |
PIN_ODR_HIGH(GPIOC_SYS_REG_EN) | \ |
|
| 408 |
PIN_ODR_HIGH(GPIOC_SYS_UART_RX) | \ |
|
| 409 |
PIN_ODR_HIGH(GPIOC_SYS_UART_TX) | \ |
|
| 410 |
PIN_ODR_HIGH(GPIOC_IMU_BOOT_LOAD_N) | \ |
|
| 411 |
PIN_ODR_LOW(GPIOC_PIN13) | \ |
|
| 412 |
PIN_ODR_LOW(GPIOC_PIN14) | \ |
|
| 413 |
PIN_ODR_LOW(GPIOC_IMU_BL_IND)) |
|
| 414 |
|
|
| 415 |
/* |
|
| 416 |
* GPIOD setup: |
|
| 417 |
* |
|
| 418 |
* PD0 - OSC_IN (input floating) |
|
| 419 |
* PD1 - OSC_OUT (input floating) |
|
| 420 |
* PD2 - SYS_WARMRST_N (output opendrain high 50MHz) |
|
| 421 |
* PD3 - PIN3 (input floating) |
|
| 422 |
* PD4 - PIN4 (input floating) |
|
| 423 |
* PD5 - PIN5 (input floating) |
|
| 424 |
* PD6 - PIN6 (input floating) |
|
| 425 |
* PD7 - PIN7 (input floating) |
|
| 426 |
* PD8 - PIN8 (input floating) |
|
| 427 |
* PD9 - PIN9 (input floating) |
|
| 428 |
* PD10 - PIN10 (input floating) |
|
| 429 |
* PD11 - PIN11 (input floating) |
|
| 430 |
* PD12 - PIN12 (input floating) |
|
| 431 |
* PD13 - PIN13 (input floating) |
|
| 432 |
* PD14 - PIN14 (input floating) |
|
| 433 |
* PD15 - PIN15 (input floating) |
|
| 434 |
*/ |
|
| 435 |
#define VAL_GPIODIGN 0 |
|
| 436 |
#define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 437 |
PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 438 |
PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
|
| 439 |
PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 440 |
PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 441 |
PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 442 |
PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 443 |
PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 444 |
#define VAL_GPIODCRH (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 445 |
PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 446 |
PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 447 |
PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 448 |
PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 449 |
PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 450 |
PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 451 |
PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 452 |
#define VAL_GPIODODR (PIN_ODR_HIGH(GPIOD_OSC_IN) | \ |
|
| 453 |
PIN_ODR_HIGH(GPIOD_OSC_OUT) | \ |
|
| 454 |
PIN_ODR_HIGH(GPIOD_SYS_WARMRST_N) | \ |
|
| 455 |
PIN_ODR_LOW(GPIOD_PIN3) | \ |
|
| 456 |
PIN_ODR_LOW(GPIOD_PIN4) | \ |
|
| 457 |
PIN_ODR_LOW(GPIOD_PIN5) | \ |
|
| 458 |
PIN_ODR_LOW(GPIOD_PIN6) | \ |
|
| 459 |
PIN_ODR_LOW(GPIOD_PIN7) | \ |
|
| 460 |
PIN_ODR_LOW(GPIOD_PIN8) | \ |
|
| 461 |
PIN_ODR_LOW(GPIOD_PIN9) | \ |
|
| 462 |
PIN_ODR_LOW(GPIOD_PIN10) | \ |
|
| 463 |
PIN_ODR_LOW(GPIOD_PIN11) | \ |
|
| 464 |
PIN_ODR_LOW(GPIOD_PIN12) | \ |
|
| 465 |
PIN_ODR_LOW(GPIOD_PIN13) | \ |
|
| 466 |
PIN_ODR_LOW(GPIOD_PIN14) | \ |
|
| 467 |
PIN_ODR_LOW(GPIOD_PIN15)) |
|
| 468 |
|
|
| 469 |
/* |
|
| 470 |
* GPIOE setup: |
|
| 471 |
* |
|
| 472 |
* PE0 - PIN0 (input floating) |
|
| 473 |
* PE1 - PIN1 (input floating) |
|
| 474 |
* PE2 - PIN2 (input floating) |
|
| 475 |
* PE3 - PIN3 (input floating) |
|
| 476 |
* PE4 - PIN4 (input floating) |
|
| 477 |
* PE5 - PIN5 (input floating) |
|
| 478 |
* PE6 - PIN6 (input floating) |
|
| 479 |
* PE7 - PIN7 (input floating) |
|
| 480 |
* PE8 - PIN8 (input floating) |
|
| 481 |
* PE9 - PIN9 (input floating) |
|
| 482 |
* PE10 - PIN10 (input floating) |
|
| 483 |
* PE11 - PIN11 (input floating) |
|
| 484 |
* PE12 - PIN12 (input floating) |
|
| 485 |
* PE13 - PIN13 (input floating) |
|
| 486 |
* PE14 - PIN14 (input floating) |
|
| 487 |
* PE15 - PIN15 (input floating) |
|
| 488 |
*/ |
|
| 489 |
#define VAL_GPIOEIGN 0 |
|
| 490 |
#define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 491 |
PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 492 |
PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 493 |
PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 494 |
PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 495 |
PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 496 |
PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 497 |
PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 498 |
#define VAL_GPIOECRH (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 499 |
PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 500 |
PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 501 |
PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 502 |
PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 503 |
PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 504 |
PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 505 |
PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 506 |
#define VAL_GPIOEODR (PIN_ODR_LOW(GPIOE_PIN0) | \ |
|
| 507 |
PIN_ODR_LOW(GPIOE_PIN1) | \ |
|
| 508 |
PIN_ODR_LOW(GPIOE_PIN2) | \ |
|
| 509 |
PIN_ODR_LOW(GPIOE_PIN3) | \ |
|
| 510 |
PIN_ODR_LOW(GPIOE_PIN4) | \ |
|
| 511 |
PIN_ODR_LOW(GPIOE_PIN5) | \ |
|
| 512 |
PIN_ODR_LOW(GPIOE_PIN6) | \ |
|
| 513 |
PIN_ODR_LOW(GPIOE_PIN7) | \ |
|
| 514 |
PIN_ODR_LOW(GPIOE_PIN8) | \ |
|
| 515 |
PIN_ODR_LOW(GPIOE_PIN9) | \ |
|
| 516 |
PIN_ODR_LOW(GPIOE_PIN10) | \ |
|
| 517 |
PIN_ODR_LOW(GPIOE_PIN11) | \ |
|
| 518 |
PIN_ODR_LOW(GPIOE_PIN12) | \ |
|
| 519 |
PIN_ODR_LOW(GPIOE_PIN13) | \ |
|
| 520 |
PIN_ODR_LOW(GPIOE_PIN14) | \ |
|
| 521 |
PIN_ODR_LOW(GPIOE_PIN15)) |
|
| 522 |
|
|
| 523 |
/* |
|
| 524 |
* GPIOF setup: |
|
| 525 |
* |
|
| 526 |
* PF0 - PIN0 (input floating) |
|
| 527 |
* PF1 - PIN1 (input floating) |
|
| 528 |
* PF2 - PIN2 (input floating) |
|
| 529 |
* PF3 - PIN3 (input floating) |
|
| 530 |
* PF4 - PIN4 (input floating) |
|
| 531 |
* PF5 - PIN5 (input floating) |
|
| 532 |
* PF6 - PIN6 (input floating) |
|
| 533 |
* PF7 - PIN7 (input floating) |
|
| 534 |
* PF8 - PIN8 (input floating) |
|
| 535 |
* PF9 - PIN9 (input floating) |
|
| 536 |
* PF10 - PIN10 (input floating) |
|
| 537 |
* PF11 - PIN11 (input floating) |
|
| 538 |
* PF12 - PIN12 (input floating) |
|
| 539 |
* PF13 - PIN13 (input floating) |
|
| 540 |
* PF14 - PIN14 (input floating) |
|
| 541 |
* PF15 - PIN15 (input floating) |
|
| 542 |
*/ |
|
| 543 |
#define VAL_GPIOFIGN 0 |
|
| 544 |
#define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 545 |
PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 546 |
PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 547 |
PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 548 |
PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 549 |
PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 550 |
PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 551 |
PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 552 |
#define VAL_GPIOFCRH (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 553 |
PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 554 |
PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 555 |
PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 556 |
PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 557 |
PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 558 |
PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 559 |
PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 560 |
#define VAL_GPIOFODR (PIN_ODR_LOW(GPIOF_PIN0) | \ |
|
| 561 |
PIN_ODR_LOW(GPIOF_PIN1) | \ |
|
| 562 |
PIN_ODR_LOW(GPIOF_PIN2) | \ |
|
| 563 |
PIN_ODR_LOW(GPIOF_PIN3) | \ |
|
| 564 |
PIN_ODR_LOW(GPIOF_PIN4) | \ |
|
| 565 |
PIN_ODR_LOW(GPIOF_PIN5) | \ |
|
| 566 |
PIN_ODR_LOW(GPIOF_PIN6) | \ |
|
| 567 |
PIN_ODR_LOW(GPIOF_PIN7) | \ |
|
| 568 |
PIN_ODR_LOW(GPIOF_PIN8) | \ |
|
| 569 |
PIN_ODR_LOW(GPIOF_PIN9) | \ |
|
| 570 |
PIN_ODR_LOW(GPIOF_PIN10) | \ |
|
| 571 |
PIN_ODR_LOW(GPIOF_PIN11) | \ |
|
| 572 |
PIN_ODR_LOW(GPIOF_PIN12) | \ |
|
| 573 |
PIN_ODR_LOW(GPIOF_PIN13) | \ |
|
| 574 |
PIN_ODR_LOW(GPIOF_PIN14) | \ |
|
| 575 |
PIN_ODR_LOW(GPIOF_PIN15)) |
|
| 576 |
|
|
| 577 |
/* |
|
| 578 |
* GPIOG setup: |
|
| 579 |
* |
|
| 580 |
* PG0 - PIN0 (input floating) |
|
| 581 |
* PG1 - PIN1 (input floating) |
|
| 582 |
* PG2 - PIN2 (input floating) |
|
| 583 |
* PG3 - PIN3 (input floating) |
|
| 584 |
* PG4 - PIN4 (input floating) |
|
| 585 |
* PG5 - PIN5 (input floating) |
|
| 586 |
* PG6 - PIN6 (input floating) |
|
| 587 |
* PG7 - PIN7 (input floating) |
|
| 588 |
* PG8 - PIN8 (input floating) |
|
| 589 |
* PG9 - PIN9 (input floating) |
|
| 590 |
* PG10 - PIN10 (input floating) |
|
| 591 |
* PG11 - PIN11 (input floating) |
|
| 592 |
* PG12 - PIN12 (input floating) |
|
| 593 |
* PG13 - PIN13 (input floating) |
|
| 594 |
* PG14 - PIN14 (input floating) |
|
| 595 |
* PG15 - PIN15 (input floating) |
|
| 596 |
*/ |
|
| 597 |
#define VAL_GPIOGIGN 0 |
|
| 598 |
#define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 599 |
PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 600 |
PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 601 |
PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 602 |
PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 603 |
PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 604 |
PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 605 |
PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 606 |
#define VAL_GPIOGCRH (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 607 |
PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 608 |
PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 609 |
PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 610 |
PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 611 |
PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 612 |
PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
|
| 613 |
PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
|
| 614 |
#define VAL_GPIOGODR (PIN_ODR_LOW(GPIOG_PIN0) | \ |
|
| 615 |
PIN_ODR_LOW(GPIOG_PIN1) | \ |
|
| 616 |
PIN_ODR_LOW(GPIOG_PIN2) | \ |
|
| 617 |
PIN_ODR_LOW(GPIOG_PIN3) | \ |
|
| 618 |
PIN_ODR_LOW(GPIOG_PIN4) | \ |
|
| 619 |
PIN_ODR_LOW(GPIOG_PIN5) | \ |
|
| 620 |
PIN_ODR_LOW(GPIOG_PIN6) | \ |
|
| 621 |
PIN_ODR_LOW(GPIOG_PIN7) | \ |
|
| 622 |
PIN_ODR_LOW(GPIOG_PIN8) | \ |
|
| 623 |
PIN_ODR_LOW(GPIOG_PIN9) | \ |
|
| 624 |
PIN_ODR_LOW(GPIOG_PIN10) | \ |
|
| 625 |
PIN_ODR_LOW(GPIOG_PIN11) | \ |
|
| 626 |
PIN_ODR_LOW(GPIOG_PIN12) | \ |
|
| 627 |
PIN_ODR_LOW(GPIOG_PIN13) | \ |
|
| 628 |
PIN_ODR_LOW(GPIOG_PIN14) | \ |
|
| 629 |
PIN_ODR_LOW(GPIOG_PIN15)) |
|
| 630 |
|
|
| 631 |
#if !defined(_FROM_ASM_) |
|
| 632 |
#ifdef __cplusplus |
|
| 633 |
extern "C" {
|
|
| 634 |
#endif |
|
| 635 |
void boardInit(void); |
|
| 636 |
#ifdef __cplusplus |
|
| 637 |
} |
|
| 638 |
#endif |
|
| 639 |
#endif /* _FROM_ASM_ */ |
|
| 640 |
|
|
| 641 |
#endif /* BOARD_H */ |
|
| 642 |
|
|
| 643 |
/** @} */ |
|
| modules/DiWheelDrive_1-2/chconf.h | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform. |
|
| 3 |
* Copyright (C) 2016..2019 Thomas Schöpping et al. |
|
| 4 |
* |
|
| 5 |
* This program is free software: you can redistribute it and/or modify |
|
| 6 |
* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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/** |
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* @file |
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* @brief ChibiOS Configuration file for the DiWheelDrive v1.2 module. |
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* @details Contains the application specific kernel settings. |
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* |
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* @addtogroup diwheeldrive_ch_config |
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* @details Kernel related settings and hooks. |
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