Revision b4885314 boards/DiWheelDrive/board.c
| boards/DiWheelDrive/board.c | ||
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palSetPad(GPIOC, GPIOC_SYS_PD_N); |
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} |
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inline void boardClearI2CBus(const uint8_t scl_pad) {
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inline void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad) {
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uint8_t i; |
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// configure I²C SCL open drain |
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// configure I²C SCL and SDA open drain
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palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN); |
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palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN); |
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// perform bus clear as per I²C Specification v5 3.1.16 |
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for (i = 0x00u; i < 0x09u; i++) {
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// perform a 2-wire software reset for the eeprom (see AT24C01BN-SH-B datasheet, chapter 3) |
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// note: clock is ~50kHz (20us per cycle) |
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palSetPad(GPIOB, sda_pad); |
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(10); |
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palSetPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(5); |
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palClearPad(GPIOB, sda_pad); |
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chThdSleepMicroseconds(5); |
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(5); |
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palSetPad(GPIOB, sda_pad); |
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chThdSleepMicroseconds(5); |
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for (i = 0; i < 9; ++i) {
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palSetPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(10); |
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(10); |
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} |
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palSetPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(5); |
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palClearPad(GPIOB, sda_pad); |
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chThdSleepMicroseconds(5); |
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(10); |
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palSetPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(5); |
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palSetPad(GPIOB, sda_pad); |
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chThdSleepMicroseconds(5); |
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(10); |
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// perform bus clear as per I²C Specification v6 3.1.16 |
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// note: clock is 100kHz (10us per cycle) |
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for (i = 0; i < 10; i++) {
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palClearPad(GPIOB, scl_pad); |
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chThdSleepMicroseconds(5); |
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palSetPad(GPIOB, scl_pad); |
| ... | ... | |
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// reconfigure I²C SCL |
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palSetPadMode(GPIOB, scl_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); |
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palSetPadMode(GPIOB, sda_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); |
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return; |
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} |
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