Revision b4885314 boards/PowerManagement/board.c

View differences:

boards/PowerManagement/board.c
146 146
  palSetPad(GPIOC, GPIOC_SYS_PD_N);
147 147
}
148 148

  
149
inline void boardClearI2CBus(const uint8_t scl_pad) {
149
inline void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad) {
150 150

  
151 151
  uint8_t i;
152 152

  
153
  // configure I²C SCL open drain
153
  // configure I²C SCL and SDA open drain
154 154
  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);
155
  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);
155 156

  
156
  // perform bus clear as per I²C Specification v5 3.1.16
157
  for (i = 0x00u; i < 0x09u; i++) {
157
  // perform a 2-wire software reset for the eeprom (see AT24C01BN-SH-B datasheet, chapter 3)
158
  // note: clock is ~50kHz (20us per cycle)
159
  palSetPad(GPIOB, sda_pad);
160
  palClearPad(GPIOB, scl_pad);
161
  chThdSleepMicroseconds(10);
162
  palSetPad(GPIOB, scl_pad);
163
  chThdSleepMicroseconds(5);
164
  palClearPad(GPIOB, sda_pad);
165
  chThdSleepMicroseconds(5);
166
  palClearPad(GPIOB, scl_pad);
167
  chThdSleepMicroseconds(5);
168
  palSetPad(GPIOB, sda_pad);
169
  chThdSleepMicroseconds(5);
170
  for (i = 0; i < 9; ++i) {
171
    palSetPad(GPIOB, scl_pad);
172
    chThdSleepMicroseconds(10);
173
    palClearPad(GPIOB, scl_pad);
174
    chThdSleepMicroseconds(10);
175
  }
176
  palSetPad(GPIOB, scl_pad);
177
  chThdSleepMicroseconds(5);
178
  palClearPad(GPIOB, sda_pad);
179
  chThdSleepMicroseconds(5);
180
  palClearPad(GPIOB, scl_pad);
181
  chThdSleepMicroseconds(10);
182
  palSetPad(GPIOB, scl_pad);
183
  chThdSleepMicroseconds(5);
184
  palSetPad(GPIOB, sda_pad);
185
  chThdSleepMicroseconds(5);
186
  palClearPad(GPIOB, scl_pad);
187
  chThdSleepMicroseconds(10);
188

  
189
  // perform bus clear as per I²C Specification v6 3.1.16
190
  // note: clock is 100kHz (10us per cycle)
191
  for (i = 0; i < 10; i++) {
158 192
    palClearPad(GPIOB, scl_pad);
159 193
    chThdSleepMicroseconds(5);
160 194
    palSetPad(GPIOB, scl_pad);
......
163 197

  
164 198
  // reconfigure I²C SCL
165 199
  palSetPadMode(GPIOB, scl_pad, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
200
  palSetPadMode(GPIOB, sda_pad, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
201

  
202
  return;
203
}
204

  
205
inline void boardResetBQ27500I2C(const uint8_t scl_pad, const uint8_t sda_pad) {
206

  
207
  // configure I²C SCL and SDA open drain
208
  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);
209
  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);
210

  
211
  // BQ27500: reset by holding bus low for t_BUSERR (17.3 - 21.2 seconds)
212
  palClearPad(GPIOB, scl_pad);
213
  palClearPad(GPIOB, sda_pad);
214
  chThdSleepSeconds(20);
215

  
216
  boardClearI2CBus(scl_pad, sda_pad);
166 217

  
218
  return;
167 219
}

Also available in: Unified diff