amiro-os / os / unittests / periphery-lld / src / ut_alld_l3g4200d.c @ be23de72
History | View | Annotate | Download (9.771 KB)
| 1 |
/*
|
|---|---|
| 2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
|
| 3 |
Copyright (C) 2016..2018 Thomas Schöpping et al.
|
| 4 |
|
| 5 |
This program is free software: you can redistribute it and/or modify
|
| 6 |
it under the terms of the GNU General Public License as published by
|
| 7 |
the Free Software Foundation, either version 3 of the License, or
|
| 8 |
(at your option) any later version.
|
| 9 |
|
| 10 |
This program is distributed in the hope that it will be useful,
|
| 11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 13 |
GNU General Public License for more details.
|
| 14 |
|
| 15 |
You should have received a copy of the GNU General Public License
|
| 16 |
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 17 |
*/
|
| 18 |
|
| 19 |
#include <ut_alld_l3g4200d.h> |
| 20 |
|
| 21 |
#if ((AMIROOS_CFG_TESTS_ENABLE == true) && defined(AMIROLLD_CFG_USE_L3G4200D)) || defined(__DOXYGEN__) |
| 22 |
|
| 23 |
#include <aos_debug.h> |
| 24 |
#include <chprintf.h> |
| 25 |
#include <aos_thread.h> |
| 26 |
#include <alld_l3g4200d.h> |
| 27 |
|
| 28 |
/**
|
| 29 |
* @brief L3G4200D unit test function.
|
| 30 |
*
|
| 31 |
* @param[in] stream Stream for input/output.
|
| 32 |
* @param[in] ut Unit test object.
|
| 33 |
*
|
| 34 |
* @return Unit test result value.
|
| 35 |
*/
|
| 36 |
aos_utresult_t utAlldL3g4200dFunc(BaseSequentialStream* stream, aos_unittest_t* ut) |
| 37 |
{
|
| 38 |
aosDbgCheck(ut->data != NULL && ((ut_l3g4200ddata_t*)(ut->data)) != NULL); |
| 39 |
|
| 40 |
// local variables
|
| 41 |
aos_utresult_t result = {0, 0};
|
| 42 |
uint32_t status; |
| 43 |
uint8_t data = 0;
|
| 44 |
uint8_t write_data[5];
|
| 45 |
uint8_t read_data[5];
|
| 46 |
int16_t sdata[3];
|
| 47 |
uint8_t status_reg; |
| 48 |
eventmask_t event_mask; |
| 49 |
bool success = false; |
| 50 |
uint8_t fifo = 0x5F;
|
| 51 |
event_listener_t el; |
| 52 |
|
| 53 |
for (uint8_t dataIdx = 0; dataIdx < 4; dataIdx++) { |
| 54 |
write_data[dataIdx] = (dataIdx+1)*11; |
| 55 |
} |
| 56 |
write_data[4] = 0; |
| 57 |
|
| 58 |
chprintf(stream, "check identity...\n");
|
| 59 |
status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_WHO_AM_I, &data, 1);
|
| 60 |
if(status == APAL_STATUS_SUCCESS && data == L3G4200D_LLD_WHO_AM_I){
|
| 61 |
aosUtPassed(stream, &result); |
| 62 |
} else {
|
| 63 |
aosUtFailedMsg(stream, &result, "0x%08X, data: %d\n", status, data);
|
| 64 |
} |
| 65 |
|
| 66 |
chprintf(stream, "write register...\n");
|
| 67 |
status = l3g4200d_lld_write_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, write_data, 1);
|
| 68 |
if (status == APAL_STATUS_SUCCESS) {
|
| 69 |
aosUtPassed(stream, &result); |
| 70 |
} else {
|
| 71 |
aosUtFailed(stream, &result); |
| 72 |
} |
| 73 |
|
| 74 |
chprintf(stream, "read register...\n");
|
| 75 |
status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, &data, 1);
|
| 76 |
if (status == APAL_STATUS_SUCCESS && data == write_data[0]) { |
| 77 |
aosUtPassed(stream, &result); |
| 78 |
} else {
|
| 79 |
aosUtFailedMsg(stream, &result, "0x%08X, data: %d\n", status, data);
|
| 80 |
} |
| 81 |
|
| 82 |
chprintf(stream, "write multiple registers...\n");
|
| 83 |
status = l3g4200d_lld_write_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, write_data, 5);
|
| 84 |
if (status == APAL_STATUS_SUCCESS) {
|
| 85 |
aosUtPassed(stream, &result); |
| 86 |
} else {
|
| 87 |
aosUtFailed(stream, &result); |
| 88 |
} |
| 89 |
|
| 90 |
chprintf(stream, "read multiple registers...\n");
|
| 91 |
status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, read_data, 5);
|
| 92 |
uint8_t errors = 0;
|
| 93 |
for (uint8_t dataIdx = 0; dataIdx < 5; dataIdx++) { |
| 94 |
if (read_data[dataIdx] != write_data[dataIdx]) {
|
| 95 |
++errors; |
| 96 |
} |
| 97 |
} |
| 98 |
if (status == APAL_STATUS_SUCCESS && errors == 0) { |
| 99 |
aosUtPassed(stream, &result); |
| 100 |
} else {
|
| 101 |
for (uint8_t dataIdx = 0; dataIdx < 5; dataIdx++) { |
| 102 |
chprintf(stream, "\t\tStatus: %d, CTRL_REG%d: %d, write_data: %d\n", status, dataIdx+1, read_data[dataIdx], write_data[dataIdx]); |
| 103 |
} |
| 104 |
aosUtFailedMsg(stream, &result, "0x%08X, errors: %d\n", status, errors);
|
| 105 |
} |
| 106 |
|
| 107 |
chprintf(stream, "read config...\n");
|
| 108 |
l3g4200d_lld_cfg_t cfg; |
| 109 |
status = l3g4200d_lld_read_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &cfg); |
| 110 |
if (status == APAL_STATUS_SUCCESS) {
|
| 111 |
aosUtPassed(stream, &result); |
| 112 |
} else {
|
| 113 |
aosUtFailed(stream, &result); |
| 114 |
} |
| 115 |
|
| 116 |
chprintf(stream, "write config...\n");
|
| 117 |
cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_100_HZ | L3G4200D_LLD_BW_12_5 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN; |
| 118 |
//cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_800_HZ | L3G4200D_LLD_BW_20 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN;
|
| 119 |
cfg.registers.ctrl_reg3 = 0x07;
|
| 120 |
cfg.registers.ctrl_reg5 |= L3G4200D_LLD_FIFO_EN; |
| 121 |
status = l3g4200d_lld_write_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, cfg); |
| 122 |
uint8_t reg1 = cfg.data[0];
|
| 123 |
status |= l3g4200d_lld_read_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &cfg); |
| 124 |
if (status == APAL_STATUS_SUCCESS && cfg.data[0] == reg1) { |
| 125 |
aosUtPassed(stream, &result); |
| 126 |
} else {
|
| 127 |
aosUtFailed(stream, &result); |
| 128 |
} |
| 129 |
|
| 130 |
chprintf(stream, "read gyro data for five seconds...\n");
|
| 131 |
status = APAL_STATUS_OK; |
| 132 |
for (uint8_t i = 0; i < 5; ++i) { |
| 133 |
status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
| 134 |
chprintf(stream, "\t\tX = %6d\tY = %6d\tZ = %6d\n", sdata[0], sdata[1], sdata[2]); |
| 135 |
aosThdSSleep(1);
|
| 136 |
} |
| 137 |
if (status == APAL_STATUS_SUCCESS) {
|
| 138 |
aosUtPassed(stream, &result); |
| 139 |
} else {
|
| 140 |
aosUtFailed(stream, &result); |
| 141 |
} |
| 142 |
|
| 143 |
chprintf(stream, "read X axis for five seconds...\n");
|
| 144 |
status = APAL_STATUS_SUCCESS; |
| 145 |
for (uint32_t i = 0; i <= 5; i++) { |
| 146 |
status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_X_AXIS, &cfg);
|
| 147 |
chprintf(stream, "\t\tX = %6d\n", sdata[0]); |
| 148 |
aosThdSSleep(1);
|
| 149 |
} |
| 150 |
if (status == APAL_STATUS_SUCCESS) {
|
| 151 |
aosUtPassed(stream, &result); |
| 152 |
} else {
|
| 153 |
aosUtFailed(stream, &result); |
| 154 |
} |
| 155 |
|
| 156 |
chprintf(stream, "read Y axis for five seconds...\n");
|
| 157 |
status = APAL_STATUS_SUCCESS; |
| 158 |
for (uint32_t i = 0; i <= 5; i++) { |
| 159 |
status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_Y_AXIS, &cfg);
|
| 160 |
chprintf(stream, "\t\tY = %6d\n", sdata[0]); |
| 161 |
aosThdSSleep(1);
|
| 162 |
} |
| 163 |
if (status == APAL_STATUS_SUCCESS) {
|
| 164 |
aosUtPassed(stream, &result); |
| 165 |
} else {
|
| 166 |
aosUtFailed(stream, &result); |
| 167 |
} |
| 168 |
|
| 169 |
chprintf(stream, "read Z axis for five seconds...\n");
|
| 170 |
status = APAL_STATUS_SUCCESS; |
| 171 |
for (uint32_t i = 0; i <= 5; i++) { |
| 172 |
status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_Z_AXIS, &cfg);
|
| 173 |
chprintf(stream, "\t\tZ = %6d\n", sdata[0]); |
| 174 |
aosThdSSleep(1);
|
| 175 |
} |
| 176 |
if (status == APAL_STATUS_SUCCESS) {
|
| 177 |
aosUtPassed(stream, &result); |
| 178 |
} else {
|
| 179 |
aosUtFailed(stream, &result); |
| 180 |
} |
| 181 |
aosThdMSleep(10);
|
| 182 |
|
| 183 |
chprintf(stream, "read status register...\n");
|
| 184 |
status = l3g4200d_lld_read_status_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &status_reg); |
| 185 |
if (status == APAL_STATUS_SUCCESS) {
|
| 186 |
aosUtPassed(stream, &result); |
| 187 |
} else {
|
| 188 |
aosUtFailed(stream, &result); |
| 189 |
} |
| 190 |
|
| 191 |
chprintf(stream, "read interrupt config...\n");
|
| 192 |
l3g4200d_lld_int_cfg_t int_cfg; |
| 193 |
status = l3g4200d_lld_read_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &int_cfg); |
| 194 |
if (status == APAL_STATUS_SUCCESS) {
|
| 195 |
aosUtPassed(stream, &result); |
| 196 |
} else {
|
| 197 |
aosUtFailed(stream, &result); |
| 198 |
} |
| 199 |
|
| 200 |
chprintf(stream, "write interrupt config...\n");
|
| 201 |
int_cfg.registers.int1_tsh_xh = 10;
|
| 202 |
status = l3g4200d_lld_write_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, int_cfg); |
| 203 |
l3g4200d_lld_int_cfg_t int_cfg2; |
| 204 |
status |= l3g4200d_lld_read_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &int_cfg2); |
| 205 |
if (status == APAL_STATUS_SUCCESS && int_cfg.registers.int1_tsh_xh == 10) { |
| 206 |
aosUtPassed(stream, &result); |
| 207 |
} else {
|
| 208 |
aosUtFailed(stream, &result); |
| 209 |
} |
| 210 |
|
| 211 |
chprintf(stream, "interrupt test: read fifo until empty...\n");
|
| 212 |
chEvtRegister(((ut_l3g4200ddata_t*)(ut->data))->src, &el, 0);
|
| 213 |
status = l3g4200d_lld_write_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,fifo); |
| 214 |
fifo = 0;
|
| 215 |
status |= l3g4200d_lld_read_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
| 216 |
status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
| 217 |
chEvtGetAndClearFlags(&el); |
| 218 |
aosThdSSleep(1);
|
| 219 |
chEvtGetAndClearFlags(&el); |
| 220 |
success = false;
|
| 221 |
for (uint8_t i = 0; i < 200; i++) { |
| 222 |
status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
| 223 |
event_mask = chEvtWaitAnyTimeout(~0, TIME_IMMEDIATE);
|
| 224 |
status |= l3g4200d_lld_read_fifo_src_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
| 225 |
if (event_mask != 0 && ((fifo & L3G4200D_LLD_EMPTY) || fifo == 0)) { |
| 226 |
success = true;
|
| 227 |
break;
|
| 228 |
} |
| 229 |
aosThdMSleep(1);
|
| 230 |
} |
| 231 |
if (status == APAL_STATUS_SUCCESS && success) {
|
| 232 |
aosUtPassed(stream, &result); |
| 233 |
} else {
|
| 234 |
aosUtFailed(stream, &result); |
| 235 |
} |
| 236 |
|
| 237 |
fifo = 0x4A;
|
| 238 |
status |= l3g4200d_lld_write_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,fifo); |
| 239 |
cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_800_HZ | L3G4200D_LLD_BW_20 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN; |
| 240 |
cfg.registers.ctrl_reg3 = 0x04;
|
| 241 |
status |= l3g4200d_lld_write_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, cfg); |
| 242 |
chprintf(stream, "interrupt test: wait until wtm reached...\n");
|
| 243 |
for (uint8_t i = 0; i < 200; i++) { |
| 244 |
status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
| 245 |
event_mask = chEvtWaitAnyTimeout(~0, TIME_IMMEDIATE);
|
| 246 |
status |= l3g4200d_lld_read_fifo_src_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
| 247 |
if (event_mask != 0 && (fifo & L3G4200D_LLD_WTM)) { |
| 248 |
success = true;
|
| 249 |
break;
|
| 250 |
} |
| 251 |
aosThdMSleep(10);
|
| 252 |
} |
| 253 |
if (status == APAL_STATUS_SUCCESS && success) {
|
| 254 |
aosUtPassed(stream, &result); |
| 255 |
} else {
|
| 256 |
aosUtFailed(stream, &result); |
| 257 |
} |
| 258 |
|
| 259 |
chEvtUnregister(((ut_l3g4200ddata_t*)(ut->data))->src, &el); |
| 260 |
aosThdMSleep(10);
|
| 261 |
|
| 262 |
aosUtInfoMsg(stream, "driver object memory footprint: %u bytes\n", sizeof(L3G4200DDriver)); |
| 263 |
|
| 264 |
return result;
|
| 265 |
} |
| 266 |
|
| 267 |
#endif /* (AMIROOS_CFG_TESTS_ENABLE == true) && defined(AMIROLLD_CFG_USE_L3G4200D) */ |
| 268 |
|
| 269 |
|