AMiRo-OS

diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c

--- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c

+++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c

@@ -34,6 +34,7 @@

 /* Driver local definitions.                                                 */

 /*===========================================================================*/

+#if STM32_I2C_I2C1_USE_DMA

 #define I2C1_RX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM,                        \

                        STM32_I2C1_RX_DMA_CHN)

@@ -41,7 +42,9 @@

 #define I2C1_TX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM,                        \

                        STM32_I2C1_TX_DMA_CHN)

+#endif

+#if STM32_I2C_I2C2_USE_DMA

 #define I2C2_RX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM,                        \

                        STM32_I2C2_RX_DMA_CHN)

@@ -49,7 +52,9 @@

 #define I2C2_TX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM,                        \

                        STM32_I2C2_TX_DMA_CHN)

+#endif

+#if STM32_I2C_I2C3_USE_DMA

 #define I2C3_RX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM,                        \

                        STM32_I2C3_RX_DMA_CHN)

@@ -57,6 +62,7 @@

 #define I2C3_TX_DMA_CHANNEL                                                 \

   STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM,                        \

                        STM32_I2C3_TX_DMA_CHN)

+#endif

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -72,6 +78,20 @@

 #define I2C_EV6_MASTER_REC_MODE_SELECTED                                    \

   ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))

+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED                                    \

+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_RXNE))

+

+#define I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP                               \

+  ((uint32_t)(I2C_SR1_RXNE))

+

+#define I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED                              \

+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) |                         \

+              I2C_SR1_BTF | I2C_SR1_RXNE))

+

+#define I2C_EV8_MASTER_BYTE_TRANSMITTING                                    \

+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA)<< 16) |           \

+              I2C_SR1_TXE))

+

 #define I2C_EV8_2_MASTER_BYTE_TRANSMITTED                                   \

   ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) |          \

               I2C_SR1_BTF | I2C_SR1_TXE))

@@ -129,8 +149,24 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {

   dp->SR1 = 0;

   /* Stops the associated DMA streams.*/

-  dmaStreamDisable(i2cp->dmatx);

-  dmaStreamDisable(i2cp->dmarx);

+#if STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA

+  if (&I2CD1 == i2cp) {

+    dmaStreamDisable(i2cp->dmatx);

+    dmaStreamDisable(i2cp->dmarx);

+  }

+#endif

+#if STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA

+  if (&I2CD2 == i2cp) {

+    dmaStreamDisable(i2cp->dmatx);

+    dmaStreamDisable(i2cp->dmarx);

+  }

+#endif

+#if STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA

+  if (&I2CD3 == i2cp) {

+    dmaStreamDisable(i2cp->dmatx);

+    dmaStreamDisable(i2cp->dmarx);

+  }

+#endif

 }

 /**

@@ -235,14 +271,18 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {

   dp->CR1 = regCR1;

 }

+#if (STM32_I2C_USE_I2C1 && STM32_I2C_I2C1_USE_DMA) ||                       \

+    (STM32_I2C_USE_I2C2 && STM32_I2C_I2C2_USE_DMA) ||                       \

+    (STM32_I2C_USE_I2C3 && STM32_I2C_I2C3_USE_DMA) ||                       \

+    defined(__DOXYGEN__)

 /**

- * @brief   I2C shared ISR code.

+ * @brief   I2C shared ISR code for DMA access.

  *

  * @param[in] i2cp      pointer to the @p I2CDriver object

  *

  * @notapi

  */

-static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {

+static void i2c_lld_serve_event_interrupt_dma(I2CDriver *i2cp) {

   I2C_TypeDef *dp = i2cp->i2c;

   uint32_t regSR2 = dp->SR2;

   uint32_t event = dp->SR1;

@@ -252,7 +292,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {

      done by the DMA.*/

   switch (I2C_EV_MASK & (event | (regSR2 << 16))) {

   case I2C_EV5_MASTER_MODE_SELECT:

-    if ((i2cp->addr >> 8) > 0) { 

+    if ((i2cp->addr >> 8) > 0) {

       /* 10-bit address: 1 1 1 1 0 X X R/W */

       dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);

     } else {

@@ -293,7 +333,146 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {

   if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))

     (void)dp->SR2;

 }

+#endif /* any I2CDx uses DMA mode */

+

+#if (STM32_I2C_USE_I2C1 && !STM32_I2C_I2C1_USE_DMA) ||                      \

+    (STM32_I2C_USE_I2C2 && !STM32_I2C_I2C2_USE_DMA) ||                      \

+    (STM32_I2C_USE_I2C3 && !STM32_I2C_I2C3_USE_DMA) ||                      \

+    defined(__DOXYGEN__)

+/**

+ * @brief   I2C shared ISR code for non-DMA access.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ *

+ * @notapi

+ */

+static void i2c_lld_serve_event_interrupt_isr(I2CDriver *i2cp) {

+  I2C_TypeDef *dp = i2cp->i2c;

+  uint32_t regSR2 = dp->SR2;

+  uint32_t event = dp->SR1;

+

+  switch (I2C_EV_MASK & (event | (regSR2 << 16))) {

+  case I2C_EV5_MASTER_MODE_SELECT:

+    dp->CR2 |= I2C_CR2_ITBUFEN;

+    dp->DR = i2cp->addr;

+    break;

+  case I2C_EV6_MASTER_TRA_MODE_SELECTED:

+    (void)dp->SR2; // clear ADDR flag

+    /* EV8_1 */

+    dp->DR = *(i2cp->txbuf);

+

+    ++i2cp->txbuf;

+    --i2cp->txbytes;

+

+    /* if N == 1, skip the I2C_EV8_MASTER_BYTE_TRANSMITTING event

+     * but enter I2C_EV8_2_MASTER_BYTE_TRANSMITTED next */

+    if (i2cp->txbytes == 0) {

+      dp->CR2 &= ~I2C_CR2_ITBUFEN;

+    }

+    break;

+  case I2C_EV6_MASTER_REC_MODE_SELECTED:

+    switch (i2cp->rxbytes) {

+    case 1:

+      dp->CR1 &= ~I2C_CR1_ACK;

+      (void)dp->SR2; // clear ADDR flag

+      dp->CR1 |= I2C_CR1_STOP;

+      break;

+    case 2:

+      (void)dp->SR2; // clear ADDR flag

+      /* EV6_1 */

+      dp->CR1 |= I2C_CR1_POS;

+      dp->CR1 &= ~I2C_CR1_ACK;

+      dp->CR2 &= ~I2C_CR2_ITBUFEN;

+      break;

+    case 3: /* N == 3 is a very special case, since EV7 is completely skipped */

+      (void)dp->SR2; // clear ADDR flag

+      /* Disable the I2C_EV7_MASTER_REC_BYTE_RECEIVED event

+       * but enter I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP next */

+      dp->CR2 &= ~I2C_CR2_ITBUFEN;

+      break;

+    default: /* N > 2 */

+      (void)dp->SR2; // clear ADDR flag

+      break;

+    }

+    break;

+  case I2C_EV7_MASTER_REC_BYTE_RECEIVED:

+    if (i2cp->rxbytes > 3) {

+      *(i2cp->rxbuf) = dp->DR;

+      ++i2cp->rxbuf;

+      --i2cp->rxbytes;

+    }

+    if (i2cp->rxbytes == 3) {

+      /* Disable this event for DataN-2, but force into event

+       * I2C_EV7_2_EV7_3_MASTER_REC_BYTE_RECEIVED_QUEUED by not reading dp->DR. */

+      dp->CR2 &= ~I2C_CR2_ITBUFEN;

+    }

+    break;

+  case I2C_EV7_MASTER_REC_BYTE_RECEIVED_STOP:

+    osalDbgAssert(i2cp->rxbytes == 1, "more than 1 byte to be received");

+    *(i2cp->rxbuf) = dp->DR;

+    --i2cp->rxbytes;

+    dp->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);

+    _i2c_wakeup_isr(i2cp);

+    break;

+  case I2C_EV7_2_EV7_3_MASTER_REC_BYTE_QUEUED:

+    if (i2cp->rxbytes == 3) {

+      /* EV7_2 (N > 2) */

+      dp->CR1 &= ~I2C_CR1_ACK;

+      *(i2cp->rxbuf) = dp->DR;

+      ++i2cp->rxbuf;

+      dp->CR1 |= I2C_CR1_STOP;

+