amiro-os / modules / DiWheelDrive_1-2 / board.h @ f38aba21
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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019 Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief DiWheeDrive v1.2 Board specific macros.
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*
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* @addtogroup diwheeldrive_board
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* @{
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*/
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#ifndef BOARD_H
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#define BOARD_H
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/*
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* Setup for AMiRo DiWheelDrive v1.2 board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_DIWHEELDRIVE_1_2
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#define BOARD_NAME "AMiRo DiWheelDrive v1.2" |
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/*
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* Board oscillators-related settings.
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* NOTE: LSE not fitted.
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*/
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 0U |
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U |
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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*/
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#define STM32_VDD 330U |
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/*
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* MCU type as defined in the ST header.
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*/
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#define STM32F103xE
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/*
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* IO pins assignments.
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*/
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#define GPIOA_WKUP 0U |
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#define GPIOA_LED 1U |
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#define GPIOA_DRIVE_PWM1A 2U |
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#define GPIOA_DRIVE_PWM1B 3U |
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#define GPIOA_PIN4 4U |
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#define GPIOA_PIN5 5U |
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#define GPIOA_PIN6 6U |
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#define GPIOA_PIN7 7U |
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#define GPIOA_PIN8 8U |
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#define GPIOA_PROG_RX 9U |
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#define GPIOA_PROG_TX 10U |
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#define GPIOA_CAN_RX 11U |
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#define GPIOA_CAN_TX 12U |
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#define GPIOA_SWDIO 13U |
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#define GPIOA_SWCLK 14U |
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#define GPIOA_DRIVE_PWM2B 15U |
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#define GPIOB_PIN0 0U |
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#define GPIOB_DRIVE_SENSE2 1U |
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#define GPIOB_POWER_EN 2U |
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#define GPIOB_DRIVE_PWM2A 3U |
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#define GPIOB_PIN4 4U |
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#define GPIOB_PIN5 5U |
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#define GPIOB_DRIVE_ENC1A 6U |
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#define GPIOB_DRIVE_ENC1B 7U |
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#define GPIOB_IMU_SCL 8U |
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#define GPIOB_IMU_SDA 9U |
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#define GPIOB_IR_SCL 10U |
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#define GPIOB_IR_SDA 11U |
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#define GPIOB_IR_INT 12U |
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#define GPIOB_PIN13 13U |
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#define GPIOB_SYS_UART_UP 14U |
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#define GPIOB_IMU_INT 15U |
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#define GPIOC_DRIVE_SENSE1 0U |
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#define GPIOC_SYS_INT_N 1U |
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#define GPIOC_IMU_RESET_N 2U |
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#define GPIOC_PATH_DCSTAT 3U |
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#define GPIOC_PIN4 4U |
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#define GPIOC_PATH_DCEN 5U |
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#define GPIOC_DRIVE_ENC2B 6U |
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#define GPIOC_DRIVE_ENC2A 7U |
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#define GPIOC_SYS_PD_N 8U |
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#define GPIOC_SYS_REG_EN 9U |
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#define GPIOC_SYS_UART_RX 10U |
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#define GPIOC_SYS_UART_TX 11U |
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#define GPIOC_IMU_BOOT_LOAD_N 12U |
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#define GPIOC_PIN13 13U |
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#define GPIOC_PIN14 14U |
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#define GPIOC_IMU_BL_IND 15U |
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#define GPIOD_OSC_IN 0U |
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#define GPIOD_OSC_OUT 1U |
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#define GPIOD_SYS_WARMRST_N 2U |
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#define GPIOD_PIN3 3U |
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#define GPIOD_PIN4 4U |
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#define GPIOD_PIN5 5U |
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#define GPIOD_PIN6 6U |
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#define GPIOD_PIN7 7U |
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#define GPIOD_PIN8 8U |
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#define GPIOD_PIN9 9U |
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#define GPIOD_PIN10 10U |
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#define GPIOD_PIN11 11U |
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#define GPIOD_PIN12 12U |
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#define GPIOD_PIN13 13U |
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#define GPIOD_PIN14 14U |
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#define GPIOD_PIN15 15U |
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#define GPIOE_PIN0 0U |
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#define GPIOE_PIN1 1U |
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#define GPIOE_PIN2 2U |
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#define GPIOE_PIN3 3U |
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#define GPIOE_PIN4 4U |
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#define GPIOE_PIN5 5U |
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#define GPIOE_PIN6 6U |
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#define GPIOE_PIN7 7U |
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#define GPIOE_PIN8 8U |
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#define GPIOE_PIN9 9U |
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#define GPIOE_PIN10 10U |
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#define GPIOE_PIN11 11U |
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#define GPIOE_PIN12 12U |
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#define GPIOE_PIN13 13U |
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#define GPIOE_PIN14 14U |
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#define GPIOE_PIN15 15U |
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#define GPIOF_PIN0 0U |
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#define GPIOF_PIN1 1U |
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#define GPIOF_PIN2 2U |
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#define GPIOF_PIN3 3U |
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#define GPIOF_PIN4 4U |
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#define GPIOF_PIN5 5U |
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#define GPIOF_PIN6 6U |
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#define GPIOF_PIN7 7U |
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#define GPIOF_PIN8 8U |
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#define GPIOF_PIN9 9U |
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#define GPIOF_PIN10 10U |
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#define GPIOF_PIN11 11U |
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#define GPIOF_PIN12 12U |
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#define GPIOF_PIN13 13U |
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#define GPIOF_PIN14 14U |
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#define GPIOF_PIN15 15U |
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#define GPIOG_PIN0 0U |
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#define GPIOG_PIN1 1U |
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#define GPIOG_PIN2 2U |
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#define GPIOG_PIN3 3U |
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#define GPIOG_PIN4 4U |
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#define GPIOG_PIN5 5U |
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#define GPIOG_PIN6 6U |
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#define GPIOG_PIN7 7U |
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#define GPIOG_PIN8 8U |
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#define GPIOG_PIN9 9U |
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#define GPIOG_PIN10 10U |
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#define GPIOG_PIN11 11U |
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#define GPIOG_PIN12 12U |
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#define GPIOG_PIN13 13U |
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#define GPIOG_PIN14 14U |
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#define GPIOG_PIN15 15U |
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/*
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* IO lines assignments.
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*/
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#define LINE_WKUP PAL_LINE(GPIOA, GPIOA_WKUP)
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#define LINE_LED PAL_LINE(GPIOA, GPIOA_LED)
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#define LINE_DRIVE_PWM1A PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1A)
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#define LINE_DRIVE_PWM1B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM1B)
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#define LINE_PROG_RX PAL_LINE(GPIOA, GPIOA_PROG_RX)
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#define LINE_PROG_TX PAL_LINE(GPIOA, GPIOA_PROG_TX)
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#define LINE_CAN_RX PAL_LINE(GPIOA, GPIOA_CAN_RX)
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#define LINE_CAN_TX PAL_LINE(GPIOA, GPIOA_CAN_TX)
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#define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO)
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#define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK)
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#define LINE_DRIVE_PWM2B PAL_LINE(GPIOA, GPIOA_DRIVE_PWM2B)
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#define LINE_DRIVE_SENSE2 PAL_LINE(GPIOB, GPIOB_DRIVE_SENSE2)
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#define LINE_POWER_EN PAL_LINE(GPIOB, GPIOB_POWER_EN)
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#define LINE_DRIVE_PWM2A PAL_LINE(GPIOB, GPIOB_DRIVE_PWM2A)
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#define LINE_DRIVE_ENC1A PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1A)
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#define LINE_DRIVE_ENC1B PAL_LINE(GPIOB, GPIOB_DRIVE_ENC1B)
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#define LINE_IMU_SCL PAL_LINE(GPIOB, GPIOB_IMU_SCL)
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#define LINE_IMU_SDA PAL_LINE(GPIOB, GPIOB_IMU_SDA)
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#define LINE_IR_SCL PAL_LINE(GPIOB, GPIOB_IR_SCL)
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#define LINE_IR_SDA PAL_LINE(GPIOB, GPIOB_IR_SDA)
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#define LINE_IR_INT PAL_LINE(GPIOB, GPIOB_IR_INT)
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#define LINE_SYS_UART_UP PAL_LINE(GPIOB, GPIOB_SYS_UART_UP)
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#define LINE_IMU_INT PAL_LINE(GPIOB, GPIOB_IMU_INT)
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#define LINE_DRIVE_SENSE1 PAL_LINE(GPIOC, GPIOC_DRIVE_SENSE1)
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#define LINE_SYS_INT_N PAL_LINE(GPIOC, GPIOC_SYS_INT_N)
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#define LINE_IMU_RESET_N PAL_LINE(GPIOC, GPIOC_IMU_RESET_N)
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#define LINE_PATH_DCSTAT PAL_LINE(GPIOC, GPIOC_PATH_DCSTAT)
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#define LINE_PATH_DCEN PAL_LINE(GPIOC, GPIOC_PATH_DCEN)
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#define LINE_DRIVE_ENC2B PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2B)
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#define LINE_DRIVE_ENC2A PAL_LINE(GPIOC, GPIOC_DRIVE_ENC2A)
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#define LINE_SYS_PD_N PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
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#define LINE_SYS_REG_EN PAL_LINE(GPIOC, GPIOC_SYS_REG_EN)
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#define LINE_SYS_UART_RX PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
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#define LINE_SYS_UART_TX PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
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#define LINE_IMU_BOOT_LOAD_N PAL_LINE(GPIOC, GPIOC_IMU_BOOT_LOAD_N)
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#define LINE_IMU_BL_IND PAL_LINE(GPIOC, GPIOC_IMU_BL_IND)
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#define LINE_OSC_IN PAL_LINE(GPIOD, GPIOD_OSC_IN)
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#define LINE_OSC_OUT PAL_LINE(GPIOD, GPIOD_OSC_OUT)
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#define LINE_SYS_WARMRST_N PAL_LINE(GPIOD, GPIOD_SYS_WARMRST_N)
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT 0U |
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#define PIN_MODE_OUTPUT_2M 2U |
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#define PIN_MODE_OUTPUT_10M 1U |
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#define PIN_MODE_OUTPUT_50M 3U |
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#define PIN_CNF_INPUT_ANALOG 0U |
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#define PIN_CNF_INPUT_FLOATING 1U |
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#define PIN_CNF_INPUT_PULLX 2U |
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#define PIN_CNF_OUTPUT_PUSHPULL 0U |
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#define PIN_CNF_OUTPUT_OPENDRAIN 1U |
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#define PIN_CNF_ALTERNATE_PUSHPULL 2U |
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#define PIN_CNF_ALTERNATE_OPENDRAIN 3U |
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#define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
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#define PIN_ODR_LOW(n) (0U << (n)) |
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#define PIN_ODR_HIGH(n) (1U << (n)) |
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#define PIN_IGNORE(n) (1U << (n)) |
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/*
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* GPIOA setup:
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*
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* PA0 - WKUP (input floating)
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* PA1 - LED (output opendrain high 50MHz)
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* PA2 - DRIVE_PWM1A (alternate pushpull 50MHz)
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* PA3 - DRIVE_PWM1B (alternate pushpull 50MHz)
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* PA4 - PIN4 (input floating)
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* PA5 - PIN5 (input floating)
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* PA6 - PIN6 (input floating)
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* PA7 - PIN7 (input floating)
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* PA8 - PIN8 (input floating)
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* PA9 - PROG_RX (alternate pushpull 50MHz)
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* PA10 - PROG_TX (input pullup)
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* PA11 - CAN_RX (input pullup)
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* PA12 - CAN_TX (alternate pushpull 50MHz)
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* PA13 - SWDIO (input pullup)
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* PA14 - SWCLK (input pullup)
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* PA15 - DRIVE_PWM2B (alternate pushpull 50MHz)
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*/
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#define VAL_GPIOAIGN (PIN_IGNORE(GPIOA_LED)) & 0 |
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#define VAL_GPIOACRL (PIN_CR(GPIOA_WKUP, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOA_LED, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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PIN_CR(GPIOA_DRIVE_PWM1A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_DRIVE_PWM1B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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#define VAL_GPIOACRH (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_DRIVE_PWM2B, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
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#define VAL_GPIOAODR (PIN_ODR_HIGH(GPIOA_WKUP) | \
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PIN_ODR_HIGH(GPIOA_LED) | \ |
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PIN_ODR_HIGH(GPIOA_DRIVE_PWM1A) | \ |
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PIN_ODR_HIGH(GPIOA_DRIVE_PWM1B) | \ |
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PIN_ODR_LOW(GPIOA_PIN4) | \ |
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PIN_ODR_LOW(GPIOA_PIN5) | \ |
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PIN_ODR_LOW(GPIOA_PIN6) | \ |
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PIN_ODR_LOW(GPIOA_PIN7) | \ |
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PIN_ODR_LOW(GPIOA_PIN8) | \ |
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PIN_ODR_HIGH(GPIOA_PROG_RX) | \ |
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PIN_ODR_HIGH(GPIOA_PROG_TX) | \ |
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PIN_ODR_HIGH(GPIOA_CAN_RX) | \ |
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PIN_ODR_HIGH(GPIOA_CAN_TX) | \ |
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PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
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PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
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PIN_ODR_HIGH(GPIOA_DRIVE_PWM2B)) |
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/*
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* GPIOB setup:
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*
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* PB0 - PIN0 (input floating)
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* PB1 - DRIVE_SENSE2 (input analog)
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* PB2 - POWER_EN (output pushpull low 50MHz)
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* PB3 - DRIVE_PWM2A (alternate pushpull 50MHz)
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* PB4 - PIN4 (input floating)
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* PB5 - PIN5 (input floating)
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* PB6 - DRIVE_ENC1A (input floating)
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* PB7 - DRIVE_ENC1B (input floating)
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* PB8 - IMU_SCL (alternate opendrain 50MHz)
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* PB9 - IMU_SDA (alternate opendrain 50MHz)
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* PB10 - IR_SCL (alternate opendrain 50MHz)
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* PB11 - IR_SDA (alternate opendrain 50MHz)
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* PB12 - IR_INT (input floating)
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* PB13 - PIN13 (input floating)
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* PB14 - SYS_UART_UP (output opendrain high 50MHz)
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* PB15 - IMU_INT (input floating)
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*/
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#define VAL_GPIOBIGN (PIN_IGNORE(GPIOB_SYS_UART_UP)) & 0 |
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#define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOB_DRIVE_SENSE2, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \ |
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PIN_CR(GPIOB_POWER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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PIN_CR(GPIOB_DRIVE_PWM2A, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_DRIVE_ENC1A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_DRIVE_ENC1B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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#define VAL_GPIOBCRH (PIN_CR(GPIOB_IMU_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \
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PIN_CR(GPIOB_IMU_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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PIN_CR(GPIOB_IR_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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PIN_CR(GPIOB_IR_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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PIN_CR(GPIOB_IR_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_SYS_UART_UP, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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PIN_CR(GPIOB_IMU_INT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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#define VAL_GPIOBODR (PIN_ODR_LOW(GPIOB_PIN0) | \
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PIN_ODR_HIGH(GPIOB_DRIVE_SENSE2) | \ |
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PIN_ODR_LOW(GPIOB_POWER_EN) | \ |
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PIN_ODR_HIGH(GPIOB_DRIVE_PWM2A) | \ |
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PIN_ODR_LOW(GPIOB_PIN4) | \ |
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PIN_ODR_LOW(GPIOB_PIN5) | \ |
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PIN_ODR_HIGH(GPIOB_DRIVE_ENC1A) | \ |
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PIN_ODR_HIGH(GPIOB_DRIVE_ENC1B) | \ |
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PIN_ODR_HIGH(GPIOB_IMU_SCL) | \ |
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PIN_ODR_HIGH(GPIOB_IMU_SDA) | \ |
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PIN_ODR_HIGH(GPIOB_IR_SCL) | \ |
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PIN_ODR_HIGH(GPIOB_IR_SDA) | \ |
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PIN_ODR_HIGH(GPIOB_IR_INT) | \ |
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PIN_ODR_LOW(GPIOB_PIN13) | \ |
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PIN_ODR_HIGH(GPIOB_SYS_UART_UP) | \ |
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PIN_ODR_LOW(GPIOB_IMU_INT)) |
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/*
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* GPIOC setup:
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*
|
| 363 |
* PC0 - DRIVE_SENSE1 (input analog)
|
| 364 |
* PC1 - SYS_INT_N (output opendrain low 50MHz)
|
| 365 |
* PC2 - IMU_RESET_N (output opendrain high 50MHz)
|
| 366 |
* PC3 - PATH_DCSTAT (input floating)
|
| 367 |
* PC4 - PIN4 (input floating)
|
| 368 |
* PC5 - PATH_DCEN (output pushpull low 50MHz)
|
| 369 |
* PC6 - DRIVE_ENC2B (input floating)
|
| 370 |
* PC7 - DRIVE_ENC2A (input floating)
|
| 371 |
* PC8 - SYS_PD_N (output opendrain high 50MHz)
|
| 372 |
* PC9 - SYS_REG_EN (input floating)
|
| 373 |
* PC10 - SYS_UART_RX (input floating)
|
| 374 |
* PC11 - SYS_UART_TX (input floating)
|
| 375 |
* PC12 - IMU_BOOT_LOAD_N (output opendrain high 50MHz)
|
| 376 |
* PC13 - PIN13 (input floating)
|
| 377 |
* PC14 - PIN14 (input floating)
|
| 378 |
* PC15 - IMU_BL_IND (input floating)
|
| 379 |
*/
|
| 380 |
#define VAL_GPIOCIGN (PIN_IGNORE(GPIOC_SYS_INT_N) | \
|
| 381 |
PIN_IGNORE(GPIOC_SYS_PD_N)) & 0
|
| 382 |
#define VAL_GPIOCCRL (PIN_CR(GPIOC_DRIVE_SENSE1, PIN_MODE_INPUT, PIN_CNF_INPUT_ANALOG) | \
|
| 383 |
PIN_CR(GPIOC_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 384 |
PIN_CR(GPIOC_IMU_RESET_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 385 |
PIN_CR(GPIOC_PATH_DCSTAT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 386 |
PIN_CR(GPIOC_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 387 |
PIN_CR(GPIOC_PATH_DCEN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
| 388 |
PIN_CR(GPIOC_DRIVE_ENC2B, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 389 |
PIN_CR(GPIOC_DRIVE_ENC2A, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 390 |
#define VAL_GPIOCCRH (PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \
|
| 391 |
PIN_CR(GPIOC_SYS_REG_EN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 392 |
PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 393 |
PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 394 |
PIN_CR(GPIOC_IMU_BOOT_LOAD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 395 |
PIN_CR(GPIOC_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 396 |
PIN_CR(GPIOC_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 397 |
PIN_CR(GPIOC_IMU_BL_IND, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 398 |
#define VAL_GPIOCODR (PIN_ODR_HIGH(GPIOC_DRIVE_SENSE1) | \
|
| 399 |
PIN_ODR_LOW(GPIOC_SYS_INT_N) | \ |
| 400 |
PIN_ODR_HIGH(GPIOC_IMU_RESET_N) | \ |
| 401 |
PIN_ODR_HIGH(GPIOC_PATH_DCSTAT) | \ |
| 402 |
PIN_ODR_LOW(GPIOC_PIN4) | \ |
| 403 |
PIN_ODR_LOW(GPIOC_PATH_DCEN) | \ |
| 404 |
PIN_ODR_HIGH(GPIOC_DRIVE_ENC2B) | \ |
| 405 |
PIN_ODR_HIGH(GPIOC_DRIVE_ENC2A) | \ |
| 406 |
PIN_ODR_HIGH(GPIOC_SYS_PD_N) | \ |
| 407 |
PIN_ODR_HIGH(GPIOC_SYS_REG_EN) | \ |
| 408 |
PIN_ODR_HIGH(GPIOC_SYS_UART_RX) | \ |
| 409 |
PIN_ODR_HIGH(GPIOC_SYS_UART_TX) | \ |
| 410 |
PIN_ODR_HIGH(GPIOC_IMU_BOOT_LOAD_N) | \ |
| 411 |
PIN_ODR_LOW(GPIOC_PIN13) | \ |
| 412 |
PIN_ODR_LOW(GPIOC_PIN14) | \ |
| 413 |
PIN_ODR_LOW(GPIOC_IMU_BL_IND)) |
| 414 |
|
| 415 |
/*
|
| 416 |
* GPIOD setup:
|
| 417 |
*
|
| 418 |
* PD0 - OSC_IN (input floating)
|
| 419 |
* PD1 - OSC_OUT (input floating)
|
| 420 |
* PD2 - SYS_WARMRST_N (output opendrain high 50MHz)
|
| 421 |
* PD3 - PIN3 (input floating)
|
| 422 |
* PD4 - PIN4 (input floating)
|
| 423 |
* PD5 - PIN5 (input floating)
|
| 424 |
* PD6 - PIN6 (input floating)
|
| 425 |
* PD7 - PIN7 (input floating)
|
| 426 |
* PD8 - PIN8 (input floating)
|
| 427 |
* PD9 - PIN9 (input floating)
|
| 428 |
* PD10 - PIN10 (input floating)
|
| 429 |
* PD11 - PIN11 (input floating)
|
| 430 |
* PD12 - PIN12 (input floating)
|
| 431 |
* PD13 - PIN13 (input floating)
|
| 432 |
* PD14 - PIN14 (input floating)
|
| 433 |
* PD15 - PIN15 (input floating)
|
| 434 |
*/
|
| 435 |
#define VAL_GPIODIGN 0 |
| 436 |
#define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 437 |
PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 438 |
PIN_CR(GPIOD_SYS_WARMRST_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 439 |
PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 440 |
PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 441 |
PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 442 |
PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 443 |
PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 444 |
#define VAL_GPIODCRH (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 445 |
PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 446 |
PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 447 |
PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 448 |
PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 449 |
PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 450 |
PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 451 |
PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 452 |
#define VAL_GPIODODR (PIN_ODR_HIGH(GPIOD_OSC_IN) | \
|
| 453 |
PIN_ODR_HIGH(GPIOD_OSC_OUT) | \ |
| 454 |
PIN_ODR_HIGH(GPIOD_SYS_WARMRST_N) | \ |
| 455 |
PIN_ODR_LOW(GPIOD_PIN3) | \ |
| 456 |
PIN_ODR_LOW(GPIOD_PIN4) | \ |
| 457 |
PIN_ODR_LOW(GPIOD_PIN5) | \ |
| 458 |
PIN_ODR_LOW(GPIOD_PIN6) | \ |
| 459 |
PIN_ODR_LOW(GPIOD_PIN7) | \ |
| 460 |
PIN_ODR_LOW(GPIOD_PIN8) | \ |
| 461 |
PIN_ODR_LOW(GPIOD_PIN9) | \ |
| 462 |
PIN_ODR_LOW(GPIOD_PIN10) | \ |
| 463 |
PIN_ODR_LOW(GPIOD_PIN11) | \ |
| 464 |
PIN_ODR_LOW(GPIOD_PIN12) | \ |
| 465 |
PIN_ODR_LOW(GPIOD_PIN13) | \ |
| 466 |
PIN_ODR_LOW(GPIOD_PIN14) | \ |
| 467 |
PIN_ODR_LOW(GPIOD_PIN15)) |
| 468 |
|
| 469 |
/*
|
| 470 |
* GPIOE setup:
|
| 471 |
*
|
| 472 |
* PE0 - PIN0 (input floating)
|
| 473 |
* PE1 - PIN1 (input floating)
|
| 474 |
* PE2 - PIN2 (input floating)
|
| 475 |
* PE3 - PIN3 (input floating)
|
| 476 |
* PE4 - PIN4 (input floating)
|
| 477 |
* PE5 - PIN5 (input floating)
|
| 478 |
* PE6 - PIN6 (input floating)
|
| 479 |
* PE7 - PIN7 (input floating)
|
| 480 |
* PE8 - PIN8 (input floating)
|
| 481 |
* PE9 - PIN9 (input floating)
|
| 482 |
* PE10 - PIN10 (input floating)
|
| 483 |
* PE11 - PIN11 (input floating)
|
| 484 |
* PE12 - PIN12 (input floating)
|
| 485 |
* PE13 - PIN13 (input floating)
|
| 486 |
* PE14 - PIN14 (input floating)
|
| 487 |
* PE15 - PIN15 (input floating)
|
| 488 |
*/
|
| 489 |
#define VAL_GPIOEIGN 0 |
| 490 |
#define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 491 |
PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 492 |
PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 493 |
PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 494 |
PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 495 |
PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 496 |
PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 497 |
PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 498 |
#define VAL_GPIOECRH (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 499 |
PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 500 |
PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 501 |
PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 502 |
PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 503 |
PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 504 |
PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 505 |
PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 506 |
#define VAL_GPIOEODR (PIN_ODR_LOW(GPIOE_PIN0) | \
|
| 507 |
PIN_ODR_LOW(GPIOE_PIN1) | \ |
| 508 |
PIN_ODR_LOW(GPIOE_PIN2) | \ |
| 509 |
PIN_ODR_LOW(GPIOE_PIN3) | \ |
| 510 |
PIN_ODR_LOW(GPIOE_PIN4) | \ |
| 511 |
PIN_ODR_LOW(GPIOE_PIN5) | \ |
| 512 |
PIN_ODR_LOW(GPIOE_PIN6) | \ |
| 513 |
PIN_ODR_LOW(GPIOE_PIN7) | \ |
| 514 |
PIN_ODR_LOW(GPIOE_PIN8) | \ |
| 515 |
PIN_ODR_LOW(GPIOE_PIN9) | \ |
| 516 |
PIN_ODR_LOW(GPIOE_PIN10) | \ |
| 517 |
PIN_ODR_LOW(GPIOE_PIN11) | \ |
| 518 |
PIN_ODR_LOW(GPIOE_PIN12) | \ |
| 519 |
PIN_ODR_LOW(GPIOE_PIN13) | \ |
| 520 |
PIN_ODR_LOW(GPIOE_PIN14) | \ |
| 521 |
PIN_ODR_LOW(GPIOE_PIN15)) |
| 522 |
|
| 523 |
/*
|
| 524 |
* GPIOF setup:
|
| 525 |
*
|
| 526 |
* PF0 - PIN0 (input floating)
|
| 527 |
* PF1 - PIN1 (input floating)
|
| 528 |
* PF2 - PIN2 (input floating)
|
| 529 |
* PF3 - PIN3 (input floating)
|
| 530 |
* PF4 - PIN4 (input floating)
|
| 531 |
* PF5 - PIN5 (input floating)
|
| 532 |
* PF6 - PIN6 (input floating)
|
| 533 |
* PF7 - PIN7 (input floating)
|
| 534 |
* PF8 - PIN8 (input floating)
|
| 535 |
* PF9 - PIN9 (input floating)
|
| 536 |
* PF10 - PIN10 (input floating)
|
| 537 |
* PF11 - PIN11 (input floating)
|
| 538 |
* PF12 - PIN12 (input floating)
|
| 539 |
* PF13 - PIN13 (input floating)
|
| 540 |
* PF14 - PIN14 (input floating)
|
| 541 |
* PF15 - PIN15 (input floating)
|
| 542 |
*/
|
| 543 |
#define VAL_GPIOFIGN 0 |
| 544 |
#define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 545 |
PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 546 |
PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 547 |
PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 548 |
PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 549 |
PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 550 |
PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 551 |
PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 552 |
#define VAL_GPIOFCRH (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 553 |
PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 554 |
PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 555 |
PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 556 |
PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 557 |
PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 558 |
PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 559 |
PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 560 |
#define VAL_GPIOFODR (PIN_ODR_LOW(GPIOF_PIN0) | \
|
| 561 |
PIN_ODR_LOW(GPIOF_PIN1) | \ |
| 562 |
PIN_ODR_LOW(GPIOF_PIN2) | \ |
| 563 |
PIN_ODR_LOW(GPIOF_PIN3) | \ |
| 564 |
PIN_ODR_LOW(GPIOF_PIN4) | \ |
| 565 |
PIN_ODR_LOW(GPIOF_PIN5) | \ |
| 566 |
PIN_ODR_LOW(GPIOF_PIN6) | \ |
| 567 |
PIN_ODR_LOW(GPIOF_PIN7) | \ |
| 568 |
PIN_ODR_LOW(GPIOF_PIN8) | \ |
| 569 |
PIN_ODR_LOW(GPIOF_PIN9) | \ |
| 570 |
PIN_ODR_LOW(GPIOF_PIN10) | \ |
| 571 |
PIN_ODR_LOW(GPIOF_PIN11) | \ |
| 572 |
PIN_ODR_LOW(GPIOF_PIN12) | \ |
| 573 |
PIN_ODR_LOW(GPIOF_PIN13) | \ |
| 574 |
PIN_ODR_LOW(GPIOF_PIN14) | \ |
| 575 |
PIN_ODR_LOW(GPIOF_PIN15)) |
| 576 |
|
| 577 |
/*
|
| 578 |
* GPIOG setup:
|
| 579 |
*
|
| 580 |
* PG0 - PIN0 (input floating)
|
| 581 |
* PG1 - PIN1 (input floating)
|
| 582 |
* PG2 - PIN2 (input floating)
|
| 583 |
* PG3 - PIN3 (input floating)
|
| 584 |
* PG4 - PIN4 (input floating)
|
| 585 |
* PG5 - PIN5 (input floating)
|
| 586 |
* PG6 - PIN6 (input floating)
|
| 587 |
* PG7 - PIN7 (input floating)
|
| 588 |
* PG8 - PIN8 (input floating)
|
| 589 |
* PG9 - PIN9 (input floating)
|
| 590 |
* PG10 - PIN10 (input floating)
|
| 591 |
* PG11 - PIN11 (input floating)
|
| 592 |
* PG12 - PIN12 (input floating)
|
| 593 |
* PG13 - PIN13 (input floating)
|
| 594 |
* PG14 - PIN14 (input floating)
|
| 595 |
* PG15 - PIN15 (input floating)
|
| 596 |
*/
|
| 597 |
#define VAL_GPIOGIGN 0 |
| 598 |
#define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 599 |
PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 600 |
PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 601 |
PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 602 |
PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 603 |
PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 604 |
PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 605 |
PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 606 |
#define VAL_GPIOGCRH (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 607 |
PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 608 |
PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 609 |
PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 610 |
PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 611 |
PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 612 |
PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 613 |
PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 614 |
#define VAL_GPIOGODR (PIN_ODR_LOW(GPIOG_PIN0) | \
|
| 615 |
PIN_ODR_LOW(GPIOG_PIN1) | \ |
| 616 |
PIN_ODR_LOW(GPIOG_PIN2) | \ |
| 617 |
PIN_ODR_LOW(GPIOG_PIN3) | \ |
| 618 |
PIN_ODR_LOW(GPIOG_PIN4) | \ |
| 619 |
PIN_ODR_LOW(GPIOG_PIN5) | \ |
| 620 |
PIN_ODR_LOW(GPIOG_PIN6) | \ |
| 621 |
PIN_ODR_LOW(GPIOG_PIN7) | \ |
| 622 |
PIN_ODR_LOW(GPIOG_PIN8) | \ |
| 623 |
PIN_ODR_LOW(GPIOG_PIN9) | \ |
| 624 |
PIN_ODR_LOW(GPIOG_PIN10) | \ |
| 625 |
PIN_ODR_LOW(GPIOG_PIN11) | \ |
| 626 |
PIN_ODR_LOW(GPIOG_PIN12) | \ |
| 627 |
PIN_ODR_LOW(GPIOG_PIN13) | \ |
| 628 |
PIN_ODR_LOW(GPIOG_PIN14) | \ |
| 629 |
PIN_ODR_LOW(GPIOG_PIN15)) |
| 630 |
|
| 631 |
#if !defined(_FROM_ASM_)
|
| 632 |
#ifdef __cplusplus
|
| 633 |
extern "C" { |
| 634 |
#endif
|
| 635 |
void boardInit(void); |
| 636 |
#ifdef __cplusplus
|
| 637 |
} |
| 638 |
#endif
|
| 639 |
#endif /* _FROM_ASM_ */ |
| 640 |
|
| 641 |
#endif /* BOARD_H */ |
| 642 |
|
| 643 |
/** @} */
|