amiro-os / modules / RT-STM32L476RG-NUCLEO64 / board.c @ f3b3fe09
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1 | 27d0378b | Simon Welzel | /*
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2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License");
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5 | you may not use this file except in compliance with the License.
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6 | You may obtain a copy of the License at
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7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0
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9 | |||
10 | Unless required by applicable law or agreed to in writing, software
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11 | distributed under the License is distributed on an "AS IS" BASIS,
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12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | See the License for the specific language governing permissions and
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14 | limitations under the License.
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15 | */
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16 | |||
17 | /*
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18 | * This file has been automatically generated using ChibiStudio board
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19 | * generator plugin. Do not edit manually.
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20 | */
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21 | |||
22 | #include "hal.h" |
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23 | #include "stm32_gpio.h" |
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24 | |||
25 | /*===========================================================================*/
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26 | /* Driver local definitions. */
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27 | /*===========================================================================*/
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28 | |||
29 | /*===========================================================================*/
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30 | /* Driver exported variables. */
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31 | /*===========================================================================*/
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32 | |||
33 | /*===========================================================================*/
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34 | /* Driver local variables and types. */
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35 | /*===========================================================================*/
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36 | |||
37 | /**
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38 | * @brief Type of STM32 GPIO port setup.
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39 | */
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40 | typedef struct { |
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41 | uint32_t moder; |
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42 | uint32_t otyper; |
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43 | uint32_t ospeedr; |
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44 | uint32_t pupdr; |
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45 | uint32_t odr; |
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46 | uint32_t afrl; |
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47 | uint32_t afrh; |
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48 | uint32_t ascr; |
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49 | uint32_t lockr; |
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50 | } gpio_setup_t; |
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51 | |||
52 | /**
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53 | * @brief Type of STM32 GPIO initialization data.
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54 | */
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55 | typedef struct { |
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56 | #if STM32_HAS_GPIOA || defined(__DOXYGEN__)
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57 | gpio_setup_t PAData; |
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58 | #endif
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59 | #if STM32_HAS_GPIOB || defined(__DOXYGEN__)
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60 | gpio_setup_t PBData; |
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61 | #endif
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62 | #if STM32_HAS_GPIOC || defined(__DOXYGEN__)
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63 | gpio_setup_t PCData; |
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64 | #endif
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65 | #if STM32_HAS_GPIOD || defined(__DOXYGEN__)
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66 | gpio_setup_t PDData; |
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67 | #endif
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68 | #if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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69 | gpio_setup_t PEData; |
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70 | #endif
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71 | #if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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72 | gpio_setup_t PFData; |
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73 | #endif
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74 | #if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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75 | gpio_setup_t PGData; |
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76 | #endif
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77 | #if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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78 | gpio_setup_t PHData; |
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79 | #endif
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80 | #if STM32_HAS_GPIOI || defined(__DOXYGEN__)
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81 | gpio_setup_t PIData; |
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82 | #endif
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83 | #if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
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84 | gpio_setup_t PJData; |
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85 | #endif
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86 | #if STM32_HAS_GPIOK || defined(__DOXYGEN__)
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87 | gpio_setup_t PKData; |
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88 | #endif
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89 | } gpio_config_t; |
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90 | |||
91 | /**
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92 | * @brief STM32 GPIO static initialization data.
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93 | */
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94 | static const gpio_config_t gpio_default_config = { |
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95 | #if STM32_HAS_GPIOA
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96 | {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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97 | VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, |
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98 | VAL_GPIOA_LOCKR}, |
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99 | #endif
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100 | #if STM32_HAS_GPIOB
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101 | {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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102 | VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, |
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103 | VAL_GPIOB_LOCKR}, |
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104 | #endif
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105 | #if STM32_HAS_GPIOC
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106 | {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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107 | VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, |
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108 | VAL_GPIOC_LOCKR}, |
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109 | #endif
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110 | #if STM32_HAS_GPIOD
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111 | {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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112 | VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, |
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113 | VAL_GPIOD_LOCKR}, |
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114 | #endif
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115 | #if STM32_HAS_GPIOE
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116 | {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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117 | VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, |
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118 | VAL_GPIOE_LOCKR}, |
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119 | #endif
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120 | #if STM32_HAS_GPIOF
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121 | {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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122 | VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, |
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123 | VAL_GPIOF_LOCKR}, |
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124 | #endif
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125 | #if STM32_HAS_GPIOG
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126 | {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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127 | VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, |
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128 | VAL_GPIOG_LOCKR}, |
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129 | #endif
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130 | #if STM32_HAS_GPIOH
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131 | {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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132 | VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, |
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133 | VAL_GPIOH_LOCKR}, |
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134 | #endif
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135 | #if STM32_HAS_GPIOI
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136 | {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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137 | VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, |
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138 | VAL_GPIOI_LOCKR}, |
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139 | #endif
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140 | #if STM32_HAS_GPIOJ
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141 | {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, |
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142 | VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, |
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143 | VAL_GPIOJ_LOCKR}, |
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144 | #endif
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145 | #if STM32_HAS_GPIOK
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146 | {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, |
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147 | VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, |
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148 | VAL_GPIOK_LOCKR} |
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149 | #endif
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150 | }; |
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151 | |||
152 | /*===========================================================================*/
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153 | /* Driver local functions. */
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154 | /*===========================================================================*/
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155 | |||
156 | static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { |
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157 | |||
158 | gpiop->OTYPER = config->otyper; |
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159 | gpiop->ASCR = config->ascr; |
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160 | gpiop->OSPEEDR = config->ospeedr; |
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161 | gpiop->PUPDR = config->pupdr; |
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162 | gpiop->ODR = config->odr; |
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163 | gpiop->AFRL = config->afrl; |
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164 | gpiop->AFRH = config->afrh; |
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165 | gpiop->MODER = config->moder; |
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166 | gpiop->LOCKR = config->lockr; |
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167 | } |
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168 | |||
169 | static void stm32_gpio_init(void) { |
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170 | |||
171 | /* Enabling GPIO-related clocks, the mask comes from the
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172 | registry header file.*/
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173 | rccResetAHB2(STM32_GPIO_EN_MASK); |
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174 | rccEnableAHB2(STM32_GPIO_EN_MASK, true);
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175 | |||
176 | /* Initializing all the defined GPIO ports.*/
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177 | #if STM32_HAS_GPIOA
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178 | gpio_init(GPIOA, &gpio_default_config.PAData); |
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179 | #endif
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180 | #if STM32_HAS_GPIOB
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181 | gpio_init(GPIOB, &gpio_default_config.PBData); |
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182 | #endif
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183 | #if STM32_HAS_GPIOC
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184 | gpio_init(GPIOC, &gpio_default_config.PCData); |
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185 | #endif
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186 | #if STM32_HAS_GPIOD
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187 | gpio_init(GPIOD, &gpio_default_config.PDData); |
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188 | #endif
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189 | #if STM32_HAS_GPIOE
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190 | gpio_init(GPIOE, &gpio_default_config.PEData); |
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191 | #endif
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192 | #if STM32_HAS_GPIOF
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193 | gpio_init(GPIOF, &gpio_default_config.PFData); |
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194 | #endif
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195 | #if STM32_HAS_GPIOG
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196 | gpio_init(GPIOG, &gpio_default_config.PGData); |
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197 | #endif
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198 | #if STM32_HAS_GPIOH
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199 | gpio_init(GPIOH, &gpio_default_config.PHData); |
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200 | #endif
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201 | #if STM32_HAS_GPIOI
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202 | gpio_init(GPIOI, &gpio_default_config.PIData); |
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203 | #endif
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204 | #if STM32_HAS_GPIOJ
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205 | gpio_init(GPIOJ, &gpio_default_config.PJData); |
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206 | #endif
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207 | #if STM32_HAS_GPIOK
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208 | gpio_init(GPIOK, &gpio_default_config.PKData); |
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209 | #endif
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210 | } |
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211 | |||
212 | /*===========================================================================*/
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213 | /* Driver interrupt handlers. */
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214 | /*===========================================================================*/
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215 | |||
216 | /*===========================================================================*/
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217 | /* Driver exported functions. */
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218 | /*===========================================================================*/
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219 | |||
220 | /**
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221 | * @brief Early initialization code.
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222 | * @details GPIO ports and system clocks are initialized before everything
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223 | * else.
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224 | */
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225 | void __early_init(void) { |
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226 | |||
227 | stm32_gpio_init(); |
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228 | stm32_clock_init(); |
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229 | } |
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230 | |||
231 | #if HAL_USE_SDC || defined(__DOXYGEN__)
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232 | /**
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233 | * @brief SDC card detection.
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234 | */
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235 | bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
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236 | |||
237 | (void)sdcp;
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238 | /* TODO: Fill the implementation.*/
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239 | return true; |
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240 | } |
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241 | |||
242 | /**
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243 | * @brief SDC card write protection detection.
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244 | */
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245 | bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
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246 | |||
247 | (void)sdcp;
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248 | /* TODO: Fill the implementation.*/
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249 | return false; |
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250 | } |
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251 | #endif /* HAL_USE_SDC */ |
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252 | |||
253 | #if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
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254 | /**
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255 | * @brief MMC_SPI card detection.
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256 | */
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257 | bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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258 | |||
259 | (void)mmcp;
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260 | /* TODO: Fill the implementation.*/
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261 | return true; |
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262 | } |
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263 | |||
264 | /**
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265 | * @brief MMC_SPI card write protection detection.
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266 | */
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267 | bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
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268 | |||
269 | (void)mmcp;
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270 | /* TODO: Fill the implementation.*/
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271 | return false; |
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272 | } |
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273 | #endif
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274 | |||
275 | /**
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276 | * @brief Board-specific initialization code.
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277 | * @todo Add your board-specific code, if any.
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278 | */
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279 | void boardInit(void) { |
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280 | |||
281 | } |