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amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / ethernetlib / src / stm32_eth.c @ 367c0652

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/**
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  ******************************************************************************
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  * @file    stm32_eth.c
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  * @author  MCD Application Team
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  * @version V1.0.0
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  * @date    06/19/2009
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  * @brief   This file provides all the ETH firmware functions.
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  ******************************************************************************
9
  * @copy
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  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
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  */ 
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/* Includes ------------------------------------------------------------------*/
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#include "stm32_eth.h"
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#include "stm32f4xx_rcc.h"
24

    
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/** @addtogroup STM32_ETH_Driver
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  * @brief ETH driver modules
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  * @{
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  */
29

    
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/** @defgroup ETH_Private_TypesDefinitions
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  * @{
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  */ 
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/**
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  * @}
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  */ 
36

    
37

    
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/** @defgroup ETH_Private_Defines
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  * @{
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  */ 
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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ETH_DMADESCTypeDef  *DMATxDescToSet;
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ETH_DMADESCTypeDef  *DMARxDescToGet;
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ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
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ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
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/* ETHERNET MAC address offsets */
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#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
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#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
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/* ETHERNET MACMIIAR register Mask */
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#define MACMIIAR_CR_Mask    ((uint32_t)0xFFFFFFE3) 
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/* ETHERNET MACCR register Mask */
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#define MACCR_CLEAR_Mask    ((uint32_t)0xFF20810F)  
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/* ETHERNET MACFCR register Mask */
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#define MACFCR_CLEAR_Mask   ((uint32_t)0x0000FF41)
56
/* ETHERNET DMAOMR register Mask */
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#define DMAOMR_CLEAR_Mask   ((uint32_t)0xF8DE3F23)
58
/* ETHERNET Remote Wake-up frame register length */
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#define ETH_WakeupRegisterLength      8
60
/* ETHERNET Missed frames counter Shift */
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#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17
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/* ETHERNET DMA Tx descriptors Collision Count Shift */
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#define  ETH_DMATxDesc_CollisionCountShift        3
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/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
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#define  ETH_DMATxDesc_BufferSize2Shift           16
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/* ETHERNET DMA Rx descriptors Frame Length Shift */
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#define  ETH_DMARxDesc_FrameLengthShift           16
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/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
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#define  ETH_DMARxDesc_Buffer2SizeShift           16
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/* ETHERNET errors */
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#define  ETH_ERROR              ((uint32_t)0)
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#define  ETH_SUCCESS            ((uint32_t)1)
73
/**
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  * @}
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  */
76

    
77
/** @defgroup ETH_Private_Macros
78
  * @{
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  */ 
80
/**
81
  * @}
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  */
83

    
84
/** @defgroup ETH_Private_Variables
85
  * @{
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  */ 
87
/**
88
  * @}
89
  */
90

    
91
/** @defgroup ETH_Private_FunctionPrototypes
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  * @{
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  */ 
94
/**
95
  * @}
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  */
97

    
98
/** @defgroup ETH_Private_Functions
99
  * @{
100
  */
101

    
102
/**
103
  * @brief  Deinitializes the ETHERNET peripheral registers to their
104
  *   default reset values.
105
  * @param  None 
106
  * @retval : None
107
  */
108
void ETH_DeInit(void)
109
{
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  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
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  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
112
}
113

    
114
/**
115
  * @brief  Initializes the ETHERNET peripheral according to the specified
116
  *   parameters in the ETH_InitStruct .
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  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
118
  *   that contains the configuration information for the
119
  *   specified ETHERNET peripheral.
120
  * @param PHYAddress: external PHY address                    
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  * @retval : ETH_ERROR: Ethernet initialization failed
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  *   ETH_SUCCESS: Ethernet successfully initialized                 
123
  */
124
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
125
{
126
  uint32_t RegValue = 0, tmpreg = 0;
127
  __IO uint32_t i = 0;
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  RCC_ClocksTypeDef  rcc_clocks;
129
  uint32_t hclk = 120000000;
130
  __IO uint32_t timeout = 0;
131
  /* Check the parameters */
132
  /* MAC --------------------------*/ 
133
  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
134
  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
135
  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
136
  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
137
  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
138
  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
139
  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
140
  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
141
  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
142
  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
143
  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
144
  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
145
  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
146
  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
147
  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
148
  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
149
  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
150
  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
151
  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
152
  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
153
  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  
154
  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
155
  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
156
  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
157
  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
158
  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
159
  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
160
  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
161
  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
162
  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
163
  /* DMA --------------------------*/
164
  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
165
  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
166
  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
167
  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
168
  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
169
  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
170
  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
171
  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
172
  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
173
  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
174
  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
175
  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
176
  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 
177
  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  
178
  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       
179
  /*-------------------------------- MAC Config ------------------------------*/   
180
  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
181
  /* Get the ETHERNET MACMIIAR value */
182
  tmpreg = ETH->MACMIIAR;
183
  /* Clear CSR Clock Range CR[2:0] bits */
184
  tmpreg &= MACMIIAR_CR_Mask;
185
  /* Get hclk frequency value */
186
  RCC_GetClocksFreq(&rcc_clocks);
187
  hclk = rcc_clocks.HCLK_Frequency;
188
  /* Set CR bits depending on hclk value */
189
  if((hclk >= 20000000)&&(hclk < 35000000))
190
  {
191
    /* CSR Clock Range between 20-35 MHz */
192
    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
193
  }
194
  else if((hclk >= 35000000)&&(hclk < 60000000))
195
  {
196
    /* CSR Clock Range between 35-60 MHz */ 
197
    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;    
198
  }  
199
  else if((hclk >= 60000000)&&(hclk <= 100000000)) 
200
  {
201
    /* CSR Clock Range between 60-100 MHz */   
202
    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;    
203
  }
204
  else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */
205
  {
206
    /* CSR Clock Range between 100-120 MHz */   
207
    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;    
208
  }
209
  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
210
  ETH->MACMIIAR = (uint32_t)tmpreg;  
211
  /*-------------------- PHY initialization and configuration ----------------*/
212
  /* Put the PHY in reset mode */
213
  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
214
  {
215
    /* Return ERROR in case of write timeout */
216
    return ETH_ERROR;
217
  }
218
  
219
  /* Delay to assure PHY reset */
220
  for(i = PHY_ResetDelay; i != 0; i--)
221
  {
222
  }
223
  
224
  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
225
  {  
226
    /* We wait for linked satus... */
227
    do
228
    {
229
      timeout++;
230
    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
231
    /* Return ERROR in case of timeout */
232
    if(timeout == PHY_READ_TO)
233
    {
234
      return ETH_ERROR;
235
    }
236
    /* Reset Timeout counter */
237
    timeout = 0;
238
    
239
    /* Enable Auto-Negotiation */
240
    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
241
    {
242
      /* Return ERROR in case of write timeout */
243
      return ETH_ERROR;
244
    }
245
    
246
    /* Wait until the autonegotiation will be completed */
247
    do
248
    {
249
      timeout++;
250
    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));  
251
    /* Return ERROR in case of timeout */
252
    if(timeout == PHY_READ_TO)
253
    {
254
      return ETH_ERROR;
255
    }
256
    /* Reset Timeout counter */
257
    timeout = 0;
258
    
259
    /* Read the result of the autonegotiation */
260
    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
261
  
262
    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
263
    if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
264
    {
265
      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
266
      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
267
            
268
    }
269
    else
270
    {
271
      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
272
      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;           
273
    }
274
    /* Configure the MAC with the speed fixed by the autonegotiation process */
275
    if(RegValue & PHY_Speed_Status)
276
    {  
277
      /* Set Ethernet speed to 10M following the autonegotiation */    
278
      ETH_InitStruct->ETH_Speed = ETH_Speed_10M; 
279
    }
280
    else
281
    {   
282
      /* Set Ethernet speed to 100M following the autonegotiation */ 
283
      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;      
284
    }    
285
  }
286
  else
287
  {
288
    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
289
                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
290
    {
291
      /* Return ERROR in case of write timeout */
292
      return ETH_ERROR;
293
    }
294
    /* Delay to assure PHY configuration */
295
    for(i = PHY_ConfigDelay; i != 0; i--)
296
    {
297
    }
298
  }
299
  /*------------------------ ETHERNET MACCR Configuration --------------------*/
300
  /* Get the ETHERNET MACCR value */  
301
  tmpreg = ETH->MACCR;
302
  /* Clear WD, PCE, PS, TE and RE bits */
303
  tmpreg &= MACCR_CLEAR_Mask;
304
  /* Set the WD bit according to ETH_Watchdog value */
305
  /* Set the JD: bit according to ETH_Jabber value */
306
  /* Set the IFG bit according to ETH_InterFrameGap value */ 
307
  /* Set the DCRS bit according to ETH_CarrierSense value */  
308
  /* Set the FES bit according to ETH_Speed value */ 
309
  /* Set the DO bit according to ETH_ReceiveOwn value */ 
310
  /* Set the LM bit according to ETH_LoopbackMode value */ 
311
  /* Set the DM bit according to ETH_Mode value */ 
312
  /* Set the IPC bit according to ETH_ChecksumOffload value */                   
313
  /* Set the DR bit according to ETH_RetryTransmission value */ 
314
  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 
315
  /* Set the BL bit according to ETH_BackOffLimit value */ 
316
  /* Set the DC bit according to ETH_DeferralCheck value */                          
317
  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 
318
                  ETH_InitStruct->ETH_Jabber | 
319
                  ETH_InitStruct->ETH_InterFrameGap |
320
                  ETH_InitStruct->ETH_CarrierSense |
321
                  ETH_InitStruct->ETH_Speed | 
322
                  ETH_InitStruct->ETH_ReceiveOwn |
323
                  ETH_InitStruct->ETH_LoopbackMode |
324
                  ETH_InitStruct->ETH_Mode | 
325
                  ETH_InitStruct->ETH_ChecksumOffload |    
326
                  ETH_InitStruct->ETH_RetryTransmission | 
327
                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 
328
                  ETH_InitStruct->ETH_BackOffLimit | 
329
                  ETH_InitStruct->ETH_DeferralCheck);
330
  /* Write to ETHERNET MACCR */
331
  ETH->MACCR = (uint32_t)tmpreg;
332
  
333
  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
334
  /* Set the RA bit according to ETH_ReceiveAll value */
335
  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
336
  /* Set the PCF bit according to ETH_PassControlFrames value */
337
  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
338
  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
339
  /* Set the PR bit according to ETH_PromiscuousMode value */
340
  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
341
  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
342
  /* Write to ETHERNET MACFFR */  
343
  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 
344
                          ETH_InitStruct->ETH_SourceAddrFilter |
345
                          ETH_InitStruct->ETH_PassControlFrames |
346
                          ETH_InitStruct->ETH_BroadcastFramesReception | 
347
                          ETH_InitStruct->ETH_DestinationAddrFilter |
348
                          ETH_InitStruct->ETH_PromiscuousMode |
349
                          ETH_InitStruct->ETH_MulticastFramesFilter |
350
                          ETH_InitStruct->ETH_UnicastFramesFilter); 
351
  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
352
  /* Write to ETHERNET MACHTHR */
353
  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
354
  /* Write to ETHERNET MACHTLR */
355
  ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
356
  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
357
  /* Get the ETHERNET MACFCR value */  
358
  tmpreg = ETH->MACFCR;
359
  /* Clear xx bits */
360
  tmpreg &= MACFCR_CLEAR_Mask;
361
  
362
  /* Set the PT bit according to ETH_PauseTime value */
363
  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
364
  /* Set the PLT bit according to ETH_PauseLowThreshold value */
365
  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
366
  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
367
  /* Set the TFE bit according to ETH_TransmitFlowControl value */  
368
  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | 
369
                   ETH_InitStruct->ETH_ZeroQuantaPause |
370
                   ETH_InitStruct->ETH_PauseLowThreshold |
371
                   ETH_InitStruct->ETH_UnicastPauseFrameDetect | 
372
                   ETH_InitStruct->ETH_ReceiveFlowControl |
373
                   ETH_InitStruct->ETH_TransmitFlowControl); 
374
  /* Write to ETHERNET MACFCR */
375
  ETH->MACFCR = (uint32_t)tmpreg;
376
  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
377
  /* Set the ETV bit according to ETH_VLANTagComparison value */
378
  /* Set the VL bit according to ETH_VLANTagIdentifier value */  
379
  ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | 
380
                             ETH_InitStruct->ETH_VLANTagIdentifier); 
381
       
382
  /*-------------------------------- DMA Config ------------------------------*/
383
  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
384
  /* Get the ETHERNET DMAOMR value */  
385
  tmpreg = ETH->DMAOMR;
386
  /* Clear xx bits */
387
  tmpreg &= DMAOMR_CLEAR_Mask;
388
  
389
  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
390
  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
391
  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
392
  /* Set the TSF bit according to ETH_TransmitStoreForward value */
393
  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
394
  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
395
  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
396
  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
397
  /* Set the OSF bit according to ETH_SecondFrameOperate value */
398
  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | 
399
                  ETH_InitStruct->ETH_ReceiveStoreForward |
400
                  ETH_InitStruct->ETH_FlushReceivedFrame |
401
                  ETH_InitStruct->ETH_TransmitStoreForward | 
402
                  ETH_InitStruct->ETH_TransmitThresholdControl |
403
                  ETH_InitStruct->ETH_ForwardErrorFrames |
404
                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
405
                  ETH_InitStruct->ETH_ReceiveThresholdControl |                                   
406
                  ETH_InitStruct->ETH_SecondFrameOperate); 
407
  /* Write to ETHERNET DMAOMR */
408
  ETH->DMAOMR = (uint32_t)tmpreg;
409
  
410
  /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 
411
  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
412
  /* Set the FB bit according to ETH_FixedBurst value */
413
  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
414
  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
415
  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
416
  /* Set the PR and DA bits according to ETH_DMAArbitration value */         
417
  ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | 
418
                          ETH_InitStruct->ETH_FixedBurst |
419
                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
420
                          ETH_InitStruct->ETH_TxDMABurstLength | 
421
                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
422
                          ETH_InitStruct->ETH_DMAArbitration |
423
                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */  
424
  /* Return Ethernet configuration success */
425
  return ETH_SUCCESS;
426
}
427

    
428
/**
429
  * @brief  Fills each ETH_InitStruct member with its default value.
430
  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
431
  *   which will be initialized.
432
  * @retval : None
433
  */
434
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
435
{
436
  /* ETH_InitStruct members default value */
437
  /*------------------------   MAC   -----------------------------------*/     
438
  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;           
439
  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;                   
440
  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;                                                     
441
  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;                                                                                                                          
442
  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;                              
443
  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;                       
444
  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;               
445
  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;              
446
  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;                       
447
  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;                                                            
448
  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;                                                                                  
449
  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                         
450
  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;                                                                
451
  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;                                                                                                                  
452
  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;                                                               
453
  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;                                
454
  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;          
455
  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
456
  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;      
457
  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             
458
  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;      
459
  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;      
460
  ETH_InitStruct->ETH_HashTableHigh = 0x0;                
461
  ETH_InitStruct->ETH_HashTableLow = 0x0;                     
462
  ETH_InitStruct->ETH_PauseTime = 0x0;                 
463
  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;            
464
  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;         
465
  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;   
466
  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;        
467
  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;      
468
  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;          
469
  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;          
470
  /*------------------------   DMA   -----------------------------------*/  
471
  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; 
472
  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;       
473
  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;       
474
  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
475
  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;  
476
  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
477
  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; 
478
  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;   
479
  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
480
  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
481
  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
482
  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
483
  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
484
  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
485
  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
486
}
487

    
488
/**
489
  * @brief  Enables ENET MAC and DMA reception/transmission 
490
  * @param  None
491
  * @retval : None
492
  */
493
void ETH_Start(void)
494
{
495
  /* Enable transmit state machine of the MAC for transmission on the MII */  
496
  ETH_MACTransmissionCmd(ENABLE);
497
  /* Flush Transmit FIFO */
498
  ETH_FlushTransmitFIFO();
499
  /* Enable receive state machine of the MAC for reception from the MII */  
500
  ETH_MACReceptionCmd(ENABLE);
501
 
502
  /* Start DMA transmission */
503
  ETH_DMATransmissionCmd(ENABLE); 
504
  /* Start DMA reception */
505
  ETH_DMAReceptionCmd(ENABLE);   
506
}
507

    
508
/**
509
  * @brief  Transmits a packet, from application buffer, pointed by ppkt.
510
  * @param ppkt: pointer to application packet buffer to transmit.
511
  * @param FrameLength: Tx Packet size.
512
  * @retval : ETH_ERROR: in case of Tx desc owned by DMA
513
  *   ETH_SUCCESS: for correct transmission
514
  */
515
uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
516
{ 
517
  uint32_t offset = 0;
518
    
519
  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
520
  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
521
  {
522
    /* Return ERROR: OWN bit set */
523
    return ETH_ERROR;
524
  }
525
  
526
  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
527
  for(offset=0; offset<FrameLength; offset++)       
528
  {
529
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
530
  }
531
        
532
  /* Setting the Frame Length: bits[12:0] */
533
  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
534
  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
535
  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
536
  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
537
  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
538
  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
539
  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
540
  {
541
    /* Clear TBUS ETHERNET DMA flag */
542
    ETH->DMASR = ETH_DMASR_TBUS;
543
    /* Resume DMA transmission*/
544
    ETH->DMATPDR = 0;
545
  }
546
  
547
  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */  
548
  /* Chained Mode */
549
  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
550
  {     
551
    /* Selects the next DMA Tx descriptor list for next buffer to send */ 
552
    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);    
553
  }
554
  else /* Ring Mode */
555
  {  
556
    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
557
    {
558
      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
559
      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);      
560
    }
561
    else
562
    {  
563
      /* Selects the next DMA Tx descriptor list for next buffer to send */
564
      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
565
    }
566
  }
567
  /* Return SUCCESS */
568
  return ETH_SUCCESS;   
569
}
570

    
571
/**
572
  * @brief  Receives a packet and copies it to memory pointed by ppkt.
573
  * @param  ppkt: pointer to application packet receive buffer.
574
  * @retval : ETH_ERROR: if there is error in reception
575
  *   framelength: received packet size if packet reception is correct
576
  */
577
uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
578
{ 
579
  uint32_t offset = 0, framelength = 0;
580
  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
581
  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
582
  {
583
    /* Return error: OWN bit set */
584
    return ETH_ERROR; 
585
  }
586
  
587
  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && 
588
     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&  
589
     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))  
590
  {      
591
    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
592
    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
593
    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
594
    for(offset=0; offset<framelength; offset++)       
595
    {
596
      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
597
    }
598
  }
599
  else
600
  {
601
    /* Return ERROR */
602
    framelength = ETH_ERROR;
603
  }
604
  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
605
  DMARxDescToGet->Status = ETH_DMARxDesc_OWN; 
606
 
607
  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
608
  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)  
609
  {
610
    /* Clear RBUS ETHERNET DMA flag */
611
    ETH->DMASR = ETH_DMASR_RBUS;
612
    /* Resume DMA reception */
613
    ETH->DMARPDR = 0;
614
  }
615
  
616
  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */      
617
  /* Chained Mode */
618
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
619
  {     
620
    /* Selects the next DMA Rx descriptor list for next buffer to read */ 
621
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);    
622
  }
623
  else /* Ring Mode */
624
  {   
625
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
626
    {
627
      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
628
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);      
629
    }
630
    else
631
    { 
632
      /* Selects the next DMA Rx descriptor list for next buffer to read */
633
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
634
    }
635
  }
636
  
637
  /* Return Frame Length/ERROR */
638
  return (framelength);  
639
}
640

    
641
/**
642
  * @brief  Get the size of received the received packet.
643
  * @param  None
644
  * @retval : framelength: received packet size 
645
  */
646
uint32_t ETH_GetRxPktSize(void)
647
{
648
  uint32_t frameLength = 0;
649
  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
650
     ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
651
     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
652
     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
653
  {
654
    /* Get the size of the packet: including 4 bytes of the CRC */
655
    frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
656
  }
657
 
658
 /* Return Frame Length */ 
659
 return frameLength;
660
}
661

    
662
/**
663
  * @brief  Drop a Received packet (too small packet, etc...)
664
  * @param  None
665
  * @retval : None
666
  */
667
void ETH_DropRxPkt(void)
668
{
669
  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
670
  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;  
671
  /* Chained Mode */
672
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
673
  {
674
    /* Selects the next DMA Rx descriptor list for next buffer read */
675
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
676
  }
677
  else /* Ring Mode */
678
  {
679
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
680
    {
681
      /* Selects the next DMA Rx descriptor list for next buffer read: this will
682
         be the first Rx descriptor in this case */
683
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
684
    }
685
    else
686
    {
687
      /* Selects the next DMA Rx descriptor list for next buffer read */
688
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
689
    }
690
  }
691
}
692

    
693
/*---------------------------------  PHY  ------------------------------------*/
694
/**
695
  * @brief  Read a PHY register
696
  * @param PHYAddress: PHY device address, is the index of one of supported
697
  *   32 PHY devices. 
698
  *   This parameter can be one of the following values: 0,..,31                  
699
  * @param PHYReg: PHY register address, is the index of one of the 32
700
  *   PHY register. 
701
  *   This parameter can be one of the following values: 
702
  * @arg PHY_BCR    : Tranceiver Basic Control Register 
703
  * @arg PHY_BSR    : Tranceiver Basic Status Register 
704
  * @arg PHY_SR     : Tranceiver Status Register    
705
  * @arg More PHY register could be read depending on the used PHY
706
  * @retval : ETH_ERROR: in case of timeout
707
  *   MAC MIIDR register value: Data read from the selected PHY register (correct read )
708
  */
709
uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
710
{
711
  uint32_t tmpreg = 0;     
712
__IO uint32_t timeout = 0;
713
  /* Check the parameters */
714
  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
715
  assert_param(IS_ETH_PHY_REG(PHYReg));
716
  
717
  /* Get the ETHERNET MACMIIAR value */
718
  tmpreg = ETH->MACMIIAR;
719
  /* Keep only the CSR Clock Range CR[2:0] bits value */
720
  tmpreg &= ~MACMIIAR_CR_Mask;
721
  /* Prepare the MII address register value */
722
  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
723
  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
724
  tmpreg &= ~ETH_MACMIIAR_MW;                              /* Set the read mode */
725
  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
726
  /* Write the result value into the MII Address register */
727
  ETH->MACMIIAR = tmpreg;
728
  /* Check for the Busy flag */
729
  do
730
  {
731
    timeout++;
732
    tmpreg = ETH->MACMIIAR;
733
  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
734
  /* Return ERROR in case of timeout */
735
  if(timeout == PHY_READ_TO)
736
  {
737
    return (uint16_t)ETH_ERROR;
738
  }
739
  
740
  /* Return data register value */
741
  return (uint16_t)(ETH->MACMIIDR);
742
}
743

    
744
/**
745
  * @brief  Write to a PHY register
746
  * @param PHYAddress: PHY device address, is the index of one of supported
747
  *   32 PHY devices. 
748
  *   This parameter can be one of the following values: 0,..,31
749
  * @param PHYReg: PHY register address, is the index of one of the 32
750
  *   PHY register. 
751
  *   This parameter can be one of the following values: 
752
  * @arg PHY_BCR    : Tranceiver Control Register  
753
  * @arg More PHY register could be written depending on the used PHY
754
  * @param PHYValue: the value to write
755
  * @retval : ETH_ERROR: in case of timeout
756
  *   ETH_SUCCESS: for correct write
757
  */
758
uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
759
{
760
  uint32_t tmpreg = 0;     
761
  __IO uint32_t timeout = 0;
762
  /* Check the parameters */
763
  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
764
  assert_param(IS_ETH_PHY_REG(PHYReg));
765
  
766
  /* Get the ETHERNET MACMIIAR value */
767
  tmpreg = ETH->MACMIIAR;
768
  /* Keep only the CSR Clock Range CR[2:0] bits value */
769
  tmpreg &= ~MACMIIAR_CR_Mask;
770
  /* Prepare the MII register address value */
771
  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
772
  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
773
  tmpreg |= ETH_MACMIIAR_MW;                               /* Set the write mode */
774
  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
775
  /* Give the value to the MII data register */
776
  ETH->MACMIIDR = PHYValue;
777
  /* Write the result value into the MII Address register */
778
  ETH->MACMIIAR = tmpreg;
779
  /* Check for the Busy flag */
780
  do
781
  {
782
    timeout++;
783
    tmpreg = ETH->MACMIIAR;
784
  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
785
  /* Return ERROR in case of timeout */
786
  if(timeout == PHY_WRITE_TO)
787
  {
788
    return ETH_ERROR;
789
  }
790
  
791
  /* Return SUCCESS */
792
  return ETH_SUCCESS;  
793
}
794

    
795
/**
796
  * @brief  Enables or disables the PHY loopBack mode.
797
  * @param PHYAddress: PHY device address, is the index of one of supported
798
  *   32 PHY devices. 
799
  *   This parameter can be one of the following values:                   
800
  * @param NewState: new state of the PHY loopBack mode.
801
  *   This parameter can be: ENABLE or DISABLE.    
802
  *   Note: Don't be confused with ETH_MACLoopBackCmd function
803
  *   which enables internal loopback at MII level
804
  * @retval : ETH_ERROR: in case of bad PHY configuration
805
  *   ETH_SUCCESS: for correct PHY configuration
806
  */
807
uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
808
{
809
  uint16_t tmpreg = 0;
810
  /* Check the parameters */
811
  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
812
  assert_param(IS_FUNCTIONAL_STATE(NewState));
813
    
814
  /* Get the PHY configuration to update it */
815
  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); 
816
  
817
  if (NewState != DISABLE)
818
  {
819
    /* Enable the PHY loopback mode */
820
    tmpreg |= PHY_Loopback;  
821
  }
822
  else
823
  {
824
    /* Disable the PHY loopback mode: normal mode */
825
    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
826
  }
827
  /* Update the PHY control register with the new configuration */
828
  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
829
  {
830
    return ETH_SUCCESS;
831
  }
832
  else
833
  {
834
    /* Return SUCCESS */
835
    return ETH_ERROR; 
836
  }   
837
}
838

    
839
/*---------------------------------  MAC  ------------------------------------*/
840
/**
841
  * @brief  Enables or disables the MAC transmission.
842
  * @param NewState: new state of the MAC transmission.
843
  *   This parameter can be: ENABLE or DISABLE.
844
  * @retval : None
845
  */
846
void ETH_MACTransmissionCmd(FunctionalState NewState)
847
{ 
848
  /* Check the parameters */
849
  assert_param(IS_FUNCTIONAL_STATE(NewState));
850
  
851
  if (NewState != DISABLE)
852
  {
853
    /* Enable the MAC transmission */
854
    ETH->MACCR |= ETH_MACCR_TE;  
855
  }
856
  else
857
  {
858
    /* Disable the MAC transmission */
859
    ETH->MACCR &= ~ETH_MACCR_TE;
860
  }
861
}
862

    
863
/**
864
  * @brief  Enables or disables the MAC reception.
865
  * @param NewState: new state of the MAC reception.
866
  *   This parameter can be: ENABLE or DISABLE.
867
  * @retval : None
868
  */
869
void ETH_MACReceptionCmd(FunctionalState NewState)
870
{ 
871
  /* Check the parameters */
872
  assert_param(IS_FUNCTIONAL_STATE(NewState));
873
  
874
  if (NewState != DISABLE)
875
  {
876
    /* Enable the MAC reception */
877
    ETH->MACCR |= ETH_MACCR_RE;  
878
  }
879
  else
880
  {
881
    /* Disable the MAC reception */
882
    ETH->MACCR &= ~ETH_MACCR_RE;
883
  }
884
}
885

    
886
/**
887
  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
888
  * @param  None
889
  * @retval : The new state of flow control busy status bit (SET or RESET).
890
  */
891
FlagStatus ETH_GetFlowControlBusyStatus(void)
892
{
893
  FlagStatus bitstatus = RESET;
894
  /* The Flow Control register should not be written to until this bit is cleared */
895
  if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
896
  {
897
    bitstatus = SET;
898
  }
899
  else
900
  {
901
    bitstatus = RESET;
902
  }
903
  return bitstatus;
904
}
905

    
906
/**
907
  * @brief  Initiate a Pause Control Frame (Full-duplex only).
908
  * @param  None
909
  * @retval : None
910
  */
911
void ETH_InitiatePauseControlFrame(void)  
912
{ 
913
  /* When Set In full duplex MAC initiates pause control frame */
914
  ETH->MACFCR |= ETH_MACFCR_FCBBPA;  
915
}
916

    
917
/**
918
  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).
919
  * @param NewState: new state of the MAC BackPressure operation activation.
920
  *   This parameter can be: ENABLE or DISABLE.
921
  * @retval : None
922
  */
923
void ETH_BackPressureActivationCmd(FunctionalState NewState)   
924
{ 
925
  /* Check the parameters */
926
  assert_param(IS_FUNCTIONAL_STATE(NewState));
927
    
928
  if (NewState != DISABLE)
929
  {
930
    /* Activate the MAC BackPressure operation */
931
    /* In Half duplex: during backpressure, when the MAC receives a new frame,
932
    the transmitter starts sending a JAM pattern resulting in a collision */
933
    ETH->MACFCR |= ETH_MACFCR_FCBBPA; 
934
  }
935
  else
936
  {
937
    /* Desactivate the MAC BackPressure operation */
938
    ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; 
939
  } 
940
}
941

    
942
/**
943
  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
944
  * @param ETH_MAC_FLAG: specifies the flag to check.
945
  *   This parameter can be one of the following values:
946
  * @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
947
  * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
948
  * @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
949
  * @arg ETH_MAC_FLAG_MMC  : MMC flag  
950
  * @arg ETH_MAC_FLAG_PMT  : PMT flag  
951
  * @retval : The new state of ETHERNET MAC flag (SET or RESET).
952
  */
953
FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
954
{
955
  FlagStatus bitstatus = RESET;
956
  /* Check the parameters */
957
  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); 
958
  if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
959
  {
960
    bitstatus = SET;
961
  }
962
  else
963
  {
964
    bitstatus = RESET;
965
  }
966
  return bitstatus;
967
}
968

    
969
/**
970
  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.
971
  * @param ETH_MAC_IT: specifies the interrupt source to check.
972
  *   This parameter can be one of the following values:
973
  * @arg ETH_MAC_IT_TST   : Time stamp trigger interrupt  
974
  * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt 
975
  * @arg ETH_MAC_IT_MMCR : MMC receive interrupt  
976
  * @arg ETH_MAC_IT_MMC  : MMC interrupt 
977
  * @arg ETH_MAC_IT_PMT  : PMT interrupt 
978
  * @retval : The new state of ETHERNET MAC interrupt (SET or RESET).
979
  */
980
ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
981
{
982
  ITStatus bitstatus = RESET;
983
  /* Check the parameters */
984
  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); 
985
  if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
986
  {
987
    bitstatus = SET;
988
  }
989
  else
990
  {
991
    bitstatus = RESET;
992
  }
993
  return bitstatus;
994
}
995

    
996
/**
997
  * @brief  Enables or disables the specified ETHERNET MAC interrupts.
998
  * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
999
  *   enabled or disabled.
1000
  *   This parameter can be any combination of the following values:
1001
  * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
1002
  * @arg ETH_MAC_IT_PMT : PMT interrupt 
1003
  * @param NewState: new state of the specified ETHERNET MAC interrupts.
1004
  *   This parameter can be: ENABLE or DISABLE.
1005
  * @retval : None
1006
  */
1007
void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
1008
{
1009
  /* Check the parameters */
1010
  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
1011
  assert_param(IS_FUNCTIONAL_STATE(NewState));  
1012
  
1013
  if (NewState != DISABLE)
1014
  {
1015
    /* Enable the selected ETHERNET MAC interrupts */
1016
    ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
1017
  }
1018
  else
1019
  {
1020
    /* Disable the selected ETHERNET MAC interrupts */
1021
    ETH->MACIMR |= ETH_MAC_IT;
1022
  }
1023
}
1024

    
1025
/**
1026
  * @brief  Configures the selected MAC address.
1027
  * @param MacAddr: The MAC addres to configure.
1028
  *   This parameter can be one of the following values:
1029
  * @arg ETH_MAC_Address0 : MAC Address0 
1030
  * @arg ETH_MAC_Address1 : MAC Address1 
1031
  * @arg ETH_MAC_Address2 : MAC Address2
1032
  * @arg ETH_MAC_Address3 : MAC Address3
1033
  * @param Addr: Pointer on MAC address buffer data (6 bytes).
1034
  * @retval : None
1035
  */
1036
void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
1037
{
1038
  uint32_t tmpreg;
1039
  /* Check the parameters */
1040
  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1041
  
1042
  /* Calculate the selectecd MAC address high register */
1043
  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
1044
  /* Load the selectecd MAC address high register */
1045
  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
1046
  /* Calculate the selectecd MAC address low register */
1047
  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
1048
 
1049
  /* Load the selectecd MAC address low register */
1050
  (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
1051
}
1052

    
1053
/**
1054
  * @brief  Get the selected MAC address.
1055
  * @param MacAddr: The MAC addres to return.
1056
  *   This parameter can be one of the following values:
1057
  * @arg ETH_MAC_Address0 : MAC Address0 
1058
  * @arg ETH_MAC_Address1 : MAC Address1 
1059
  * @arg ETH_MAC_Address2 : MAC Address2
1060
  * @arg ETH_MAC_Address3 : MAC Address3
1061
  * @param Addr: Pointer on MAC address buffer data (6 bytes).
1062
  * @retval : None
1063
  */
1064
void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
1065
{
1066
  uint32_t tmpreg;
1067
  /* Check the parameters */
1068
  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1069
  
1070
  /* Get the selectecd MAC address high register */
1071
  tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr));
1072
 
1073
  /* Calculate the selectecd MAC address buffer */
1074
  Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
1075
  Addr[4] = (tmpreg & (uint8_t)0xFF);
1076
  /* Load the selectecd MAC address low register */
1077
  tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr));
1078
  /* Calculate the selectecd MAC address buffer */
1079
  Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
1080
  Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
1081
  Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
1082
  Addr[0] = (tmpreg & (uint8_t)0xFF);
1083
}
1084

    
1085
/**
1086
  * @brief  Enables or disables the Address filter module uses the specified
1087
  *   ETHERNET MAC address for perfect filtering 
1088
  * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
1089
  *   This parameter can be one of the following values: 
1090
  * @arg ETH_MAC_Address1 : MAC Address1 
1091
  * @arg ETH_MAC_Address2 : MAC Address2
1092
  * @arg ETH_MAC_Address3 : MAC Address3
1093
  * @param NewState: new state of the specified ETHERNET MAC address use.
1094
  *   This parameter can be: ENABLE or DISABLE.
1095
  * @retval : None
1096
  */
1097
void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
1098
{
1099
  /* Check the parameters */
1100
  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1101
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1102
    
1103
  if (NewState != DISABLE)
1104
  {
1105
    /* Enable the selected ETHERNET MAC address for perfect filtering */
1106
    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
1107
  }
1108
  else
1109
  {
1110
    /* Disable the selected ETHERNET MAC address for perfect filtering */
1111
    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
1112
  }
1113
}
1114

    
1115
/**
1116
  * @brief  Set the filter type for the specified ETHERNET MAC address 
1117
  * @param MacAddr: specifies the ETHERNET MAC address 
1118
  *   This parameter can be one of the following values: 
1119
  * @arg ETH_MAC_Address1 : MAC Address1 
1120
  * @arg ETH_MAC_Address2 : MAC Address2
1121
  * @arg ETH_MAC_Address3 : MAC Address3
1122
  * @param Filter: specifies the used frame received field for comparaison 
1123
  *   This parameter can be one of the following values: 
1124
  * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare 
1125
  *   with the SA fields of the received frame.
1126
  * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare 
1127
  *   with the DA fields of the received frame.
1128
  * @retval : None
1129
  */
1130
void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
1131
{
1132
  /* Check the parameters */
1133
  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1134
  assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
1135
  
1136
  if (Filter != ETH_MAC_AddressFilter_DA)
1137
  {
1138
    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
1139
       received frame. */
1140
    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
1141
  }
1142
  else
1143
  {
1144
    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
1145
       received frame. */
1146
    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
1147
  }
1148
}
1149

    
1150
/**
1151
  * @brief  Set the filter type for the specified ETHERNET MAC address 
1152
  * @param MacAddr: specifies the ETHERNET MAC address 
1153
  *   This parameter can be one of the following values: 
1154
  * @arg ETH_MAC_Address1 : MAC Address1 
1155
  * @arg ETH_MAC_Address2 : MAC Address2
1156
  * @arg ETH_MAC_Address3 : MAC Address3
1157
  * @param MaskByte: specifies the used address bytes for comparaison 
1158
  *   This parameter can be any combination of the following values: 
1159
  * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
1160
  * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
1161
  * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
1162
  * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
1163
  * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
1164
  * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
1165
  * @retval : None
1166
  */
1167
void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
1168
{
1169
  /* Check the parameters */
1170
  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1171
  assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
1172
  
1173
  /* Clear MBC bits in the selected MAC address  high register */
1174
  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
1175
  /* Set the selected Filetr mask bytes */
1176
  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
1177
}
1178
/*------------------------  DMA Tx/Rx Desciptors -----------------------------*/
1179

    
1180
/**
1181
  * @brief  Initializes the DMA Tx descriptors in chain mode.
1182
  * @param DMATxDescTab: Pointer on the first Tx desc list 
1183
  * @param TxBuff: Pointer on the first TxBuffer list
1184
  * @param TxBuffCount: Number of the used Tx desc in the list
1185
  * @retval : None
1186
  */
1187
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
1188
{
1189
  uint32_t i = 0;
1190
  ETH_DMADESCTypeDef *DMATxDesc;
1191
  
1192
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1193
  DMATxDescToSet = DMATxDescTab;
1194
  /* Fill each DMATxDesc descriptor with the right values */   
1195
  for(i=0; i < TxBuffCount; i++)
1196
  {
1197
    /* Get the pointer on the ith member of the Tx Desc list */
1198
    DMATxDesc = DMATxDescTab + i;
1199
    /* Set Second Address Chained bit */
1200
    DMATxDesc->Status = ETH_DMATxDesc_TCH;  
1201
       
1202
    /* Set Buffer1 address pointer */
1203
    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
1204
    
1205
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1206
    if(i < (TxBuffCount-1))
1207
    {
1208
      /* Set next descriptor address register with next descriptor base address */
1209
      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
1210
    }
1211
    else
1212
    {
1213
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
1214
      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
1215
    }
1216
  }
1217
   
1218
  /* Set Transmit Desciptor List Address Register */
1219
  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
1220
}
1221

    
1222
/**
1223
  * @brief  Initializes the DMA Tx descriptors in ring mode.
1224
  * @param DMATxDescTab: Pointer on the first Tx desc list 
1225
  * @param TxBuff1: Pointer on the first TxBuffer1 list 
1226
  * @param TxBuff2: Pointer on the first TxBuffer2 list
1227
  * @param TxBuffCount: Number of the used Tx desc in the list
1228
  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
1229
  *   for the number of Words to skip between two unchained descriptors.  
1230
  * @retval : None
1231
  */
1232
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
1233
{
1234
  uint32_t i = 0;
1235
  ETH_DMADESCTypeDef *DMATxDesc;
1236
 
1237
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1238
  DMATxDescToSet = DMATxDescTab;
1239
  /* Fill each DMATxDesc descriptor with the right values */  
1240
  for(i=0; i < TxBuffCount; i++)
1241
  {
1242
    /* Get the pointer on the ith member of the Tx Desc list */
1243
    DMATxDesc = DMATxDescTab + i;
1244
    /* Set Buffer1 address pointer */
1245
    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
1246
    
1247
    /* Set Buffer2 address pointer */
1248
    DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
1249
    
1250
    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
1251
       address of the list, creating a Desciptor Ring */
1252
    if(i == (TxBuffCount-1))
1253
    {
1254
      /* Set Transmit End of Ring bit */
1255
      DMATxDesc->Status = ETH_DMATxDesc_TER;
1256
    }
1257
  }
1258
   
1259
  /* Set Transmit Desciptor List Address Register */
1260
  ETH->DMATDLAR =  (uint32_t) DMATxDescTab;
1261
}
1262

    
1263
/**
1264
  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1265
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1266
  * @param ETH_DMATxDescFlag: specifies the flag to check.
1267
  *   This parameter can be one of the following values:
1268
  * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
1269
  * @arg ETH_DMATxDesc_IC  : Interrupt on completetion
1270
  * @arg ETH_DMATxDesc_LS  : Last Segment
1271
  * @arg ETH_DMATxDesc_FS  : First Segment
1272
  * @arg ETH_DMATxDesc_DC  : Disable CRC
1273
  * @arg ETH_DMATxDesc_DP  : Disable Pad
1274
  * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
1275
  * @arg ETH_DMATxDesc_TER : Transmit End of Ring
1276
  * @arg ETH_DMATxDesc_TCH : Second Address Chained
1277
  * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
1278
  * @arg ETH_DMATxDesc_IHE : IP Header Error
1279
  * @arg ETH_DMATxDesc_ES  : Error summary
1280
  * @arg ETH_DMATxDesc_JT  : Jabber Timeout
1281
  * @arg ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
1282
  * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
1283
  * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
1284
  * @arg ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
1285
  * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
1286
  * @arg ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
1287
  * @arg ETH_DMATxDesc_VF  : VLAN Frame
1288
  * @arg ETH_DMATxDesc_CC  : Collision Count 
1289
  * @arg ETH_DMATxDesc_ED  : Excessive Deferral
1290
  * @arg ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
1291
  * @arg ETH_DMATxDesc_DB  : Deferred Bit
1292
  * @retval : The new state of ETH_DMATxDescFlag (SET or RESET).
1293
  */
1294
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
1295
{
1296
  FlagStatus bitstatus = RESET;
1297
  /* Check the parameters */
1298
  assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
1299
  
1300
  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
1301
  {
1302
    bitstatus = SET;
1303
  }
1304
  else
1305
  {
1306
    bitstatus = RESET;
1307
  }
1308
  return bitstatus;
1309
}
1310

    
1311
/**
1312
  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
1313
  * @param DMATxDesc: pointer on a DMA Tx descriptor                     
1314
  * @retval : The Transmit descriptor collision counter value.
1315
  */
1316
uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
1317
{
1318
  /* Return the Receive descriptor frame length */
1319
  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
1320
}
1321

    
1322
/**
1323
  * @brief  Set the specified DMA Tx Desc Own bit.
1324
  * @param DMATxDesc: Pointer on a Tx desc
1325
  * @retval : None
1326
  */
1327
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
1328
{
1329
  /* Set the DMA Tx Desc Own bit */
1330
  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
1331
}
1332

    
1333
/**
1334
  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
1335
  * @param DMATxDesc: Pointer on a Tx desc
1336
  * @param NewState: new state of the DMA Tx Desc transmit interrupt.
1337
  *   This parameter can be: ENABLE or DISABLE.                   
1338
  * @retval : None
1339
  */
1340
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1341
{
1342
  /* Check the parameters */
1343
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1344
  
1345
  if (NewState != DISABLE)
1346
  {
1347
    /* Enable the DMA Tx Desc Transmit interrupt */
1348
    DMATxDesc->Status |= ETH_DMATxDesc_IC;
1349
  }
1350
  else
1351
  {
1352
    /* Disable the DMA Tx Desc Transmit interrupt */
1353
    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
1354
  }
1355
}
1356

    
1357
/**
1358
  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
1359
  * @param DMATxDesc: Pointer on a Tx desc
1360
  * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
1361
  *   This parameter can be one of the following values:
1362
  * @arg ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment 
1363
  * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment                   
1364
  * @retval : None
1365
  */
1366
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
1367
{
1368
  /* Check the parameters */
1369
  assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
1370
  
1371
  /* Selects the DMA Tx Desc Frame segment */
1372
  DMATxDesc->Status |= DMATxDesc_FrameSegment;
1373
}
1374

    
1375
/**
1376
  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1377
  * @param DMATxDesc: pointer on a DMA Tx descriptor 
1378
  * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
1379
  *   This parameter can be one of the following values:
1380
  * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
1381
  * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
1382
  * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1383
  * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
1384
  * @retval : None
1385
  */
1386
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
1387
{
1388
  /* Check the parameters */
1389
  assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
1390
  
1391
  /* Set the selected DMA Tx desc checksum insertion control */
1392
  DMATxDesc->Status |= DMATxDesc_Checksum;
1393
}
1394

    
1395
/**
1396
  * @brief  Enables or disables the DMA Tx Desc CRC.
1397
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1398
  * @param NewState: new state of the specified DMA Tx Desc CRC.
1399
  *   This parameter can be: ENABLE or DISABLE.
1400
  * @retval : None
1401
  */
1402
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1403
{
1404
  /* Check the parameters */
1405
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1406
  
1407
  if (NewState != DISABLE)
1408
  {
1409
    /* Enable the selected DMA Tx Desc CRC */
1410
    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
1411
  }
1412
  else
1413
  {
1414
    /* Disable the selected DMA Tx Desc CRC */
1415
    DMATxDesc->Status |= ETH_DMATxDesc_DC; 
1416
  }
1417
}
1418

    
1419
/**
1420
  * @brief  Enables or disables the DMA Tx Desc end of ring.
1421
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1422
  * @param NewState: new state of the specified DMA Tx Desc end of ring.
1423
  *   This parameter can be: ENABLE or DISABLE.
1424
  * @retval : None
1425
  */
1426
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1427
{
1428
  /* Check the parameters */
1429
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1430
  
1431
  if (NewState != DISABLE)
1432
  {
1433
    /* Enable the selected DMA Tx Desc end of ring */
1434
    DMATxDesc->Status |= ETH_DMATxDesc_TER;  
1435
  }
1436
  else
1437
  {
1438
    /* Disable the selected DMA Tx Desc end of ring */
1439
    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); 
1440
  }
1441
}
1442

    
1443
/**
1444
  * @brief  Enables or disables the DMA Tx Desc second address chained.
1445
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1446
  * @param NewState: new state of the specified DMA Tx Desc second address chained.
1447
  *   This parameter can be: ENABLE or DISABLE.
1448
  * @retval : None
1449
  */
1450
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1451
{
1452
  /* Check the parameters */
1453
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1454
  
1455
  if (NewState != DISABLE)
1456
  {
1457
    /* Enable the selected DMA Tx Desc second address chained */
1458
    DMATxDesc->Status |= ETH_DMATxDesc_TCH;  
1459
  }
1460
  else
1461
  {
1462
    /* Disable the selected DMA Tx Desc second address chained */
1463
    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); 
1464
  }
1465
}
1466

    
1467
/**
1468
  * @brief  Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1469
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1470
  * @param NewState: new state of the specified DMA Tx Desc padding for
1471
  *   frame shorter than 64 bytes.
1472
  *   This parameter can be: ENABLE or DISABLE.
1473
  * @retval : None
1474
  */
1475
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1476
{
1477
  /* Check the parameters */
1478
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1479
  
1480
  if (NewState != DISABLE)
1481
  {
1482
    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
1483
    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
1484
  }
1485
  else
1486
  {
1487
    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
1488
    DMATxDesc->Status |= ETH_DMATxDesc_DP; 
1489
  }
1490
}
1491

    
1492
/**
1493
  * @brief  Enables or disables the DMA Tx Desc time stamp.
1494
  * @param DMATxDesc: pointer on a DMA Tx descriptor
1495
  * @param NewState: new state of the specified DMA Tx Desc time stamp.
1496
  *   This parameter can be: ENABLE or DISABLE.
1497
  * @retval : None
1498
  */
1499
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1500
{
1501
  /* Check the parameters */
1502
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1503
  
1504
  if (NewState != DISABLE)
1505
  {
1506
    /* Enable the selected DMA Tx Desc time stamp */
1507
    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;  
1508
  }
1509
  else
1510
  {
1511
    /* Disable the selected DMA Tx Desc time stamp */
1512
    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); 
1513
  }
1514
}
1515

    
1516
/**
1517
  * @brief  Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
1518
  * @param DMATxDesc: Pointer on a Tx desc
1519
  * @param BufferSize1: specifies the Tx desc buffer1 size.
1520
  * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
1521
  * @retval : None
1522
  */
1523
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
1524
{
1525
  /* Check the parameters */
1526
  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
1527
  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
1528
  
1529
  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
1530
  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
1531
}
1532

    
1533
/**
1534
  * @brief  Initializes the DMA Rx descriptors in chain mode.
1535
  * @param DMARxDescTab: Pointer on the first Rx desc list 
1536
  * @param RxBuff: Pointer on the first RxBuffer list
1537
  * @param RxBuffCount: Number of the used Rx desc in the list
1538
  * @retval : None
1539
  */
1540
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
1541
{
1542
  uint32_t i = 0;
1543
  ETH_DMADESCTypeDef *DMARxDesc;
1544
  
1545
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1546
  DMARxDescToGet = DMARxDescTab; 
1547
  /* Fill each DMARxDesc descriptor with the right values */
1548
  for(i=0; i < RxBuffCount; i++)
1549
  {
1550
    /* Get the pointer on the ith member of the Rx Desc list */
1551
    DMARxDesc = DMARxDescTab+i;
1552
    /* Set Own bit of the Rx descriptor Status */
1553
    DMARxDesc->Status = ETH_DMARxDesc_OWN;
1554

    
1555
    /* Set Buffer1 size and Second Address Chained bit */
1556
    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;  
1557
    /* Set Buffer1 address pointer */
1558
    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
1559
    
1560
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1561
    if(i < (RxBuffCount-1))
1562
    {
1563
      /* Set next descriptor address register with next descriptor base address */
1564
      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
1565
    }
1566
    else
1567
    {
1568
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
1569
      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
1570
    }
1571
  }
1572
   
1573
  /* Set Receive Desciptor List Address Register */
1574
  ETH->DMARDLAR = (uint32_t) DMARxDescTab;  
1575
}
1576

    
1577
/**
1578
  * @brief  Initializes the DMA Rx descriptors in ring mode.
1579
  * @param DMARxDescTab: Pointer on the first Rx desc list 
1580
  * @param RxBuff1: Pointer on the first RxBuffer1 list 
1581
  * @param RxBuff2: Pointer on the first RxBuffer2 list
1582
  * @param RxBuffCount: Number of the used Rx desc in the list
1583
  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
1584
  *   for the number of Words to skip between two unchained descriptors.  
1585
  * @retval : None
1586
  */
1587
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
1588
{
1589
  uint32_t i = 0;
1590
  ETH_DMADESCTypeDef *DMARxDesc;
1591
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1592
  DMARxDescToGet = DMARxDescTab; 
1593
  /* Fill each DMARxDesc descriptor with the right values */  
1594
  for(i=0; i < RxBuffCount; i++)
1595
  {
1596
    /* Get the pointer on the ith member of the Rx Desc list */
1597
    DMARxDesc = DMARxDescTab+i; 
1598
    /* Set Own bit of the Rx descriptor Status */
1599
    DMARxDesc->Status = ETH_DMARxDesc_OWN; 
1600
    /* Set Buffer1 size */
1601
    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;  
1602
    /* Set Buffer1 address pointer */
1603
    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); 
1604
    
1605
    /* Set Buffer2 address pointer */
1606
    DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); 
1607
    
1608
    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
1609
       address of the list, creating a Desciptor Ring */
1610
    if(i == (RxBuffCount-1))
1611
    {
1612
      /* Set Receive End of Ring bit */
1613
      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1614
    }
1615
  }
1616
   
1617
  /* Set Receive Desciptor List Address Register */
1618
  ETH->DMARDLAR = (uint32_t) DMARxDescTab;  
1619
}
1620

    
1621
/**
1622
  * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
1623
  * @param DMARxDesc: pointer on a DMA Rx descriptor
1624
  * @param ETH_DMARxDescFlag: specifies the flag to check.
1625
  *   This parameter can be one of the following values:
1626
  * @arg ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine 
1627
  * @arg ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
1628
  * @arg ETH_DMARxDesc_ES:          Error summary
1629
  * @arg ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
1630
  * @arg ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
1631
  * @arg ETH_DMARxDesc_LE:          Frame size not matching with length field
1632
  * @arg ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
1633
  * @arg ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
1634
  * @arg ETH_DMARxDesc_FS:          First descriptor of the frame
1635
  * @arg ETH_DMARxDesc_LS:          Last descriptor of the frame
1636
  * @arg ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error 
1637
  * @arg ETH_DMARxDesc_LC:          Late collision occurred during reception
1638
  * @arg ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
1639
  * @arg ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
1640
  * @arg ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
1641
  * @arg ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
1642
  * @arg ETH_DMARxDesc_CE:          CRC error
1643
  * @arg ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
1644
  * @retval : The new state of ETH_DMARxDescFlag (SET or RESET).
1645
  */
1646
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
1647
{
1648
  FlagStatus bitstatus = RESET;
1649
  /* Check the parameters */
1650
  assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
1651
  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
1652
  {
1653
    bitstatus = SET;
1654
  }
1655
  else
1656
  {
1657
    bitstatus = RESET;
1658
  }
1659
  return bitstatus;
1660
}
1661

    
1662
/**
1663
  * @brief  Set the specified DMA Rx Desc Own bit.
1664
  * @param DMARxDesc: Pointer on a Rx desc
1665
  * @retval : None
1666
  */
1667
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
1668
{
1669
  /* Set the DMA Rx Desc Own bit */
1670
  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
1671
}
1672

    
1673
/**
1674
  * @brief  Returns the specified DMA Rx Desc frame length.
1675
  * @param DMARxDesc: pointer on a DMA Rx descriptor                     
1676
  * @retval : The Rx descriptor received frame length.
1677
  */
1678
uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
1679
{
1680
  /* Return the Receive descriptor frame length */
1681
  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
1682
}
1683

    
1684
/**
1685
  * @brief  Enables or disables the specified DMA Rx Desc receive interrupt.
1686
  * @param DMARxDesc: Pointer on a Rx desc
1687
  * @param NewState: new state of the specified DMA Rx Desc interrupt.
1688
  *   This parameter can be: ENABLE or DISABLE.                   
1689
  * @retval : None
1690
  */
1691
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1692
{
1693
  /* Check the parameters */
1694
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1695
  
1696
  if (NewState != DISABLE)
1697
  {
1698
    /* Enable the DMA Rx Desc receive interrupt */
1699
    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
1700
  }
1701
  else
1702
  {
1703
    /* Disable the DMA Rx Desc receive interrupt */
1704
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
1705
  }
1706
}
1707

    
1708
/**
1709
  * @brief  Enables or disables the DMA Rx Desc end of ring.
1710
  * @param DMARxDesc: pointer on a DMA Rx descriptor
1711
  * @param NewState: new state of the specified DMA Rx Desc end of ring.
1712
  *   This parameter can be: ENABLE or DISABLE.
1713
  * @retval : None
1714
  */
1715
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1716
{
1717
  /* Check the parameters */
1718
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1719
  
1720
  if (NewState != DISABLE)
1721
  {
1722
    /* Enable the selected DMA Rx Desc end of ring */
1723
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;  
1724
  }
1725
  else
1726
  {
1727
    /* Disable the selected DMA Rx Desc end of ring */
1728
    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); 
1729
  }
1730
}
1731

    
1732
/**
1733
  * @brief  Enables or disables the DMA Rx Desc second address chained.
1734
  * @param DMARxDesc: pointer on a DMA Rx descriptor
1735
  * @param NewState: new state of the specified DMA Rx Desc second address chained.
1736
  *   This parameter can be: ENABLE or DISABLE.
1737
  * @retval : None
1738
  */
1739
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1740
{
1741
  /* Check the parameters */
1742
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1743
  
1744
  if (NewState != DISABLE)
1745
  {
1746
    /* Enable the selected DMA Rx Desc second address chained */
1747
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;  
1748
  }
1749
  else
1750
  {
1751
    /* Disable the selected DMA Rx Desc second address chained */
1752
    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); 
1753
  }
1754
}
1755

    
1756
/**
1757
  * @brief  Returns the specified ETHERNET DMA Rx Desc buffer size.
1758
  * @param DMARxDesc: pointer on a DMA Rx descriptor 
1759
  * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
1760
  *   This parameter can be any one of the following values:
1761
  * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
1762
  * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2                     
1763
  * @retval : The Receive descriptor frame length.
1764
  */
1765
uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
1766
{
1767
  /* Check the parameters */
1768
  assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
1769
  
1770
  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
1771
  {
1772
    /* Return the DMA Rx Desc buffer2 size */
1773
    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); 
1774
  }
1775
  else
1776
  {
1777
    /* Return the DMA Rx Desc buffer1 size */
1778
    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); 
1779
  }
1780
}
1781

    
1782
/*---------------------------------  DMA  ------------------------------------*/
1783
/**
1784
  * @brief  Resets all MAC subsystem internal registers and logic.
1785
  * @param  None
1786
  * @retval : None
1787
  */
1788
void ETH_SoftwareReset(void)
1789
{
1790
  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
1791
  /* After reset all the registers holds their respective reset values */
1792
  ETH->DMABMR |= ETH_DMABMR_SR;
1793
}
1794

    
1795
/**
1796
  * @brief  Checks whether the ETHERNET software reset bit is set or not.
1797
  * @param  None
1798
  * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET).
1799
  */
1800
FlagStatus ETH_GetSoftwareResetStatus(void)
1801
{
1802
  FlagStatus bitstatus = RESET;
1803
  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
1804
  {
1805
    bitstatus = SET;
1806
  }
1807
  else
1808
  {
1809
    bitstatus = RESET;
1810
  }
1811
  return bitstatus;
1812
}
1813

    
1814
/**
1815
  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
1816
  * @param ETH_DMA_FLAG: specifies the flag to check.
1817
  *   This parameter can be one of the following values:
1818
  * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
1819
  * @arg ETH_DMA_FLAG_PMT : PMT flag 
1820
  * @arg ETH_DMA_FLAG_MMC : MMC flag 
1821
  * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
1822
  * @arg ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
1823
  * @arg ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
1824
  * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1825
  * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag  
1826
  * @arg ETH_DMA_FLAG_ER  : Early receive flag 
1827
  * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
1828
  * @arg ETH_DMA_FLAG_ET  : Early transmit flag 
1829
  * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
1830
  * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
1831
  * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
1832
  * @arg ETH_DMA_FLAG_R   : Receive flag 
1833
  * @arg ETH_DMA_FLAG_TU  : Underflow flag 
1834
  * @arg ETH_DMA_FLAG_RO  : Overflow flag 
1835
  * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
1836
  * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
1837
  * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
1838
  * @arg ETH_DMA_FLAG_T   : Transmit flag 
1839
  * @retval : The new state of ETH_DMA_FLAG (SET or RESET).
1840
  */
1841
FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
1842
{  
1843
  FlagStatus bitstatus = RESET;
1844
  /* Check the parameters */
1845
  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
1846
  if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
1847
  {
1848
    bitstatus = SET;
1849
  }
1850
  else
1851
  {
1852
    bitstatus = RESET;
1853
  }
1854
  return bitstatus;
1855
}
1856

    
1857
/**
1858
  * @brief  Clears the ETHERNET?s DMA pending flag.
1859
  * @param ETH_DMA_FLAG: specifies the flag to clear.
1860
  *   This parameter can be any combination of the following values:
1861
  * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1862
  * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag 
1863
  * @arg ETH_DMA_FLAG_ER  : Early receive flag 
1864
  * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
1865
  * @arg ETH_DMA_FLAG_ETI : Early transmit flag 
1866
  * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
1867
  * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
1868
  * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
1869
  * @arg ETH_DMA_FLAG_R   : Receive flag 
1870
  * @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag 
1871
  * @arg ETH_DMA_FLAG_RO  : Receive Overflow flag 
1872
  * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
1873
  * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
1874
  * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
1875
  * @arg ETH_DMA_FLAG_T   : Transmit flag
1876
  * @retval : None
1877
  */
1878
void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
1879
{
1880
  /* Check the parameters */
1881
  assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
1882
  
1883
  /* Clear the selected ETHERNET DMA FLAG */
1884
  ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
1885
}
1886

    
1887
/**
1888
  * @brief  Checks whether the specified ETHERNET DMA interrupt has occured or not.
1889
  * @param ETH_DMA_IT: specifies the interrupt source to check.
1890
  *   This parameter can be one of the following values:
1891
  * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
1892
  * @arg ETH_DMA_IT_PMT : PMT interrupt 
1893
  * @arg ETH_DMA_IT_MMC : MMC interrupt
1894
  * @arg ETH_DMA_IT_NIS : Normal interrupt summary 
1895
  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
1896
  * @arg ETH_DMA_IT_ER  : Early receive interrupt 
1897
  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
1898
  * @arg ETH_DMA_IT_ET  : Early transmit interrupt 
1899
  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
1900
  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
1901
  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
1902
  * @arg ETH_DMA_IT_R   : Receive interrupt 
1903
  * @arg ETH_DMA_IT_TU  : Underflow interrupt 
1904
  * @arg ETH_DMA_IT_RO  : Overflow interrupt 
1905
  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
1906
  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
1907
  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
1908
  * @arg ETH_DMA_IT_T   : Transmit interrupt 
1909
  * @retval : The new state of ETH_DMA_IT (SET or RESET).
1910
  */
1911
ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
1912
{  
1913
  ITStatus bitstatus = RESET;
1914
  /* Check the parameters */
1915
  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
1916
  if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
1917
  {
1918
    bitstatus = SET;
1919
  }
1920
  else
1921
  {
1922
    bitstatus = RESET;
1923
  }
1924
  return bitstatus;
1925
}
1926

    
1927
/**
1928
  * @brief  Clears the ETHERNET?s DMA IT pending bit.
1929
  * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
1930
  *   This parameter can be any combination of the following values:
1931
  * @arg ETH_DMA_IT_NIS : Normal interrupt summary 
1932
  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
1933
  * @arg ETH_DMA_IT_ER  : Early receive interrupt 
1934
  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
1935
  * @arg ETH_DMA_IT_ETI : Early transmit interrupt 
1936
  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
1937
  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
1938
  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
1939
  * @arg ETH_DMA_IT_R   : Receive interrupt 
1940
  * @arg ETH_DMA_IT_TU  : Transmit Underflow interrupt 
1941
  * @arg ETH_DMA_IT_RO  : Receive Overflow interrupt 
1942
  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
1943
  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
1944
  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
1945
  * @arg ETH_DMA_IT_T   : Transmit interrupt
1946
  * @retval : None
1947
  */
1948
void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
1949
{
1950
  /* Check the parameters */
1951
  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
1952
  
1953
  /* Clear the selected ETHERNET DMA IT */
1954
  ETH->DMASR = (uint32_t) ETH_DMA_IT;
1955
}
1956

    
1957
/**
1958
  * @brief  Returns the ETHERNET DMA Transmit Process State.
1959
  * @param  None
1960
  * @retval : The new ETHERNET DMA Transmit Process State:
1961
  *   This can be one of the following values:
1962
  * - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
1963
  * - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor 
1964
  * - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
1965
  * - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
1966
  * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
1967
  * - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor  
1968
  */
1969
uint32_t ETH_GetTransmitProcessState(void)
1970
{
1971
  return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); 
1972
}
1973

    
1974
/**
1975
  * @brief  Returns the ETHERNET DMA Receive Process State.
1976
  * @param  None
1977
  * @retval : The new ETHERNET DMA Receive Process State:
1978
  *   This can be one of the following values:
1979
  * - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
1980
  * - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor 
1981
  * - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
1982
  * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
1983
  * - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
1984
  * - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory  
1985
  */
1986
uint32_t ETH_GetReceiveProcessState(void)
1987
{
1988
  return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); 
1989
}
1990

    
1991
/**
1992
  * @brief  Clears the ETHERNET transmit FIFO.
1993
  * @param  None                
1994
  * @retval : None
1995
  */
1996
void ETH_FlushTransmitFIFO(void)
1997
{
1998
  /* Set the Flush Transmit FIFO bit */
1999
  ETH->DMAOMR |= ETH_DMAOMR_FTF;  
2000
}
2001

    
2002
/**
2003
  * @brief  Checks whether the ETHERNET transmit FIFO bit is cleared or not.
2004
  * @param  None                
2005
  * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
2006
  */
2007
FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
2008
{   
2009
  FlagStatus bitstatus = RESET;
2010
  if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
2011
  {
2012
    bitstatus = SET;
2013
  }
2014
  else
2015
  {
2016
    bitstatus = RESET;
2017
  }
2018
  return bitstatus; 
2019
}
2020

    
2021
/**
2022
  * @brief  Enables or disables the DMA transmission.
2023
  * @param NewState: new state of the DMA transmission.
2024
  *   This parameter can be: ENABLE or DISABLE.
2025
  * @retval : None
2026
  */
2027
void ETH_DMATransmissionCmd(FunctionalState NewState)
2028
{ 
2029
  /* Check the parameters */
2030
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2031
  
2032
  if (NewState != DISABLE)
2033
  {
2034
    /* Enable the DMA transmission */
2035
    ETH->DMAOMR |= ETH_DMAOMR_ST;  
2036
  }
2037
  else
2038
  {
2039
    /* Disable the DMA transmission */
2040
    ETH->DMAOMR &= ~ETH_DMAOMR_ST;
2041
  }
2042
}
2043

    
2044
/**
2045
  * @brief  Enables or disables the DMA reception.
2046
  * @param NewState: new state of the DMA reception.
2047
  *   This parameter can be: ENABLE or DISABLE.
2048
  * @retval : None
2049
  */
2050
void ETH_DMAReceptionCmd(FunctionalState NewState)
2051
{ 
2052
  /* Check the parameters */
2053
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2054
  
2055
  if (NewState != DISABLE)
2056
  {
2057
    /* Enable the DMA reception */
2058
    ETH->DMAOMR |= ETH_DMAOMR_SR;  
2059
  }
2060
  else
2061
  {
2062
    /* Disable the DMA reception */
2063
    ETH->DMAOMR &= ~ETH_DMAOMR_SR;
2064
  }
2065
}
2066

    
2067
/**
2068
  * @brief  Enables or disables the specified ETHERNET DMA interrupts.
2069
  * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
2070
  *   enabled or disabled.
2071
  *   This parameter can be any combination of the following values:
2072
  * @arg ETH_DMA_IT_NIS : Normal interrupt summary 
2073
  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
2074
  * @arg ETH_DMA_IT_ER  : Early receive interrupt 
2075
  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
2076
  * @arg ETH_DMA_IT_ET  : Early transmit interrupt 
2077
  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
2078
  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
2079
  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
2080
  * @arg ETH_DMA_IT_R   : Receive interrupt 
2081
  * @arg ETH_DMA_IT_TU  : Underflow interrupt 
2082
  * @arg ETH_DMA_IT_RO  : Overflow interrupt 
2083
  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
2084
  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
2085
  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
2086
  * @arg ETH_DMA_IT_T   : Transmit interrupt
2087
  * @param NewState: new state of the specified ETHERNET DMA interrupts.
2088
  *   This parameter can be: ENABLE or DISABLE.
2089
  * @retval : None
2090
  */
2091
void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
2092
{
2093
  /* Check the parameters */
2094
  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
2095
  assert_param(IS_FUNCTIONAL_STATE(NewState));  
2096
  
2097
  if (NewState != DISABLE)
2098
  {
2099
    /* Enable the selected ETHERNET DMA interrupts */
2100
    ETH->DMAIER |= ETH_DMA_IT;
2101
  }
2102
  else
2103
  {
2104
    /* Disable the selected ETHERNET DMA interrupts */
2105
    ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
2106
  }
2107
}
2108

    
2109
/**
2110
  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
2111
  * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
2112
  *   This parameter can be one of the following values:
2113
  * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
2114
  * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
2115
  * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET).
2116
  */
2117
FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
2118
{
2119
  FlagStatus bitstatus = RESET;
2120
  /* Check the parameters */
2121
  assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
2122
  
2123
  if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
2124
  {
2125
    bitstatus = SET;
2126
  }
2127
  else
2128
  {
2129
    bitstatus = RESET;
2130
  }
2131
  return bitstatus;
2132
}
2133

    
2134
/**
2135
  * @brief  Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
2136
  * @param  None
2137
  * @retval : The value of Rx overflow Missed Frame Counter.
2138
  */
2139
uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
2140
{
2141
  return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
2142
}
2143

    
2144
/**
2145
  * @brief  Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
2146
  * @param  None
2147
  * @retval : The value of Buffer unavailable Missed Frame Counter.
2148
  */
2149
uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
2150
{
2151
  return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
2152
}
2153

    
2154
/**
2155
  * @brief  Get the ETHERNET DMA DMACHTDR register value.
2156
  * @param  None
2157
  * @retval : The value of the current Tx desc start address.
2158
  */
2159
uint32_t ETH_GetCurrentTxDescStartAddress(void)
2160
{
2161
  return ((uint32_t)(ETH->DMACHTDR));
2162
}
2163

    
2164
/**
2165
  * @brief  Get the ETHERNET DMA DMACHRDR register value.
2166
  * @param  None
2167
  * @retval : The value of the current Rx desc start address.
2168
  */
2169
uint32_t ETH_GetCurrentRxDescStartAddress(void)
2170
{
2171
  return ((uint32_t)(ETH->DMACHRDR));
2172
}
2173

    
2174
/**
2175
  * @brief  Get the ETHERNET DMA DMACHTBAR register value.
2176
  * @param  None
2177
  * @retval : The value of the current Tx desc buffer address.
2178
  */
2179
uint32_t ETH_GetCurrentTxBufferAddress(void)
2180
{
2181
  return ((uint32_t)(ETH->DMACHTBAR));
2182
}
2183

    
2184
/**
2185
  * @brief  Get the ETHERNET DMA DMACHRBAR register value.
2186
  * @param  None
2187
  * @retval : The value of the current Rx desc buffer address.
2188
  */
2189
uint32_t ETH_GetCurrentRxBufferAddress(void)
2190
{
2191
  return ((uint32_t)(ETH->DMACHRBAR));
2192
}
2193

    
2194
/**
2195
  * @brief  Resumes the DMA Transmission by writing to the DmaTxPollDemand 
2196
  *   register: (the data written could be anything). This forces 
2197
  *   the DMA to resume transmission.
2198
  * @param  None
2199
  * @retval : None.
2200
  */
2201
void ETH_ResumeDMATransmission(void)
2202
{
2203
  ETH->DMATPDR = 0;
2204
}
2205

    
2206
/**
2207
  * @brief  Resumes the DMA Transmission by writing to the DmaRxPollDemand 
2208
  *   register: (the data written could be anything). This forces 
2209
  *   the DMA to resume reception.
2210
  * @param  None
2211
  * @retval : None.
2212
  */
2213
void ETH_ResumeDMAReception(void)
2214
{
2215
  ETH->DMARPDR = 0;
2216
}
2217

    
2218
/*---------------------------------  PMT  ------------------------------------*/
2219
/**
2220
  * @brief  Reset Wakeup frame filter register pointer.
2221
  * @param  None
2222
  * @retval : None
2223
  */
2224
void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
2225
{  
2226
  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
2227
  ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;  
2228
}
2229

    
2230
/**
2231
  * @brief  Populates the remote wakeup frame registers.
2232
  * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer
2233
  *   data (8 words).
2234
  * @retval : None
2235
  */
2236
void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
2237
{
2238
  uint32_t i = 0;
2239
  
2240
  /* Fill Remote Wake-up Frame Filter register with Buffer data */
2241
  for(i =0; i<ETH_WakeupRegisterLength; i++)
2242
  {
2243
    /* Write each time to the same register */ 
2244
    ETH->MACRWUFFR = Buffer[i];
2245
  }
2246
}
2247

    
2248
/**
2249
  * @brief  Enables or disables any unicast packet filtered by the MAC 
2250
  *   (DAF) address recognition to be a wake-up frame.
2251
  * @param NewState: new state of the MAC Global Unicast Wake-Up.
2252
  *   This parameter can be: ENABLE or DISABLE.
2253
  * @retval : None
2254
  */
2255
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
2256
{ 
2257
  /* Check the parameters */
2258
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2259
  
2260
  if (NewState != DISABLE)
2261
  {
2262
    /* Enable the MAC Global Unicast Wake-Up */
2263
    ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;  
2264
  }
2265
  else
2266
  {
2267
    /* Disable the MAC Global Unicast Wake-Up */ 
2268
    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
2269
  }
2270
}
2271

    
2272
/**
2273
  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
2274
  * @param ETH_PMT_FLAG: specifies the flag to check.
2275
  *   This parameter can be one of the following values:
2276
  * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset 
2277
  * @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
2278
  * @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
2279
  * @retval : The new state of ETHERNET PMT Flag (SET or RESET).
2280
  */
2281
FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
2282
{
2283
  FlagStatus bitstatus = RESET;
2284
  /* Check the parameters */
2285
  assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
2286
  
2287
  if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
2288
  {
2289
    bitstatus = SET;
2290
  }
2291
  else
2292
  {
2293
    bitstatus = RESET;
2294
  }
2295
  return bitstatus;
2296
}
2297

    
2298
/**
2299
  * @brief  Enables or disables the MAC Wake-Up Frame Detection.
2300
  * @param NewState: new state of the MAC Wake-Up Frame Detection.
2301
  *   This parameter can be: ENABLE or DISABLE.
2302
  * @retval : None
2303
  */
2304
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
2305
{ 
2306
  /* Check the parameters */
2307
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2308
  
2309
  if (NewState != DISABLE)
2310
  {
2311
    /* Enable the MAC Wake-Up Frame Detection */
2312
    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;  
2313
  }
2314
  else
2315
  {
2316
    /* Disable the MAC Wake-Up Frame Detection */ 
2317
    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
2318
  }
2319
}
2320

    
2321
/**
2322
  * @brief  Enables or disables the MAC Magic Packet Detection.
2323
  * @param NewState: new state of the MAC Magic Packet Detection.
2324
  *   This parameter can be: ENABLE or DISABLE.
2325
  * @retval : None
2326
  */
2327
void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
2328
{ 
2329
  /* Check the parameters */
2330
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2331
  
2332
  if (NewState != DISABLE)
2333
  {
2334
    /* Enable the MAC Magic Packet Detection */
2335
    ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;  
2336
  }
2337
  else
2338
  {
2339
    /* Disable the MAC Magic Packet Detection */ 
2340
    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
2341
  }
2342
}
2343

    
2344
/**
2345
  * @brief  Enables or disables the MAC Power Down.
2346
  * @param NewState: new state of the MAC Power Down.
2347
  *   This parameter can be: ENABLE or DISABLE.
2348
  * @retval : None
2349
  */
2350
void ETH_PowerDownCmd(FunctionalState NewState)
2351
{ 
2352
  /* Check the parameters */
2353
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2354
  
2355
  if (NewState != DISABLE)
2356
  {
2357
    /* Enable the MAC Power Down */
2358
    /* This puts the MAC in power down mode */
2359
    ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;  
2360
  }
2361
  else
2362
  {
2363
    /* Disable the MAC Power Down */ 
2364
    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
2365
  }
2366
}
2367

    
2368
/*---------------------------------  MMC  ------------------------------------*/
2369
/**
2370
  * @brief  Enables or disables the MMC Counter Freeze.
2371
  * @param NewState: new state of the MMC Counter Freeze.
2372
  *   This parameter can be: ENABLE or DISABLE.
2373
  * @retval : None
2374
  */
2375
void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
2376
{
2377
  /* Check the parameters */
2378
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2379
  
2380
  if (NewState != DISABLE)
2381
  {
2382
    /* Enable the MMC Counter Freeze */
2383
    ETH->MMCCR |= ETH_MMCCR_MCF;
2384
  }
2385
  else
2386
  {
2387
    /* Disable the MMC Counter Freeze */
2388
    ETH->MMCCR &= ~ETH_MMCCR_MCF;
2389
  }
2390
}
2391

    
2392
/**
2393
  * @brief  Enables or disables the MMC Reset On Read.
2394
  * @param NewState: new state of the MMC Reset On Read.
2395
  *   This parameter can be: ENABLE or DISABLE.
2396
  * @retval : None
2397
  */
2398
void ETH_MMCResetOnReadCmd(FunctionalState NewState)
2399
{
2400
  /* Check the parameters */
2401
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2402
  
2403
  if (NewState != DISABLE)
2404
  {
2405
    /* Enable the MMC Counter reset on read */
2406
    ETH->MMCCR |= ETH_MMCCR_ROR; 
2407
  }
2408
  else
2409
  {
2410
    /* Disable the MMC Counter reset on read */
2411
    ETH->MMCCR &= ~ETH_MMCCR_ROR;
2412
  }
2413
}
2414

    
2415
/**
2416
  * @brief  Enables or disables the MMC Counter Stop Rollover.
2417
  * @param NewState: new state of the MMC Counter Stop Rollover.
2418
  *   This parameter can be: ENABLE or DISABLE.
2419
  * @retval : None
2420
  */
2421
void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
2422
{
2423
  /* Check the parameters */
2424
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2425
  
2426
  if (NewState != DISABLE)
2427
  {
2428
    /* Disable the MMC Counter Stop Rollover  */
2429
    ETH->MMCCR &= ~ETH_MMCCR_CSR;
2430
  }
2431
  else
2432
  {
2433
    /* Enable the MMC Counter Stop Rollover */
2434
    ETH->MMCCR |= ETH_MMCCR_CSR; 
2435
  }
2436
}
2437

    
2438
/**
2439
  * @brief  Resets the MMC Counters.
2440
  * @param  None
2441
  * @retval : None
2442
  */
2443
void ETH_MMCCountersReset(void)
2444
{
2445
  /* Resets the MMC Counters */
2446
  ETH->MMCCR |= ETH_MMCCR_CR; 
2447
}
2448

    
2449
/**
2450
  * @brief  Enables or disables the specified ETHERNET MMC interrupts.
2451
  * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt 
2452
  *   sources to be enabled or disabled.
2453
  *   This parameter can be any combination of Tx interrupt or 
2454
  *   any combination of Rx interrupt (but not both)of the following values: 
2455
  * @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
2456
  * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
2457
  * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
2458
  * @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value  
2459
  * @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
2460
  * @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
2461
  * @param NewState: new state of the specified ETHERNET MMC interrupts.
2462
  *   This parameter can be: ENABLE or DISABLE.
2463
  * @retval : None
2464
  */
2465
void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
2466
{ 
2467
  /* Check the parameters */
2468
  assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));  
2469
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2470
   
2471
  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2472
  {
2473
    /* Remove egister mak from IT */
2474
    ETH_MMC_IT &= 0xEFFFFFFF;
2475
  
2476
    /* ETHERNET MMC Rx interrupts selected */
2477
    if (NewState != DISABLE)
2478
    {
2479
      /* Enable the selected ETHERNET MMC interrupts */
2480
      ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
2481
    }
2482
    else
2483
    {
2484
      /* Disable the selected ETHERNET MMC interrupts */
2485
      ETH->MMCRIMR |= ETH_MMC_IT;    
2486
    }
2487
  }
2488
  else
2489
  {
2490
    /* ETHERNET MMC Tx interrupts selected */
2491
    if (NewState != DISABLE)
2492
    {
2493
      /* Enable the selected ETHERNET MMC interrupts */
2494
      ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
2495
    }
2496
    else
2497
    {
2498
      /* Disable the selected ETHERNET MMC interrupts */
2499
      ETH->MMCTIMR |= ETH_MMC_IT;    
2500
    }  
2501
  }
2502
}
2503

    
2504
/**
2505
  * @brief  Checks whether the specified ETHERNET MMC IT is set or not.
2506
  * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
2507
  *   This parameter can be one of the following values:
2508
  * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value 
2509
  * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value 
2510
  * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value 
2511
  * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value  
2512
  * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value 
2513
  * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value 
2514
  * @retval : The value of ETHERNET MMC IT (SET or RESET).
2515
  */
2516
ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
2517
{
2518
  ITStatus bitstatus = RESET;
2519
  /* Check the parameters */
2520
  assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); 
2521
  
2522
  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2523
  {
2524
    /* ETHERNET MMC Rx interrupts selected */
2525
    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ 
2526
    if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2527
    {
2528
      bitstatus = SET;
2529
    }
2530
    else
2531
    {
2532
      bitstatus = RESET;
2533
    }
2534
  }
2535
  else
2536
  {
2537
    /* ETHERNET MMC Tx interrupts selected */
2538
    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */  
2539
    if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2540
    {
2541
      bitstatus = SET;
2542
    }
2543
    else
2544
    {
2545
      bitstatus = RESET;
2546
    }  
2547
  }    
2548
    
2549
  return bitstatus;
2550
}
2551

    
2552
/**
2553
  * @brief  Get the specified ETHERNET MMC register value.
2554
  * @param ETH_MMCReg: specifies the ETHERNET MMC register.
2555
  *   This parameter can be one of the following values:
2556
  * @arg ETH_MMCCR      : MMC CR register 
2557
  * @arg ETH_MMCRIR     : MMC RIR register 
2558
  * @arg ETH_MMCTIR     : MMC TIR register 
2559
  * @arg ETH_MMCRIMR    : MMC RIMR register 
2560
  * @arg ETH_MMCTIMR    : MMC TIMR register 
2561
  * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register 
2562
  * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register  
2563
  * @arg ETH_MMCTGFCR   : MMC TGFCR register
2564
  * @arg ETH_MMCRFCECR  : MMC RFCECR register 
2565
  * @arg ETH_MMCRFAECR  : MMC RFAECR register 
2566
  * @arg ETH_MMCRGUFCR  : MMC RGUFCRregister 
2567
  * @retval : The value of ETHERNET MMC Register value.
2568
  */
2569
uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
2570
{
2571
  /* Check the parameters */
2572
  assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
2573
  
2574
  /* Return the selected register value */
2575
  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
2576
}
2577
/*---------------------------------  PTP  ------------------------------------*/
2578

    
2579
/**
2580
  * @brief  Updated the PTP block for fine correction with the Time Stamp
2581
  *   Addend register value.
2582
  * @param  None
2583
  * @retval : None
2584
  */
2585
void ETH_EnablePTPTimeStampAddend(void)
2586
{
2587
  /* Enable the PTP block update with the Time Stamp Addend register value */
2588
  ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;    
2589
}
2590

    
2591
/**
2592
  * @brief  Enable the PTP Time Stamp interrupt trigger
2593
  * @param  None
2594
  * @retval : None
2595
  */
2596
void ETH_EnablePTPTimeStampInterruptTrigger(void)
2597
{
2598
  /* Enable the PTP target time interrupt */
2599
  ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;    
2600
}
2601

    
2602
/**
2603
  * @brief  Updated the PTP system time with the Time Stamp Update register
2604
  *   value.
2605
  * @param  None
2606
  * @retval : None
2607
  */
2608
void ETH_EnablePTPTimeStampUpdate(void)
2609
{
2610
  /* Enable the PTP system time update with the Time Stamp Update register value */
2611
  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;    
2612
}
2613

    
2614
/**
2615
  * @brief  Initialize the PTP Time Stamp
2616
  * @param  None
2617
  * @retval : None
2618
  */
2619
void ETH_InitializePTPTimeStamp(void)
2620
{
2621
  /* Initialize the PTP Time Stamp */
2622
  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;    
2623
}
2624

    
2625
/**
2626
  * @brief  Selects the PTP Update method
2627
  * @param UpdateMethod: the PTP Update method
2628
  *   This parameter can be one of the following values:
2629
  * @arg ETH_PTP_FineUpdate   : Fine Update method 
2630
  * @arg ETH_PTP_CoarseUpdate : Coarse Update method 
2631
  * @retval : None
2632
  */
2633
void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
2634
{
2635
  /* Check the parameters */
2636
  assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
2637
  
2638
  if (UpdateMethod != ETH_PTP_CoarseUpdate)
2639
  {
2640
    /* Enable the PTP Fine Update method */
2641
    ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
2642
  }
2643
  else
2644
  {
2645
    /* Disable the PTP Coarse Update method */
2646
    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
2647
  } 
2648
}
2649

    
2650
/**
2651
  * @brief  Enables or disables the PTP time stamp for transmit and receive frames.
2652
  * @param NewState: new state of the PTP time stamp for transmit and receive frames
2653
  *   This parameter can be: ENABLE or DISABLE.
2654
  * @retval : None
2655
  */
2656
void ETH_PTPTimeStampCmd(FunctionalState NewState)
2657
{
2658
  /* Check the parameters */
2659
  assert_param(IS_FUNCTIONAL_STATE(NewState));
2660
  
2661
  if (NewState != DISABLE)
2662
  {
2663
    /* Enable the PTP time stamp for transmit and receive frames */
2664
    ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
2665
  }
2666
  else
2667
  {
2668
    /* Disable the PTP time stamp for transmit and receive frames */
2669
    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
2670
  }
2671
}
2672

    
2673
/**
2674
  * @brief  Checks whether the specified ETHERNET PTP flag is set or not.
2675
  * @param ETH_PTP_FLAG: specifies the flag to check.
2676
  *   This parameter can be one of the following values:
2677
  * @arg ETH_PTP_FLAG_TSARU : Addend Register Update 
2678
  * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable 
2679
  * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update 
2680
  * @arg ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize                       
2681
  * @retval : The new state of ETHERNET PTP Flag (SET or RESET).
2682
  */
2683
FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
2684
{
2685
  FlagStatus bitstatus = RESET;
2686
  /* Check the parameters */
2687
  assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
2688
  
2689
  if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
2690
  {
2691
    bitstatus = SET;
2692
  }
2693
  else
2694
  {
2695
    bitstatus = RESET;
2696
  }
2697
  return bitstatus;
2698
}
2699

    
2700
/**
2701
  * @brief  Sets the system time Sub-Second Increment value.
2702
  * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.
2703
  * @retval : None
2704
  */
2705
void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
2706
{
2707
  /* Check the parameters */
2708
  assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
2709
  /* Set the PTP Sub-Second Increment Register */
2710
  ETH->PTPSSIR = SubSecondValue;    
2711
}
2712

    
2713
/**
2714
  * @brief  Sets the Time Stamp update sign and values.
2715
  * @param Sign: specifies the PTP Time update value sign.
2716
  *   This parameter can be one of the following values:
2717
  * @arg ETH_PTP_PositiveTime : positive time value. 
2718
  * @arg ETH_PTP_NegativeTime : negative time value.  
2719
  * @param SecondValue: specifies the PTP Time update second value. 
2720
  * @param SubSecondValue: specifies the PTP Time update sub-second value.
2721
  *   this is a 31 bit value. bit32 correspond to the sign.
2722
  * @retval : None
2723
  */
2724
void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
2725
{
2726
  /* Check the parameters */
2727
  assert_param(IS_ETH_PTP_TIME_SIGN(Sign));  
2728
  assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); 
2729
  /* Set the PTP Time Update High Register */
2730
  ETH->PTPTSHUR = SecondValue;
2731
  
2732
  /* Set the PTP Time Update Low Register with sign */
2733
  ETH->PTPTSLUR = Sign | SubSecondValue;   
2734
}
2735

    
2736
/**
2737
  * @brief  Sets the Time Stamp Addend value.
2738
  * @param Value: specifies the PTP Time Stamp Addend Register value.
2739
  * @retval : None
2740
  */
2741
void ETH_SetPTPTimeStampAddend(uint32_t Value)
2742
{
2743
  /* Set the PTP Time Stamp Addend Register */
2744
  ETH->PTPTSAR = Value;    
2745
}
2746

    
2747
/**
2748
  * @brief  Sets the Target Time registers values.
2749
  * @param HighValue: specifies the PTP Target Time High Register value.
2750
  * @param LowValue: specifies the PTP Target Time Low Register value.
2751
  * @retval : None
2752
  */
2753
void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
2754
{
2755
  /* Set the PTP Target Time High Register */
2756
  ETH->PTPTTHR = HighValue;
2757
  /* Set the PTP Target Time Low Register */
2758
  ETH->PTPTTLR = LowValue;    
2759
}
2760

    
2761
/**
2762
  * @brief  Get the specified ETHERNET PTP register value.
2763
  * @param ETH_PTPReg: specifies the ETHERNET PTP register.
2764
  *   This parameter can be one of the following values:
2765
  * @arg ETH_PTPTSCR  : Sub-Second Increment Register 
2766
  * @arg ETH_PTPSSIR  : Sub-Second Increment Register 
2767
  * @arg ETH_PTPTSHR  : Time Stamp High Register
2768
  * @arg ETH_PTPTSLR  : Time Stamp Low Register 
2769
  * @arg ETH_PTPTSHUR : Time Stamp High Update Register  
2770
  * @arg ETH_PTPTSLUR : Time Stamp Low Update Register
2771
  * @arg ETH_PTPTSAR  : Time Stamp Addend Register
2772
  * @arg ETH_PTPTTHR  : Target Time High Register 
2773
  * @arg ETH_PTPTTLR  : Target Time Low Register 
2774
  * @retval : The value of ETHERNET PTP Register value.
2775
  */
2776
uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
2777
{
2778
  /* Check the parameters */
2779
  assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
2780
  
2781
  /* Return the selected register value */
2782
  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
2783
}
2784

    
2785
/**
2786
  * @brief  Initializes the DMA Tx descriptors in chain mode with PTP.
2787
  * @param DMATxDescTab: Pointer on the first Tx desc list 
2788
  * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
2789
  * @param TxBuff: Pointer on the first TxBuffer list
2790
  * @param TxBuffCount: Number of the used Tx desc in the list
2791
  * @retval : None
2792
  */
2793
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
2794
{
2795
  uint32_t i = 0;
2796
  ETH_DMADESCTypeDef *DMATxDesc;
2797
  
2798
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
2799
  DMATxDescToSet = DMATxDescTab;
2800
  DMAPTPTxDescToSet = DMAPTPTxDescTab;
2801
  /* Fill each DMATxDesc descriptor with the right values */   
2802
  for(i=0; i < TxBuffCount; i++)
2803
  {
2804
    /* Get the pointer on the ith member of the Tx Desc list */
2805
    DMATxDesc = DMATxDescTab+i;
2806
    /* Set Second Address Chained bit and enable PTP */
2807
    DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;  
2808
       
2809
    /* Set Buffer1 address pointer */
2810
    DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
2811
    
2812
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2813
    if(i < (TxBuffCount-1))
2814
    {
2815
      /* Set next descriptor address register with next descriptor base address */
2816
      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
2817
    }
2818
    else
2819
    {
2820
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
2821
      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
2822
    }
2823
    /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
2824
    (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
2825
    (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
2826
  }
2827
  /* Store on the last DMAPTPTxDescTab desc status record the first list address */
2828
  (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
2829

    
2830
  /* Set Transmit Desciptor List Address Register */
2831
  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
2832
}
2833

    
2834
/**
2835
  * @brief  Initializes the DMA Rx descriptors in chain mode.
2836
  * @param DMARxDescTab: Pointer on the first Rx desc list 
2837
  * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
2838
  * @param RxBuff: Pointer on the first RxBuffer list
2839
  * @param RxBuffCount: Number of the used Rx desc in the list
2840
  * @retval : None
2841
  */
2842
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
2843
{
2844
  uint32_t i = 0;
2845
  ETH_DMADESCTypeDef *DMARxDesc;
2846
  
2847
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
2848
  DMARxDescToGet = DMARxDescTab; 
2849
  DMAPTPRxDescToGet = DMAPTPRxDescTab;
2850
  /* Fill each DMARxDesc descriptor with the right values */
2851
  for(i=0; i < RxBuffCount; i++)
2852
  {
2853
    /* Get the pointer on the ith member of the Rx Desc list */
2854
    DMARxDesc = DMARxDescTab+i;
2855
    /* Set Own bit of the Rx descriptor Status */
2856
    DMARxDesc->Status = ETH_DMARxDesc_OWN;
2857

    
2858
    /* Set Buffer1 size and Second Address Chained bit */
2859
    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;  
2860
    /* Set Buffer1 address pointer */
2861
    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
2862
    
2863
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2864
    if(i < (RxBuffCount-1))
2865
    {
2866
      /* Set next descriptor address register with next descriptor base address */
2867
      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
2868
    }
2869
    else
2870
    {
2871
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
2872
      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
2873
    }
2874
    /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
2875
    (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
2876
    (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
2877
  }
2878
  /* Store on the last DMAPTPRxDescTab desc status record the first list address */
2879
  (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
2880

    
2881
  /* Set Receive Desciptor List Address Register */
2882
  ETH->DMARDLAR = (uint32_t) DMARxDescTab;  
2883
}
2884

    
2885
/**
2886
  * @brief  Transmits a packet, from application buffer, pointed by ppkt with 
2887
  *   Time Stamp values.
2888
  * @param ppkt: pointer to application packet buffer to transmit.
2889
  * @param FrameLength: Tx Packet size.
2890
  * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
2891
  * @retval : ETH_ERROR: in case of Tx desc owned by DMA
2892
  *   ETH_SUCCESS: for correct transmission
2893
  */
2894
uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
2895
{
2896
  uint32_t offset = 0, timeout = 0;
2897
  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
2898
  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
2899
  {
2900
    /* Return ERROR: OWN bit set */
2901
    return ETH_ERROR;
2902
  }
2903
  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
2904
  for(offset=0; offset<FrameLength; offset++)
2905
  {
2906
    (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
2907
  }
2908
  /* Setting the Frame Length: bits[12:0] */
2909
  DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
2910
  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
2911
  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
2912
  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
2913
  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
2914
  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
2915
  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
2916
  {
2917
    /* Clear TBUS ETHERNET DMA flag */
2918
    ETH->DMASR = ETH_DMASR_TBUS;
2919
    /* Resume DMA transmission*/
2920
    ETH->DMATPDR = 0;
2921
  }
2922
  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
2923
  do
2924
  {
2925
    timeout++;
2926
  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
2927
  /* Return ERROR in case of timeout */
2928
  if(timeout == PHY_READ_TO)
2929
  {
2930
    return ETH_ERROR;
2931
  }
2932
  /* Clear the DMATxDescToSet status register TTSS flag */
2933
  DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
2934
  *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
2935
  *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
2936
  /* Update the ENET DMA current descriptor */
2937
  /* Chained Mode */
2938
  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
2939
  {  
2940
    /* Selects the next DMA Tx descriptor list for next buffer read */ 
2941
    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
2942
    if(DMAPTPTxDescToSet->Status != 0)
2943
    { 
2944
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
2945
    }
2946
    else
2947
    {
2948
      DMAPTPTxDescToSet++;
2949
    }
2950
  }
2951
  else /* Ring Mode */
2952
  {  
2953
    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
2954
    {
2955
      /* Selects the next DMA Tx descriptor list for next buffer read: this will
2956
         be the first Tx descriptor in this case */
2957
      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); 
2958
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
2959
    }
2960
    else
2961
    {
2962
      /* Selects the next DMA Tx descriptor list for next buffer read */
2963
      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
2964
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
2965
    }
2966
  }
2967
  /* Return SUCCESS */
2968
  return ETH_SUCCESS;
2969
}
2970

    
2971
/**
2972
  * @brief  Receives a packet and copies it to memory pointed by ppkt with 
2973
  *   Time Stamp values.
2974
  * @param  ppkt: pointer to application packet receive buffer.  
2975
  * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
2976
  * @retval : ETH_ERROR: if there is error in reception
2977
  *   framelength: received packet size if packet reception is correct
2978
  */
2979
uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
2980
{
2981
  uint32_t offset = 0, framelength = 0;
2982
  /* Check if the descriptor is owned by the ENET or CPU */
2983
  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
2984
  {
2985
    /* Return error: OWN bit set */
2986
    return ETH_ERROR;
2987
  }
2988
  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
2989
     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
2990
     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
2991
  {
2992
    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
2993
    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
2994
    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ 
2995
    for(offset=0; offset<framelength; offset++)
2996
    {
2997
      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
2998
    }
2999
  }
3000
  else
3001
  {
3002
    /* Return ERROR */
3003
    framelength = ETH_ERROR;
3004
  }
3005
  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
3006
  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
3007
  {
3008
    /* Clear RBUS ETHERNET DMA flag */
3009
    ETH->DMASR = ETH_DMASR_RBUS;
3010
    /* Resume DMA reception */
3011
    ETH->DMARPDR = 0;
3012
  }
3013
  *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
3014
  *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
3015
  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
3016
  DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
3017
  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
3018
  /* Chained Mode */
3019
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
3020
  {
3021
    /* Selects the next DMA Rx descriptor list for next buffer read */
3022
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
3023
    if(DMAPTPRxDescToGet->Status != 0)
3024
    {
3025
      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
3026
    }
3027
    else
3028
    {
3029
      DMAPTPRxDescToGet++;
3030
    }
3031
  }
3032
  else /* Ring Mode */
3033
  {
3034
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
3035
    {
3036
      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
3037
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
3038
    }
3039
    else
3040
    {
3041
      /* Selects the next DMA Rx descriptor list for next buffer to read */
3042
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
3043
    }
3044
  }
3045
  /* Return Frame Length/ERROR */
3046
  return (framelength);
3047
}
3048
/**
3049
  * @}
3050
  */
3051

    
3052
/**
3053
  * @}
3054
  */
3055

    
3056
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/