Revision 470d0567 Target/Demo/ARMCM3_STM32F103_DiWheelDrive_GCC/Boot/main.c

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Target/Demo/ARMCM3_STM32F103_DiWheelDrive_GCC/Boot/main.c
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* You should have received a copy of the GNU General Public License along with OpenBLT.
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* If not, see <http://www.gnu.org/licenses/>.
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*
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* A special exception to the GPL is included to allow you to distribute a combined work 
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* that includes OpenBLT without being obliged to provide the source code for any 
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* A special exception to the GPL is included to allow you to distribute a combined work
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* that includes OpenBLT without being obliged to provide the source code for any
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* proprietary components. The exception text is included at the bottom of the license
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* file <license.html>.
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* 
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*
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* \endinternal
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****************************************************************************************/
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......
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#include "stm32f10x_conf.h"                      /* STM32 peripheral drivers           */
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#include "timer.h"
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#include "ARMCM3_STM32/types.h"
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#include "AMiRo/interfaces.h"
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#include "AMiRo/amiroblt.h"
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#include "AMiRo/helper.h"
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......
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void shutdownToHibernate(const blt_bool exec_disambiguation);
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void shutdownAndRestart(const blt_bool exec_disambiguation);
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volatile BlBackupRegister backup_reg;
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volatile blBackupRegister_t backup_reg;
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/****************************************************************************************
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* Callback configuration
......
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void blCallbackShutdownRestart(void);
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void blCallbackHandleShutdownRequest(void);
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const BlCallbackTable cbtable __attribute ((section ("_callback_table"))) = {
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const blCallbackTable_t cbtable __attribute__ ((section ("_callback_table"))) = {
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  .magicNumber = BL_MAGIC_NUMBER,
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  .versionMajor = BL_VERSION_MAJOR,
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  .versionMinor = BL_VERSION_MINOR,
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  .versionHotfix = 0,
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  .vBootloader = {BL_VERSION_ID_AMiRoBLT_Release, BL_VERSION_MAJOR, BL_VERSION_MINOR, 0},
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  .vSSSP = {BL_VERSION_ID_SSSP, SSSP_VERSION_MAJOR, SSSP_VERSION_MINOR, 0},
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  .vCompiler = {BL_VERSION_ID_GCC, __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__},  // currently only GCC is supported
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  .cbShutdownHibernate = blCallbackShutdownHibernate,
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  .cbShutdownDeepsleep = blCallbackShutdownDeepsleep,
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  .cbShutdownTransportation = blCallbackShutdownTransportation,
......
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/************************************************************************************//**
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** \brief     This is the entry point for the bootloader application and is called 
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** \brief     This is the entry point for the bootloader application and is called
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**            by the reset interrupt vector after the C-startup routines executed.
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** \return    Program return code.
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**
......
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/************************************************************************************//**
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** \brief     Initializes the microcontroller. 
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** \brief     Initializes the microcontroller.
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** \return    none.
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**
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****************************************************************************************/
......
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  blt_int32u pll_multiplier;
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#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0)
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  GPIO_InitTypeDef  GPIO_InitStruct;
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  USART_InitTypeDef USART_InitStruct;  
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#endif  
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  USART_InitTypeDef USART_InitStruct;
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#endif
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  /* reset the RCC clock configuration to the default reset state (for debug purpose) */
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  /* set HSION bit */
......
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  RCC->CFGR &= (blt_int32u)0xFF80FFFF;
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  /* disable all interrupts and clear pending bits  */
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  RCC->CIR = 0x009F0000;
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  /* enable HSE */    
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  /* enable HSE */
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  RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
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  /* wait till HSE is ready and if Time out is reached exit */
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  do
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  {
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    HSEStatus = RCC->CR & RCC_CR_HSERDY;
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    StartUpCounter++;  
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  } 
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    StartUpCounter++;
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  }
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  while((HSEStatus == 0) && (StartUpCounter != 1500));
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  /* check if time out was reached */
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  if ((RCC->CR & RCC_CR_HSERDY) == RESET)
......
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  FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
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#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
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  /* configure 2 flash wait states */
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  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;    
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#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)  
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  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
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#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
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  /* configure 1 flash wait states */
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  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;    
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  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
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#endif
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  /* HCLK = SYSCLK */
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  RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
......
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  }
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  /* select PLL as system clock source */
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  RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
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  RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;    
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  RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
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  /* wait till PLL is used as system clock source */
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  while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
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  {

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