amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_dma.h @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_dma.h
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4 | * @author MCD Application Team
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5 | * @version V1.1.0
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6 | * @date 11-January-2013
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7 | * @brief This file contains all the functions prototypes for the DMA firmware
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8 | * library.
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9 | ******************************************************************************
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10 | * @attention
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11 | *
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12 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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13 | *
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14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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15 | * You may not use this file except in compliance with the License.
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16 | * You may obtain a copy of the License at:
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17 | *
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18 | * http://www.st.com/software_license_agreement_liberty_v2
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19 | *
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20 | * Unless required by applicable law or agreed to in writing, software
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21 | * distributed under the License is distributed on an "AS IS" BASIS,
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22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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23 | * See the License for the specific language governing permissions and
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24 | * limitations under the License.
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25 | *
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26 | ******************************************************************************
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27 | */
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28 | |||
29 | /* Define to prevent recursive inclusion -------------------------------------*/
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30 | #ifndef __STM32F4xx_DMA_H
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31 | #define __STM32F4xx_DMA_H
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32 | |||
33 | #ifdef __cplusplus
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34 | extern "C" { |
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35 | #endif
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36 | |||
37 | /* Includes ------------------------------------------------------------------*/
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38 | #include "stm32f4xx.h" |
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39 | |||
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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41 | * @{
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42 | */
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43 | |||
44 | /** @addtogroup DMA
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45 | * @{
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46 | */
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47 | |||
48 | /* Exported types ------------------------------------------------------------*/
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49 | |||
50 | /**
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51 | * @brief DMA Init structure definition
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52 | */
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53 | |||
54 | typedef struct |
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55 | { |
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56 | uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
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57 | This parameter can be a value of @ref DMA_channel */
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58 | |||
59 | uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
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60 | |||
61 | uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
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62 | This memory is the default memory used when double buffer mode is
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63 | not enabled. */
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64 | |||
65 | uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
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66 | from memory to memory or from peripheral to memory.
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67 | This parameter can be a value of @ref DMA_data_transfer_direction */
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68 | |||
69 | uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
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70 | The data unit is equal to the configuration set in DMA_PeripheralDataSize
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71 | or DMA_MemoryDataSize members depending in the transfer direction. */
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72 | |||
73 | uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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74 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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75 | |||
76 | uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
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77 | This parameter can be a value of @ref DMA_memory_incremented_mode */
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78 | |||
79 | uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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80 | This parameter can be a value of @ref DMA_peripheral_data_size */
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81 | |||
82 | uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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83 | This parameter can be a value of @ref DMA_memory_data_size */
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84 | |||
85 | uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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86 | This parameter can be a value of @ref DMA_circular_normal_mode
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87 | @note The circular buffer mode cannot be used if the memory-to-memory
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88 | data transfer is configured on the selected Stream */
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89 | |||
90 | uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
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91 | This parameter can be a value of @ref DMA_priority_level */
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92 | |||
93 | uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
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94 | This parameter can be a value of @ref DMA_fifo_direct_mode
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95 | @note The Direct mode (FIFO mode disabled) cannot be used if the
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96 | memory-to-memory data transfer is configured on the selected Stream */
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97 | |||
98 | uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
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99 | This parameter can be a value of @ref DMA_fifo_threshold_level */
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100 | |||
101 | uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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102 | It specifies the amount of data to be transferred in a single non interruptable
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103 | transaction. This parameter can be a value of @ref DMA_memory_burst
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104 | @note The burst mode is possible only if the address Increment mode is enabled. */
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105 | |||
106 | uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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107 | It specifies the amount of data to be transferred in a single non interruptable
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108 | transaction. This parameter can be a value of @ref DMA_peripheral_burst
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109 | @note The burst mode is possible only if the address Increment mode is enabled. */
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110 | }DMA_InitTypeDef; |
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111 | |||
112 | /* Exported constants --------------------------------------------------------*/
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113 | |||
114 | /** @defgroup DMA_Exported_Constants
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115 | * @{
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116 | */
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117 | |||
118 | #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
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119 | ((PERIPH) == DMA1_Stream1) || \ |
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120 | ((PERIPH) == DMA1_Stream2) || \ |
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121 | ((PERIPH) == DMA1_Stream3) || \ |
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122 | ((PERIPH) == DMA1_Stream4) || \ |
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123 | ((PERIPH) == DMA1_Stream5) || \ |
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124 | ((PERIPH) == DMA1_Stream6) || \ |
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125 | ((PERIPH) == DMA1_Stream7) || \ |
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126 | ((PERIPH) == DMA2_Stream0) || \ |
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127 | ((PERIPH) == DMA2_Stream1) || \ |
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128 | ((PERIPH) == DMA2_Stream2) || \ |
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129 | ((PERIPH) == DMA2_Stream3) || \ |
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130 | ((PERIPH) == DMA2_Stream4) || \ |
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131 | ((PERIPH) == DMA2_Stream5) || \ |
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132 | ((PERIPH) == DMA2_Stream6) || \ |
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133 | ((PERIPH) == DMA2_Stream7)) |
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134 | |||
135 | #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
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136 | ((CONTROLLER) == DMA2)) |
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137 | |||
138 | /** @defgroup DMA_channel
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139 | * @{
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140 | */
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141 | #define DMA_Channel_0 ((uint32_t)0x00000000) |
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142 | #define DMA_Channel_1 ((uint32_t)0x02000000) |
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143 | #define DMA_Channel_2 ((uint32_t)0x04000000) |
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144 | #define DMA_Channel_3 ((uint32_t)0x06000000) |
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145 | #define DMA_Channel_4 ((uint32_t)0x08000000) |
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146 | #define DMA_Channel_5 ((uint32_t)0x0A000000) |
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147 | #define DMA_Channel_6 ((uint32_t)0x0C000000) |
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148 | #define DMA_Channel_7 ((uint32_t)0x0E000000) |
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149 | |||
150 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
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151 | ((CHANNEL) == DMA_Channel_1) || \ |
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152 | ((CHANNEL) == DMA_Channel_2) || \ |
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153 | ((CHANNEL) == DMA_Channel_3) || \ |
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154 | ((CHANNEL) == DMA_Channel_4) || \ |
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155 | ((CHANNEL) == DMA_Channel_5) || \ |
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156 | ((CHANNEL) == DMA_Channel_6) || \ |
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157 | ((CHANNEL) == DMA_Channel_7)) |
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158 | /**
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159 | * @}
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160 | */
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161 | |||
162 | |||
163 | /** @defgroup DMA_data_transfer_direction
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164 | * @{
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165 | */
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166 | #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) |
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167 | #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) |
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168 | #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) |
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169 | |||
170 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
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171 | ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ |
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172 | ((DIRECTION) == DMA_DIR_MemoryToMemory)) |
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173 | /**
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174 | * @}
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175 | */
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176 | |||
177 | |||
178 | /** @defgroup DMA_data_buffer_size
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179 | * @{
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180 | */
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181 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
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182 | /**
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183 | * @}
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184 | */
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185 | |||
186 | |||
187 | /** @defgroup DMA_peripheral_incremented_mode
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188 | * @{
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189 | */
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190 | #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) |
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191 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
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192 | |||
193 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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194 | ((STATE) == DMA_PeripheralInc_Disable)) |
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195 | /**
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196 | * @}
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197 | */
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198 | |||
199 | |||
200 | /** @defgroup DMA_memory_incremented_mode
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201 | * @{
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202 | */
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203 | #define DMA_MemoryInc_Enable ((uint32_t)0x00000400) |
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204 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
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205 | |||
206 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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207 | ((STATE) == DMA_MemoryInc_Disable)) |
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208 | /**
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209 | * @}
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210 | */
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211 | |||
212 | |||
213 | /** @defgroup DMA_peripheral_data_size
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214 | * @{
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215 | */
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216 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
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217 | #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) |
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218 | #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) |
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219 | |||
220 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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221 | ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ |
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222 | ((SIZE) == DMA_PeripheralDataSize_Word)) |
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223 | /**
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224 | * @}
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225 | */
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226 | |||
227 | |||
228 | /** @defgroup DMA_memory_data_size
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229 | * @{
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230 | */
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231 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
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232 | #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) |
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233 | #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) |
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234 | |||
235 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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236 | ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ |
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237 | ((SIZE) == DMA_MemoryDataSize_Word )) |
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238 | /**
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239 | * @}
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240 | */
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241 | |||
242 | |||
243 | /** @defgroup DMA_circular_normal_mode
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244 | * @{
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245 | */
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246 | #define DMA_Mode_Normal ((uint32_t)0x00000000) |
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247 | #define DMA_Mode_Circular ((uint32_t)0x00000100) |
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248 | |||
249 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
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250 | ((MODE) == DMA_Mode_Circular)) |
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251 | /**
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252 | * @}
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253 | */
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254 | |||
255 | |||
256 | /** @defgroup DMA_priority_level
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257 | * @{
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258 | */
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259 | #define DMA_Priority_Low ((uint32_t)0x00000000) |
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260 | #define DMA_Priority_Medium ((uint32_t)0x00010000) |
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261 | #define DMA_Priority_High ((uint32_t)0x00020000) |
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262 | #define DMA_Priority_VeryHigh ((uint32_t)0x00030000) |
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263 | |||
264 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
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265 | ((PRIORITY) == DMA_Priority_Medium) || \ |
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266 | ((PRIORITY) == DMA_Priority_High) || \ |
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267 | ((PRIORITY) == DMA_Priority_VeryHigh)) |
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268 | /**
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269 | * @}
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270 | */
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271 | |||
272 | |||
273 | /** @defgroup DMA_fifo_direct_mode
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274 | * @{
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275 | */
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276 | #define DMA_FIFOMode_Disable ((uint32_t)0x00000000) |
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277 | #define DMA_FIFOMode_Enable ((uint32_t)0x00000004) |
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278 | |||
279 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
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280 | ((STATE) == DMA_FIFOMode_Enable)) |
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281 | /**
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282 | * @}
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283 | */
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284 | |||
285 | |||
286 | /** @defgroup DMA_fifo_threshold_level
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287 | * @{
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288 | */
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289 | #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) |
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290 | #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) |
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291 | #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) |
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292 | #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) |
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293 | |||
294 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
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295 | ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ |
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296 | ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ |
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297 | ((THRESHOLD) == DMA_FIFOThreshold_Full)) |
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298 | /**
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299 | * @}
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300 | */
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301 | |||
302 | |||
303 | /** @defgroup DMA_memory_burst
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304 | * @{
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305 | */
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306 | #define DMA_MemoryBurst_Single ((uint32_t)0x00000000) |
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307 | #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) |
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308 | #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) |
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309 | #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) |
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310 | |||
311 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
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312 | ((BURST) == DMA_MemoryBurst_INC4) || \ |
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313 | ((BURST) == DMA_MemoryBurst_INC8) || \ |
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314 | ((BURST) == DMA_MemoryBurst_INC16)) |
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315 | /**
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316 | * @}
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317 | */
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318 | |||
319 | |||
320 | /** @defgroup DMA_peripheral_burst
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321 | * @{
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322 | */
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323 | #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) |
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324 | #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) |
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325 | #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) |
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326 | #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) |
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327 | |||
328 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
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329 | ((BURST) == DMA_PeripheralBurst_INC4) || \ |
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330 | ((BURST) == DMA_PeripheralBurst_INC8) || \ |
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331 | ((BURST) == DMA_PeripheralBurst_INC16)) |
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332 | /**
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333 | * @}
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334 | */
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335 | |||
336 | |||
337 | /** @defgroup DMA_fifo_status_level
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338 | * @{
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339 | */
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340 | #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) |
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341 | #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) |
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342 | #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) |
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343 | #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) |
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344 | #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) |
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345 | #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) |
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346 | |||
347 | #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
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348 | ((STATUS) == DMA_FIFOStatus_HalfFull) || \ |
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349 | ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ |
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350 | ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ |
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351 | ((STATUS) == DMA_FIFOStatus_Full) || \ |
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352 | ((STATUS) == DMA_FIFOStatus_Empty)) |
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353 | /**
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354 | * @}
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355 | */
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356 | |||
357 | /** @defgroup DMA_flags_definition
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358 | * @{
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359 | */
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360 | #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) |
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361 | #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) |
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362 | #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) |
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363 | #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) |
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364 | #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) |
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365 | #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) |
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366 | #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) |
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367 | #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) |
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368 | #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) |
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369 | #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) |
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370 | #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) |
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371 | #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) |
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372 | #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) |
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373 | #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) |
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374 | #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) |
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375 | #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) |
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376 | #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) |
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377 | #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) |
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378 | #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) |
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379 | #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) |
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380 | #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) |
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381 | #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) |
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382 | #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) |
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383 | #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) |
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384 | #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) |
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385 | #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) |
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386 | #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) |
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387 | #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) |
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388 | #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) |
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389 | #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) |
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390 | #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) |
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391 | #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) |
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392 | #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) |
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393 | #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) |
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394 | #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) |
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395 | #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) |
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396 | #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) |
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397 | #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) |
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398 | #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) |
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399 | #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) |
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400 | |||
401 | #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ |
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402 | (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) |
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403 | |||
404 | #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
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405 | ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ |
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406 | ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ |
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407 | ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ |
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408 | ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ |
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409 | ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ |
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410 | ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ |
||
411 | ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ |
||
412 | ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ |
||
413 | ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ |
||
414 | ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ |
||
415 | ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ |
||
416 | ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ |
||
417 | ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ |
||
418 | ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ |
||
419 | ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ |
||
420 | ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ |
||
421 | ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ |
||
422 | ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ |
||
423 | ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) |
||
424 | /**
|
||
425 | * @}
|
||
426 | */
|
||
427 | |||
428 | |||
429 | /** @defgroup DMA_interrupt_enable_definitions
|
||
430 | * @{
|
||
431 | */
|
||
432 | #define DMA_IT_TC ((uint32_t)0x00000010) |
||
433 | #define DMA_IT_HT ((uint32_t)0x00000008) |
||
434 | #define DMA_IT_TE ((uint32_t)0x00000004) |
||
435 | #define DMA_IT_DME ((uint32_t)0x00000002) |
||
436 | #define DMA_IT_FE ((uint32_t)0x00000080) |
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437 | |||
438 | #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) |
||
439 | /**
|
||
440 | * @}
|
||
441 | */
|
||
442 | |||
443 | |||
444 | /** @defgroup DMA_interrupts_definitions
|
||
445 | * @{
|
||
446 | */
|
||
447 | #define DMA_IT_FEIF0 ((uint32_t)0x90000001) |
||
448 | #define DMA_IT_DMEIF0 ((uint32_t)0x10001004) |
||
449 | #define DMA_IT_TEIF0 ((uint32_t)0x10002008) |
||
450 | #define DMA_IT_HTIF0 ((uint32_t)0x10004010) |
||
451 | #define DMA_IT_TCIF0 ((uint32_t)0x10008020) |
||
452 | #define DMA_IT_FEIF1 ((uint32_t)0x90000040) |
||
453 | #define DMA_IT_DMEIF1 ((uint32_t)0x10001100) |
||
454 | #define DMA_IT_TEIF1 ((uint32_t)0x10002200) |
||
455 | #define DMA_IT_HTIF1 ((uint32_t)0x10004400) |
||
456 | #define DMA_IT_TCIF1 ((uint32_t)0x10008800) |
||
457 | #define DMA_IT_FEIF2 ((uint32_t)0x90010000) |
||
458 | #define DMA_IT_DMEIF2 ((uint32_t)0x10041000) |
||
459 | #define DMA_IT_TEIF2 ((uint32_t)0x10082000) |
||
460 | #define DMA_IT_HTIF2 ((uint32_t)0x10104000) |
||
461 | #define DMA_IT_TCIF2 ((uint32_t)0x10208000) |
||
462 | #define DMA_IT_FEIF3 ((uint32_t)0x90400000) |
||
463 | #define DMA_IT_DMEIF3 ((uint32_t)0x11001000) |
||
464 | #define DMA_IT_TEIF3 ((uint32_t)0x12002000) |
||
465 | #define DMA_IT_HTIF3 ((uint32_t)0x14004000) |
||
466 | #define DMA_IT_TCIF3 ((uint32_t)0x18008000) |
||
467 | #define DMA_IT_FEIF4 ((uint32_t)0xA0000001) |
||
468 | #define DMA_IT_DMEIF4 ((uint32_t)0x20001004) |
||
469 | #define DMA_IT_TEIF4 ((uint32_t)0x20002008) |
||
470 | #define DMA_IT_HTIF4 ((uint32_t)0x20004010) |
||
471 | #define DMA_IT_TCIF4 ((uint32_t)0x20008020) |
||
472 | #define DMA_IT_FEIF5 ((uint32_t)0xA0000040) |
||
473 | #define DMA_IT_DMEIF5 ((uint32_t)0x20001100) |
||
474 | #define DMA_IT_TEIF5 ((uint32_t)0x20002200) |
||
475 | #define DMA_IT_HTIF5 ((uint32_t)0x20004400) |
||
476 | #define DMA_IT_TCIF5 ((uint32_t)0x20008800) |
||
477 | #define DMA_IT_FEIF6 ((uint32_t)0xA0010000) |
||
478 | #define DMA_IT_DMEIF6 ((uint32_t)0x20041000) |
||
479 | #define DMA_IT_TEIF6 ((uint32_t)0x20082000) |
||
480 | #define DMA_IT_HTIF6 ((uint32_t)0x20104000) |
||
481 | #define DMA_IT_TCIF6 ((uint32_t)0x20208000) |
||
482 | #define DMA_IT_FEIF7 ((uint32_t)0xA0400000) |
||
483 | #define DMA_IT_DMEIF7 ((uint32_t)0x21001000) |
||
484 | #define DMA_IT_TEIF7 ((uint32_t)0x22002000) |
||
485 | #define DMA_IT_HTIF7 ((uint32_t)0x24004000) |
||
486 | #define DMA_IT_TCIF7 ((uint32_t)0x28008000) |
||
487 | |||
488 | #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ |
||
489 | (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ |
||
490 | (((IT) & 0x40820082) == 0x00)) |
||
491 | |||
492 | #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
|
||
493 | ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ |
||
494 | ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ |
||
495 | ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ |
||
496 | ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ |
||
497 | ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ |
||
498 | ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ |
||
499 | ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ |
||
500 | ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ |
||
501 | ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ |
||
502 | ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ |
||
503 | ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ |
||
504 | ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ |
||
505 | ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ |
||
506 | ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ |
||
507 | ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ |
||
508 | ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ |
||
509 | ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ |
||
510 | ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ |
||
511 | ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) |
||
512 | /**
|
||
513 | * @}
|
||
514 | */
|
||
515 | |||
516 | |||
517 | /** @defgroup DMA_peripheral_increment_offset
|
||
518 | * @{
|
||
519 | */
|
||
520 | #define DMA_PINCOS_Psize ((uint32_t)0x00000000) |
||
521 | #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) |
||
522 | |||
523 | #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
|
||
524 | ((SIZE) == DMA_PINCOS_WordAligned)) |
||
525 | /**
|
||
526 | * @}
|
||
527 | */
|
||
528 | |||
529 | |||
530 | /** @defgroup DMA_flow_controller_definitions
|
||
531 | * @{
|
||
532 | */
|
||
533 | #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) |
||
534 | #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) |
||
535 | |||
536 | #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
|
||
537 | ((CTRL) == DMA_FlowCtrl_Peripheral)) |
||
538 | /**
|
||
539 | * @}
|
||
540 | */
|
||
541 | |||
542 | |||
543 | /** @defgroup DMA_memory_targets_definitions
|
||
544 | * @{
|
||
545 | */
|
||
546 | #define DMA_Memory_0 ((uint32_t)0x00000000) |
||
547 | #define DMA_Memory_1 ((uint32_t)0x00080000) |
||
548 | |||
549 | #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
|
||
550 | /**
|
||
551 | * @}
|
||
552 | */
|
||
553 | |||
554 | /**
|
||
555 | * @}
|
||
556 | */
|
||
557 | |||
558 | /* Exported macro ------------------------------------------------------------*/
|
||
559 | /* Exported functions --------------------------------------------------------*/
|
||
560 | |||
561 | /* Function used to set the DMA configuration to the default reset state *****/
|
||
562 | void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
|
||
563 | |||
564 | /* Initialization and Configuration functions *********************************/
|
||
565 | void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
|
||
566 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||
567 | void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||
568 | |||
569 | /* Optional Configuration functions *******************************************/
|
||
570 | void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
|
||
571 | void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
|
||
572 | |||
573 | /* Data Counter functions *****************************************************/
|
||
574 | void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
|
||
575 | uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); |
||
576 | |||
577 | /* Double Buffer mode functions ***********************************************/
|
||
578 | void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
|
||
579 | uint32_t DMA_CurrentMemory); |
||
580 | void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||
581 | void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
|
||
582 | uint32_t DMA_MemoryTarget); |
||
583 | uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); |
||
584 | |||
585 | /* Interrupts and flags management functions **********************************/
|
||
586 | FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); |
||
587 | uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); |
||
588 | FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); |
||
589 | void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
||
590 | void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
|
||
591 | ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); |
||
592 | void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
||
593 | |||
594 | #ifdef __cplusplus
|
||
595 | } |
||
596 | #endif
|
||
597 | |||
598 | #endif /*__STM32F4xx_DMA_H */ |
||
599 | |||
600 | /**
|
||
601 | * @}
|
||
602 | */
|
||
603 | |||
604 | /**
|
||
605 | * @}
|
||
606 | */
|
||
607 | |||
608 | |||
609 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|