amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_dma.h @ 69661903
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/**
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******************************************************************************
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* @file stm32f4xx_dma.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 11-January-2013
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* @brief This file contains all the functions prototypes for the DMA firmware
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* library.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_DMA_H
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#define __STM32F4xx_DMA_H
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#ifdef __cplusplus
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extern "C" { |
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h" |
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief DMA Init structure definition
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*/
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typedef struct |
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{
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uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
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This parameter can be a value of @ref DMA_channel */
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uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
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uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
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This memory is the default memory used when double buffer mode is
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not enabled. */
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uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
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from memory to memory or from peripheral to memory.
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This parameter can be a value of @ref DMA_data_transfer_direction */
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uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
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The data unit is equal to the configuration set in DMA_PeripheralDataSize
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or DMA_MemoryDataSize members depending in the transfer direction. */
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uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
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This parameter can be a value of @ref DMA_memory_incremented_mode */
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uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_peripheral_data_size */
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uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_memory_data_size */
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uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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This parameter can be a value of @ref DMA_circular_normal_mode
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@note The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Stream */
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uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
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This parameter can be a value of @ref DMA_priority_level */
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uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
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This parameter can be a value of @ref DMA_fifo_direct_mode
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@note The Direct mode (FIFO mode disabled) cannot be used if the
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memory-to-memory data transfer is configured on the selected Stream */
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uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
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This parameter can be a value of @ref DMA_fifo_threshold_level */
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uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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It specifies the amount of data to be transferred in a single non interruptable
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transaction. This parameter can be a value of @ref DMA_memory_burst
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@note The burst mode is possible only if the address Increment mode is enabled. */
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uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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It specifies the amount of data to be transferred in a single non interruptable
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transaction. This parameter can be a value of @ref DMA_peripheral_burst
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@note The burst mode is possible only if the address Increment mode is enabled. */
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}DMA_InitTypeDef; |
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants
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* @{
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*/
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#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
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((PERIPH) == DMA1_Stream1) || \ |
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((PERIPH) == DMA1_Stream2) || \ |
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((PERIPH) == DMA1_Stream3) || \ |
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((PERIPH) == DMA1_Stream4) || \ |
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((PERIPH) == DMA1_Stream5) || \ |
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((PERIPH) == DMA1_Stream6) || \ |
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((PERIPH) == DMA1_Stream7) || \ |
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((PERIPH) == DMA2_Stream0) || \ |
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((PERIPH) == DMA2_Stream1) || \ |
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((PERIPH) == DMA2_Stream2) || \ |
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((PERIPH) == DMA2_Stream3) || \ |
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((PERIPH) == DMA2_Stream4) || \ |
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((PERIPH) == DMA2_Stream5) || \ |
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((PERIPH) == DMA2_Stream6) || \ |
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((PERIPH) == DMA2_Stream7)) |
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#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
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((CONTROLLER) == DMA2)) |
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/** @defgroup DMA_channel
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* @{
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*/
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#define DMA_Channel_0 ((uint32_t)0x00000000) |
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#define DMA_Channel_1 ((uint32_t)0x02000000) |
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#define DMA_Channel_2 ((uint32_t)0x04000000) |
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#define DMA_Channel_3 ((uint32_t)0x06000000) |
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#define DMA_Channel_4 ((uint32_t)0x08000000) |
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#define DMA_Channel_5 ((uint32_t)0x0A000000) |
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#define DMA_Channel_6 ((uint32_t)0x0C000000) |
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#define DMA_Channel_7 ((uint32_t)0x0E000000) |
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#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
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((CHANNEL) == DMA_Channel_1) || \ |
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((CHANNEL) == DMA_Channel_2) || \ |
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((CHANNEL) == DMA_Channel_3) || \ |
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((CHANNEL) == DMA_Channel_4) || \ |
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((CHANNEL) == DMA_Channel_5) || \ |
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((CHANNEL) == DMA_Channel_6) || \ |
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((CHANNEL) == DMA_Channel_7)) |
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/**
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* @}
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*/
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/** @defgroup DMA_data_transfer_direction
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* @{
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*/
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#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) |
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#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) |
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#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) |
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#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
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((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ |
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((DIRECTION) == DMA_DIR_MemoryToMemory)) |
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/**
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* @}
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*/
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/** @defgroup DMA_data_buffer_size
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* @{
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*/
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#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_incremented_mode
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* @{
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*/
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#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) |
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#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
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#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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((STATE) == DMA_PeripheralInc_Disable)) |
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/**
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* @}
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*/
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/** @defgroup DMA_memory_incremented_mode
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* @{
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*/
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#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) |
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#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
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#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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((STATE) == DMA_MemoryInc_Disable)) |
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_data_size
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* @{
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*/
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#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
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#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) |
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#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) |
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#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ |
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((SIZE) == DMA_PeripheralDataSize_Word)) |
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/**
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* @}
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*/
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/** @defgroup DMA_memory_data_size
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* @{
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*/
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#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
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#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) |
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#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) |
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#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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((SIZE) == DMA_MemoryDataSize_HalfWord) || \ |
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((SIZE) == DMA_MemoryDataSize_Word )) |
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/**
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* @}
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*/
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/** @defgroup DMA_circular_normal_mode
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* @{
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*/
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#define DMA_Mode_Normal ((uint32_t)0x00000000) |
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#define DMA_Mode_Circular ((uint32_t)0x00000100) |
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
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((MODE) == DMA_Mode_Circular)) |
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/**
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* @}
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*/
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/** @defgroup DMA_priority_level
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* @{
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*/
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#define DMA_Priority_Low ((uint32_t)0x00000000) |
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#define DMA_Priority_Medium ((uint32_t)0x00010000) |
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#define DMA_Priority_High ((uint32_t)0x00020000) |
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#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) |
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#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
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((PRIORITY) == DMA_Priority_Medium) || \ |
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((PRIORITY) == DMA_Priority_High) || \ |
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((PRIORITY) == DMA_Priority_VeryHigh)) |
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/**
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* @}
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*/
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/** @defgroup DMA_fifo_direct_mode
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* @{
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*/
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#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) |
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#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) |
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#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
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((STATE) == DMA_FIFOMode_Enable)) |
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/**
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* @}
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*/
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/** @defgroup DMA_fifo_threshold_level
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* @{
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*/
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#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) |
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#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) |
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#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) |
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#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) |
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#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
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((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ |
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((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ |
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((THRESHOLD) == DMA_FIFOThreshold_Full)) |
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/**
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* @}
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*/
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/** @defgroup DMA_memory_burst
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* @{
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*/
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#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) |
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#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) |
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#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) |
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#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) |
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#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
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((BURST) == DMA_MemoryBurst_INC4) || \ |
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((BURST) == DMA_MemoryBurst_INC8) || \ |
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((BURST) == DMA_MemoryBurst_INC16)) |
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_burst
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* @{
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*/
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#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) |
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#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) |
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#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) |
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#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) |
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#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
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((BURST) == DMA_PeripheralBurst_INC4) || \ |
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((BURST) == DMA_PeripheralBurst_INC8) || \ |
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((BURST) == DMA_PeripheralBurst_INC16)) |
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/**
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* @}
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*/
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/** @defgroup DMA_fifo_status_level
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* @{
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*/
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#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) |
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#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) |
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#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) |
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#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) |
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#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) |
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#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) |
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#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
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((STATUS) == DMA_FIFOStatus_HalfFull) || \ |
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((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ |
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((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ |
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((STATUS) == DMA_FIFOStatus_Full) || \ |
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((STATUS) == DMA_FIFOStatus_Empty)) |
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/**
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* @}
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*/
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/** @defgroup DMA_flags_definition
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* @{
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*/
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#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) |
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#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) |
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#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) |
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#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) |
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#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) |
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#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) |
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#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) |
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#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) |
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#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) |
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#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) |
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#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) |
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#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) |
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#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) |
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#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) |
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#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) |
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#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) |
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#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) |
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#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) |
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#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) |
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#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) |
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#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) |
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#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) |
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#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) |
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#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) |
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#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) |
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#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) |
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#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) |
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#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) |
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#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) |
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#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) |
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#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) |
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#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) |
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#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) |
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#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) |
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#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) |
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#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) |
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#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) |
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#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) |
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#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) |
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#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) |
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#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ |
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(((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) |
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#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
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((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ |
| 406 |
((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ |
| 407 |
((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ |
| 408 |
((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ |
| 409 |
((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ |
| 410 |
((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ |
| 411 |
((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ |
| 412 |
((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ |
| 413 |
((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ |
| 414 |
((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ |
| 415 |
((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ |
| 416 |
((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ |
| 417 |
((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ |
| 418 |
((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ |
| 419 |
((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ |
| 420 |
((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ |
| 421 |
((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ |
| 422 |
((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ |
| 423 |
((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) |
| 424 |
/**
|
| 425 |
* @}
|
| 426 |
*/
|
| 427 |
|
| 428 |
|
| 429 |
/** @defgroup DMA_interrupt_enable_definitions
|
| 430 |
* @{
|
| 431 |
*/
|
| 432 |
#define DMA_IT_TC ((uint32_t)0x00000010) |
| 433 |
#define DMA_IT_HT ((uint32_t)0x00000008) |
| 434 |
#define DMA_IT_TE ((uint32_t)0x00000004) |
| 435 |
#define DMA_IT_DME ((uint32_t)0x00000002) |
| 436 |
#define DMA_IT_FE ((uint32_t)0x00000080) |
| 437 |
|
| 438 |
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) |
| 439 |
/**
|
| 440 |
* @}
|
| 441 |
*/
|
| 442 |
|
| 443 |
|
| 444 |
/** @defgroup DMA_interrupts_definitions
|
| 445 |
* @{
|
| 446 |
*/
|
| 447 |
#define DMA_IT_FEIF0 ((uint32_t)0x90000001) |
| 448 |
#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) |
| 449 |
#define DMA_IT_TEIF0 ((uint32_t)0x10002008) |
| 450 |
#define DMA_IT_HTIF0 ((uint32_t)0x10004010) |
| 451 |
#define DMA_IT_TCIF0 ((uint32_t)0x10008020) |
| 452 |
#define DMA_IT_FEIF1 ((uint32_t)0x90000040) |
| 453 |
#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) |
| 454 |
#define DMA_IT_TEIF1 ((uint32_t)0x10002200) |
| 455 |
#define DMA_IT_HTIF1 ((uint32_t)0x10004400) |
| 456 |
#define DMA_IT_TCIF1 ((uint32_t)0x10008800) |
| 457 |
#define DMA_IT_FEIF2 ((uint32_t)0x90010000) |
| 458 |
#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) |
| 459 |
#define DMA_IT_TEIF2 ((uint32_t)0x10082000) |
| 460 |
#define DMA_IT_HTIF2 ((uint32_t)0x10104000) |
| 461 |
#define DMA_IT_TCIF2 ((uint32_t)0x10208000) |
| 462 |
#define DMA_IT_FEIF3 ((uint32_t)0x90400000) |
| 463 |
#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) |
| 464 |
#define DMA_IT_TEIF3 ((uint32_t)0x12002000) |
| 465 |
#define DMA_IT_HTIF3 ((uint32_t)0x14004000) |
| 466 |
#define DMA_IT_TCIF3 ((uint32_t)0x18008000) |
| 467 |
#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) |
| 468 |
#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) |
| 469 |
#define DMA_IT_TEIF4 ((uint32_t)0x20002008) |
| 470 |
#define DMA_IT_HTIF4 ((uint32_t)0x20004010) |
| 471 |
#define DMA_IT_TCIF4 ((uint32_t)0x20008020) |
| 472 |
#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) |
| 473 |
#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) |
| 474 |
#define DMA_IT_TEIF5 ((uint32_t)0x20002200) |
| 475 |
#define DMA_IT_HTIF5 ((uint32_t)0x20004400) |
| 476 |
#define DMA_IT_TCIF5 ((uint32_t)0x20008800) |
| 477 |
#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) |
| 478 |
#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) |
| 479 |
#define DMA_IT_TEIF6 ((uint32_t)0x20082000) |
| 480 |
#define DMA_IT_HTIF6 ((uint32_t)0x20104000) |
| 481 |
#define DMA_IT_TCIF6 ((uint32_t)0x20208000) |
| 482 |
#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) |
| 483 |
#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) |
| 484 |
#define DMA_IT_TEIF7 ((uint32_t)0x22002000) |
| 485 |
#define DMA_IT_HTIF7 ((uint32_t)0x24004000) |
| 486 |
#define DMA_IT_TCIF7 ((uint32_t)0x28008000) |
| 487 |
|
| 488 |
#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ |
| 489 |
(((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ |
| 490 |
(((IT) & 0x40820082) == 0x00)) |
| 491 |
|
| 492 |
#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
|
| 493 |
((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ |
| 494 |
((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ |
| 495 |
((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ |
| 496 |
((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ |
| 497 |
((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ |
| 498 |
((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ |
| 499 |
((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ |
| 500 |
((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ |
| 501 |
((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ |
| 502 |
((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ |
| 503 |
((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ |
| 504 |
((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ |
| 505 |
((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ |
| 506 |
((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ |
| 507 |
((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ |
| 508 |
((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ |
| 509 |
((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ |
| 510 |
((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ |
| 511 |
((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) |
| 512 |
/**
|
| 513 |
* @}
|
| 514 |
*/
|
| 515 |
|
| 516 |
|
| 517 |
/** @defgroup DMA_peripheral_increment_offset
|
| 518 |
* @{
|
| 519 |
*/
|
| 520 |
#define DMA_PINCOS_Psize ((uint32_t)0x00000000) |
| 521 |
#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) |
| 522 |
|
| 523 |
#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
|
| 524 |
((SIZE) == DMA_PINCOS_WordAligned)) |
| 525 |
/**
|
| 526 |
* @}
|
| 527 |
*/
|
| 528 |
|
| 529 |
|
| 530 |
/** @defgroup DMA_flow_controller_definitions
|
| 531 |
* @{
|
| 532 |
*/
|
| 533 |
#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) |
| 534 |
#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) |
| 535 |
|
| 536 |
#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
|
| 537 |
((CTRL) == DMA_FlowCtrl_Peripheral)) |
| 538 |
/**
|
| 539 |
* @}
|
| 540 |
*/
|
| 541 |
|
| 542 |
|
| 543 |
/** @defgroup DMA_memory_targets_definitions
|
| 544 |
* @{
|
| 545 |
*/
|
| 546 |
#define DMA_Memory_0 ((uint32_t)0x00000000) |
| 547 |
#define DMA_Memory_1 ((uint32_t)0x00080000) |
| 548 |
|
| 549 |
#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
|
| 550 |
/**
|
| 551 |
* @}
|
| 552 |
*/
|
| 553 |
|
| 554 |
/**
|
| 555 |
* @}
|
| 556 |
*/
|
| 557 |
|
| 558 |
/* Exported macro ------------------------------------------------------------*/
|
| 559 |
/* Exported functions --------------------------------------------------------*/
|
| 560 |
|
| 561 |
/* Function used to set the DMA configuration to the default reset state *****/
|
| 562 |
void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
|
| 563 |
|
| 564 |
/* Initialization and Configuration functions *********************************/
|
| 565 |
void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
|
| 566 |
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
| 567 |
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
| 568 |
|
| 569 |
/* Optional Configuration functions *******************************************/
|
| 570 |
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
|
| 571 |
void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
|
| 572 |
|
| 573 |
/* Data Counter functions *****************************************************/
|
| 574 |
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
|
| 575 |
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); |
| 576 |
|
| 577 |
/* Double Buffer mode functions ***********************************************/
|
| 578 |
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
|
| 579 |
uint32_t DMA_CurrentMemory); |
| 580 |
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
| 581 |
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
|
| 582 |
uint32_t DMA_MemoryTarget); |
| 583 |
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); |
| 584 |
|
| 585 |
/* Interrupts and flags management functions **********************************/
|
| 586 |
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); |
| 587 |
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); |
| 588 |
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); |
| 589 |
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
| 590 |
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
|
| 591 |
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); |
| 592 |
void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
| 593 |
|
| 594 |
#ifdef __cplusplus
|
| 595 |
} |
| 596 |
#endif
|
| 597 |
|
| 598 |
#endif /*__STM32F4xx_DMA_H */ |
| 599 |
|
| 600 |
/**
|
| 601 |
* @}
|
| 602 |
*/
|
| 603 |
|
| 604 |
/**
|
| 605 |
* @}
|
| 606 |
*/
|
| 607 |
|
| 608 |
|
| 609 |
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|