amiro-blt / Target / Source / ARMCM4_STM32 / GCC / vectors.c @ 69661903
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| 1 | 69661903 | Thomas Schöpping | /************************************************************************************//** |
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| 2 | * \file Source\ARMCM4_STM32\GCC\vectors.c
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| 3 | * \brief Bootloader interrupt vector table source file.
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| 4 | * \ingroup Target_ARMCM4_STM32
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| 5 | * \internal
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| 6 | *----------------------------------------------------------------------------------------
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| 7 | * C O P Y R I G H T
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| 8 | *----------------------------------------------------------------------------------------
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| 9 | * Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
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| 10 | *
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| 11 | *----------------------------------------------------------------------------------------
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| 12 | * L I C E N S E
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| 13 | *----------------------------------------------------------------------------------------
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| 14 | * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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| 15 | * modify it under the terms of the GNU General Public License as published by the Free
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| 16 | * Software Foundation, either version 3 of the License, or (at your option) any later
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| 17 | * version.
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| 18 | *
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| 19 | * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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| 20 | * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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| 21 | * PURPOSE. See the GNU General Public License for more details.
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| 22 | *
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| 23 | * You should have received a copy of the GNU General Public License along with OpenBLT.
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| 24 | * If not, see <http://www.gnu.org/licenses/>.
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| 25 | *
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| 26 | * A special exception to the GPL is included to allow you to distribute a combined work
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| 27 | * that includes OpenBLT without being obliged to provide the source code for any
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| 28 | * proprietary components. The exception text is included at the bottom of the license
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| 29 | * file <license.html>.
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| 30 | *
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| 31 | * \endinternal
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| 32 | ****************************************************************************************/
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| 33 | |||
| 34 | /****************************************************************************************
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| 35 | * Include files
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| 36 | ****************************************************************************************/
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| 37 | #include "boot.h" /* bootloader generic header */ |
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| 38 | |||
| 39 | |||
| 40 | /****************************************************************************************
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| 41 | * External data declarations
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| 42 | ****************************************************************************************/
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| 43 | extern blt_int32u _estack; /* stack end address (memory.x) */ |
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| 44 | |||
| 45 | |||
| 46 | /************************************************************************************//** |
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| 47 | ** \brief Catch-all for unused interrrupt service routines.
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| 48 | ** \return none.
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| 49 | **
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| 50 | ****************************************************************************************/
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| 51 | void UnusedISR(void) |
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| 52 | {
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| 53 | /* unexpected interrupt occured, so trigger an assertion to halt the system */
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| 54 | ASSERT_RT(BLT_FALSE); |
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| 55 | } /*** end of UnusedISR ***/
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| 56 | |||
| 57 | |||
| 58 | /****************************************************************************************
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| 59 | * I N T E R R U P T V E C T O R T A B L E
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| 60 | ****************************************************************************************/
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| 61 | extern void reset_handler(void); /* implemented in cstart.c */ |
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| 62 | /** \brief Structure type for vector table entries. */
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| 63 | typedef union |
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| 64 | {
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| 65 | void (*func)(void); /**< for ISR function pointers */ |
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| 66 | blt_int32u ptr; /**< for stack pointer entry */
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| 67 | }tIsrFunc; |
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| 68 | |||
| 69 | /** \brief Interrupt vector table. */
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| 70 | __attribute__ ((section(".isr_vector")))
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| 71 | const tIsrFunc _vectab[] =
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| 72 | {
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| 73 | { .ptr = (blt_int32u)&_estack }, /* the initial stack pointer */
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| 74 | { reset_handler }, /* the reset handler */
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| 75 | { UnusedISR }, /* NMI Handler */
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| 76 | { UnusedISR }, /* Hard Fault Handler */
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| 77 | { UnusedISR }, /* MPU Fault Handler */
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| 78 | { UnusedISR }, /* Bus Fault Handler */
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| 79 | { UnusedISR }, /* Usage Fault Handler */
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| 80 | { UnusedISR }, /* Reserved */
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| 81 | { UnusedISR }, /* Reserved */
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| 82 | { UnusedISR }, /* Reserved */
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| 83 | { UnusedISR }, /* Reserved */
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| 84 | { UnusedISR }, /* SVCall Handler */
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| 85 | { UnusedISR }, /* Debug Monitor Handler */
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| 86 | { UnusedISR }, /* Reserved */
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| 87 | { UnusedISR }, /* PendSV Handler */
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| 88 | { UnusedISR }, /* SysTick Handler */
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| 89 | { UnusedISR }, /* Window Watchdog */
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| 90 | { UnusedISR }, /* PVD through EXTI Line detect */
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| 91 | { UnusedISR }, /* Tamper */
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| 92 | { UnusedISR }, /* RTC */
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| 93 | { UnusedISR }, /* Flash */
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| 94 | { UnusedISR }, /* RCC */
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| 95 | { UnusedISR }, /* EXTI Line 0 */
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| 96 | { UnusedISR }, /* EXTI Line 1 */
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| 97 | { UnusedISR }, /* EXTI Line 2 */
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| 98 | { UnusedISR }, /* EXTI Line 3 */
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| 99 | { UnusedISR }, /* EXTI Line 4 */
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| 100 | { UnusedISR }, /* DMA1 Channel 0 */
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| 101 | { UnusedISR }, /* DMA1 Channel 1 */
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| 102 | { UnusedISR }, /* DMA1 Channel 2 */
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| 103 | { UnusedISR }, /* DMA1 Channel 3 */
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| 104 | { UnusedISR }, /* DMA1 Channel 4 */
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| 105 | { UnusedISR }, /* DMA1 Channel 5 */
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| 106 | { UnusedISR }, /* DMA1 Channel 6 */
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| 107 | { UnusedISR }, /* ADC1 and ADC2, ADC3s */
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| 108 | { UnusedISR }, /* CAN1 TX */
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| 109 | { UnusedISR }, /* CAN1 RX0 */
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| 110 | { UnusedISR }, /* CAN1 RX1 */
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| 111 | { UnusedISR }, /* CAN1 SCE */
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| 112 | { UnusedISR }, /* EXTI Line 9..5 */
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| 113 | { UnusedISR }, /* TIM1 Break and TIM9 */
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| 114 | { UnusedISR }, /* TIM1 Update and TIM10 */
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| 115 | { UnusedISR }, /* TIM1 Trigger/Comm. and TIM11 */
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| 116 | { UnusedISR }, /* TIM1 Capture Compare */
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| 117 | { UnusedISR }, /* TIM2 */
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| 118 | { UnusedISR }, /* TIM3 */
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| 119 | { UnusedISR }, /* TIM4 */
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| 120 | { UnusedISR }, /* I2C1 Event */
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| 121 | { UnusedISR }, /* I2C1 Error */
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| 122 | { UnusedISR }, /* I2C2 Event */
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| 123 | { UnusedISR }, /* I2C1 Error */
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| 124 | { UnusedISR }, /* SPI1 */
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| 125 | { UnusedISR }, /* SPI2 */
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| 126 | { UnusedISR }, /* USART1 */
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| 127 | { UnusedISR }, /* USART2 */
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| 128 | { UnusedISR }, /* USART3 */
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| 129 | { UnusedISR }, /* EXTI Line 15..10 */
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| 130 | { UnusedISR }, /* RTC alarm through EXTI line */
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| 131 | { UnusedISR }, /* USB OTG FS Wakeup */
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| 132 | { UnusedISR }, /* TIM8 Break and TIM12 */
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| 133 | { UnusedISR }, /* TIM8 Update and TIM13 */
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| 134 | { UnusedISR }, /* TIM8 Trigger/Comm. and TIM14 */
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| 135 | { UnusedISR }, /* TIM8 Capture Compare */
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| 136 | { UnusedISR }, /* DMA1 Stream7 */
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| 137 | { UnusedISR }, /* FSMC */
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| 138 | { UnusedISR }, /* SDIO */
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| 139 | { UnusedISR }, /* TIM5 */
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| 140 | { UnusedISR }, /* SPI3 */
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| 141 | { UnusedISR }, /* UART4 */
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| 142 | { UnusedISR }, /* UART5 */
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| 143 | { UnusedISR }, /* TIM6 and DAC1&2 underrun err. */
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| 144 | { UnusedISR }, /* TIM7 */
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| 145 | { UnusedISR }, /* DMA2 Stream 0 */
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| 146 | { UnusedISR }, /* DMA2 Stream 1 */
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| 147 | { UnusedISR }, /* DMA2 Stream 2 */
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| 148 | { UnusedISR }, /* DMA2 Stream 3 */
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| 149 | { UnusedISR }, /* DMA2 Stream 4 */
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| 150 | { UnusedISR }, /* Ethernet */
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| 151 | { UnusedISR }, /* Ethernet Wakeup */
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| 152 | { UnusedISR }, /* CAN2 TX */
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| 153 | { UnusedISR }, /* CAN2 RX0 */
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| 154 | { UnusedISR }, /* CAN2 RX1 */
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| 155 | { UnusedISR }, /* CAN2 SCE */
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| 156 | { UnusedISR }, /* USB OTG FS */
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| 157 | { UnusedISR }, /* DMA2 Stream 5 */
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| 158 | { UnusedISR }, /* DMA2 Stream 6 */
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| 159 | { UnusedISR }, /* DMA2 Stream 7 */
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| 160 | { UnusedISR }, /* USART6 */
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| 161 | { UnusedISR }, /* I2C3 event */
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| 162 | { UnusedISR }, /* I2C3 error */
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| 163 | { UnusedISR }, /* USB OTG HS End Point 1 Out */
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| 164 | { UnusedISR }, /* USB OTG HS End Point 1 In */
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| 165 | { UnusedISR }, /* USB OTG HS Wakeup through EXTI*/
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| 166 | { UnusedISR }, /* USB OTG HS */
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| 167 | { UnusedISR }, /* DCMI */
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| 168 | { UnusedISR }, /* CRYP crypto */
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| 169 | { UnusedISR }, /* Hash and Rng */
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| 170 | { UnusedISR } /* FPU */
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| 171 | }; |
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| 172 | |||
| 173 | |||
| 174 | /************************************ end of vectors.c *********************************/
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| 175 | |||
| 176 |