amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / CMSIS / Include / core_cmFunc.h @ 69661903
History | View | Annotate | Download (15.5 KB)
1 |
/**************************************************************************//** |
---|---|
2 |
* @file core_cmFunc.h
|
3 |
* @brief CMSIS Cortex-M Core Function Access Header File
|
4 |
* @version V3.01
|
5 |
* @date 06. March 2012
|
6 |
*
|
7 |
* @note
|
8 |
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
9 |
*
|
10 |
* @par
|
11 |
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
12 |
* processor based microcontrollers. This file can be freely distributed
|
13 |
* within development tools that are supporting such ARM based processors.
|
14 |
*
|
15 |
* @par
|
16 |
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
17 |
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
18 |
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
19 |
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
20 |
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
21 |
*
|
22 |
******************************************************************************/
|
23 |
|
24 |
#ifndef __CORE_CMFUNC_H
|
25 |
#define __CORE_CMFUNC_H
|
26 |
|
27 |
|
28 |
/* ########################### Core Function Access ########################### */
|
29 |
/** \ingroup CMSIS_Core_FunctionInterface
|
30 |
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
31 |
@{
|
32 |
*/
|
33 |
|
34 |
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
35 |
/* ARM armcc specific functions */
|
36 |
|
37 |
#if (__ARMCC_VERSION < 400677) |
38 |
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
39 |
#endif
|
40 |
|
41 |
/* intrinsic void __enable_irq(); */
|
42 |
/* intrinsic void __disable_irq(); */
|
43 |
|
44 |
/** \brief Get Control Register
|
45 |
|
46 |
This function returns the content of the Control Register.
|
47 |
|
48 |
\return Control Register value
|
49 |
*/
|
50 |
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
51 |
{ |
52 |
register uint32_t __regControl __ASM("control"); |
53 |
return(__regControl);
|
54 |
} |
55 |
|
56 |
|
57 |
/** \brief Set Control Register
|
58 |
|
59 |
This function writes the given value to the Control Register.
|
60 |
|
61 |
\param [in] control Control Register value to set
|
62 |
*/
|
63 |
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
64 |
{ |
65 |
register uint32_t __regControl __ASM("control"); |
66 |
__regControl = control; |
67 |
} |
68 |
|
69 |
|
70 |
/** \brief Get IPSR Register
|
71 |
|
72 |
This function returns the content of the IPSR Register.
|
73 |
|
74 |
\return IPSR Register value
|
75 |
*/
|
76 |
__STATIC_INLINE uint32_t __get_IPSR(void)
|
77 |
{ |
78 |
register uint32_t __regIPSR __ASM("ipsr"); |
79 |
return(__regIPSR);
|
80 |
} |
81 |
|
82 |
|
83 |
/** \brief Get APSR Register
|
84 |
|
85 |
This function returns the content of the APSR Register.
|
86 |
|
87 |
\return APSR Register value
|
88 |
*/
|
89 |
__STATIC_INLINE uint32_t __get_APSR(void)
|
90 |
{ |
91 |
register uint32_t __regAPSR __ASM("apsr"); |
92 |
return(__regAPSR);
|
93 |
} |
94 |
|
95 |
|
96 |
/** \brief Get xPSR Register
|
97 |
|
98 |
This function returns the content of the xPSR Register.
|
99 |
|
100 |
\return xPSR Register value
|
101 |
*/
|
102 |
__STATIC_INLINE uint32_t __get_xPSR(void)
|
103 |
{ |
104 |
register uint32_t __regXPSR __ASM("xpsr"); |
105 |
return(__regXPSR);
|
106 |
} |
107 |
|
108 |
|
109 |
/** \brief Get Process Stack Pointer
|
110 |
|
111 |
This function returns the current value of the Process Stack Pointer (PSP).
|
112 |
|
113 |
\return PSP Register value
|
114 |
*/
|
115 |
__STATIC_INLINE uint32_t __get_PSP(void)
|
116 |
{ |
117 |
register uint32_t __regProcessStackPointer __ASM("psp"); |
118 |
return(__regProcessStackPointer);
|
119 |
} |
120 |
|
121 |
|
122 |
/** \brief Set Process Stack Pointer
|
123 |
|
124 |
This function assigns the given value to the Process Stack Pointer (PSP).
|
125 |
|
126 |
\param [in] topOfProcStack Process Stack Pointer value to set
|
127 |
*/
|
128 |
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
129 |
{ |
130 |
register uint32_t __regProcessStackPointer __ASM("psp"); |
131 |
__regProcessStackPointer = topOfProcStack; |
132 |
} |
133 |
|
134 |
|
135 |
/** \brief Get Main Stack Pointer
|
136 |
|
137 |
This function returns the current value of the Main Stack Pointer (MSP).
|
138 |
|
139 |
\return MSP Register value
|
140 |
*/
|
141 |
__STATIC_INLINE uint32_t __get_MSP(void)
|
142 |
{ |
143 |
register uint32_t __regMainStackPointer __ASM("msp"); |
144 |
return(__regMainStackPointer);
|
145 |
} |
146 |
|
147 |
|
148 |
/** \brief Set Main Stack Pointer
|
149 |
|
150 |
This function assigns the given value to the Main Stack Pointer (MSP).
|
151 |
|
152 |
\param [in] topOfMainStack Main Stack Pointer value to set
|
153 |
*/
|
154 |
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
155 |
{ |
156 |
register uint32_t __regMainStackPointer __ASM("msp"); |
157 |
__regMainStackPointer = topOfMainStack; |
158 |
} |
159 |
|
160 |
|
161 |
/** \brief Get Priority Mask
|
162 |
|
163 |
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
164 |
|
165 |
\return Priority Mask value
|
166 |
*/
|
167 |
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
168 |
{ |
169 |
register uint32_t __regPriMask __ASM("primask"); |
170 |
return(__regPriMask);
|
171 |
} |
172 |
|
173 |
|
174 |
/** \brief Set Priority Mask
|
175 |
|
176 |
This function assigns the given value to the Priority Mask Register.
|
177 |
|
178 |
\param [in] priMask Priority Mask
|
179 |
*/
|
180 |
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
181 |
{ |
182 |
register uint32_t __regPriMask __ASM("primask"); |
183 |
__regPriMask = (priMask); |
184 |
} |
185 |
|
186 |
|
187 |
#if (__CORTEX_M >= 0x03) |
188 |
|
189 |
/** \brief Enable FIQ
|
190 |
|
191 |
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
192 |
Can only be executed in Privileged modes.
|
193 |
*/
|
194 |
#define __enable_fault_irq __enable_fiq
|
195 |
|
196 |
|
197 |
/** \brief Disable FIQ
|
198 |
|
199 |
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
200 |
Can only be executed in Privileged modes.
|
201 |
*/
|
202 |
#define __disable_fault_irq __disable_fiq
|
203 |
|
204 |
|
205 |
/** \brief Get Base Priority
|
206 |
|
207 |
This function returns the current value of the Base Priority register.
|
208 |
|
209 |
\return Base Priority register value
|
210 |
*/
|
211 |
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
212 |
{ |
213 |
register uint32_t __regBasePri __ASM("basepri"); |
214 |
return(__regBasePri);
|
215 |
} |
216 |
|
217 |
|
218 |
/** \brief Set Base Priority
|
219 |
|
220 |
This function assigns the given value to the Base Priority register.
|
221 |
|
222 |
\param [in] basePri Base Priority value to set
|
223 |
*/
|
224 |
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
225 |
{ |
226 |
register uint32_t __regBasePri __ASM("basepri"); |
227 |
__regBasePri = (basePri & 0xff);
|
228 |
} |
229 |
|
230 |
|
231 |
/** \brief Get Fault Mask
|
232 |
|
233 |
This function returns the current value of the Fault Mask register.
|
234 |
|
235 |
\return Fault Mask register value
|
236 |
*/
|
237 |
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
238 |
{ |
239 |
register uint32_t __regFaultMask __ASM("faultmask"); |
240 |
return(__regFaultMask);
|
241 |
} |
242 |
|
243 |
|
244 |
/** \brief Set Fault Mask
|
245 |
|
246 |
This function assigns the given value to the Fault Mask register.
|
247 |
|
248 |
\param [in] faultMask Fault Mask value to set
|
249 |
*/
|
250 |
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
251 |
{ |
252 |
register uint32_t __regFaultMask __ASM("faultmask"); |
253 |
__regFaultMask = (faultMask & (uint32_t)1);
|
254 |
} |
255 |
|
256 |
#endif /* (__CORTEX_M >= 0x03) */ |
257 |
|
258 |
|
259 |
#if (__CORTEX_M == 0x04) |
260 |
|
261 |
/** \brief Get FPSCR
|
262 |
|
263 |
This function returns the current value of the Floating Point Status/Control register.
|
264 |
|
265 |
\return Floating Point Status/Control register value
|
266 |
*/
|
267 |
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
268 |
{ |
269 |
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
270 |
register uint32_t __regfpscr __ASM("fpscr"); |
271 |
return(__regfpscr);
|
272 |
#else
|
273 |
return(0); |
274 |
#endif
|
275 |
} |
276 |
|
277 |
|
278 |
/** \brief Set FPSCR
|
279 |
|
280 |
This function assigns the given value to the Floating Point Status/Control register.
|
281 |
|
282 |
\param [in] fpscr Floating Point Status/Control value to set
|
283 |
*/
|
284 |
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
285 |
{ |
286 |
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
287 |
register uint32_t __regfpscr __ASM("fpscr"); |
288 |
__regfpscr = (fpscr); |
289 |
#endif
|
290 |
} |
291 |
|
292 |
#endif /* (__CORTEX_M == 0x04) */ |
293 |
|
294 |
|
295 |
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
296 |
/* IAR iccarm specific functions */
|
297 |
|
298 |
#include <cmsis_iar.h> |
299 |
|
300 |
|
301 |
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ |
302 |
/* TI CCS specific functions */
|
303 |
|
304 |
#include <cmsis_ccs.h> |
305 |
|
306 |
|
307 |
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
308 |
/* GNU gcc specific functions */
|
309 |
|
310 |
/** \brief Enable IRQ Interrupts
|
311 |
|
312 |
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
313 |
Can only be executed in Privileged modes.
|
314 |
*/
|
315 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
316 |
{ |
317 |
__ASM volatile ("cpsie i"); |
318 |
} |
319 |
|
320 |
|
321 |
/** \brief Disable IRQ Interrupts
|
322 |
|
323 |
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
324 |
Can only be executed in Privileged modes.
|
325 |
*/
|
326 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) |
327 |
{ |
328 |
__ASM volatile ("cpsid i"); |
329 |
} |
330 |
|
331 |
|
332 |
/** \brief Get Control Register
|
333 |
|
334 |
This function returns the content of the Control Register.
|
335 |
|
336 |
\return Control Register value
|
337 |
*/
|
338 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
339 |
{ |
340 |
uint32_t result; |
341 |
|
342 |
__ASM volatile ("MRS %0, control" : "=r" (result) ); |
343 |
return(result);
|
344 |
} |
345 |
|
346 |
|
347 |
/** \brief Set Control Register
|
348 |
|
349 |
This function writes the given value to the Control Register.
|
350 |
|
351 |
\param [in] control Control Register value to set
|
352 |
*/
|
353 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
354 |
{ |
355 |
__ASM volatile ("MSR control, %0" : : "r" (control) ); |
356 |
} |
357 |
|
358 |
|
359 |
/** \brief Get IPSR Register
|
360 |
|
361 |
This function returns the content of the IPSR Register.
|
362 |
|
363 |
\return IPSR Register value
|
364 |
*/
|
365 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
366 |
{ |
367 |
uint32_t result; |
368 |
|
369 |
__ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
370 |
return(result);
|
371 |
} |
372 |
|
373 |
|
374 |
/** \brief Get APSR Register
|
375 |
|
376 |
This function returns the content of the APSR Register.
|
377 |
|
378 |
\return APSR Register value
|
379 |
*/
|
380 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
381 |
{ |
382 |
uint32_t result; |
383 |
|
384 |
__ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
385 |
return(result);
|
386 |
} |
387 |
|
388 |
|
389 |
/** \brief Get xPSR Register
|
390 |
|
391 |
This function returns the content of the xPSR Register.
|
392 |
|
393 |
\return xPSR Register value
|
394 |
*/
|
395 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
396 |
{ |
397 |
uint32_t result; |
398 |
|
399 |
__ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
400 |
return(result);
|
401 |
} |
402 |
|
403 |
|
404 |
/** \brief Get Process Stack Pointer
|
405 |
|
406 |
This function returns the current value of the Process Stack Pointer (PSP).
|
407 |
|
408 |
\return PSP Register value
|
409 |
*/
|
410 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
411 |
{ |
412 |
register uint32_t result;
|
413 |
|
414 |
__ASM volatile ("MRS %0, psp\n" : "=r" (result) ); |
415 |
return(result);
|
416 |
} |
417 |
|
418 |
|
419 |
/** \brief Set Process Stack Pointer
|
420 |
|
421 |
This function assigns the given value to the Process Stack Pointer (PSP).
|
422 |
|
423 |
\param [in] topOfProcStack Process Stack Pointer value to set
|
424 |
*/
|
425 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
426 |
{ |
427 |
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); |
428 |
} |
429 |
|
430 |
|
431 |
/** \brief Get Main Stack Pointer
|
432 |
|
433 |
This function returns the current value of the Main Stack Pointer (MSP).
|
434 |
|
435 |
\return MSP Register value
|
436 |
*/
|
437 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
438 |
{ |
439 |
register uint32_t result;
|
440 |
|
441 |
__ASM volatile ("MRS %0, msp\n" : "=r" (result) ); |
442 |
return(result);
|
443 |
} |
444 |
|
445 |
|
446 |
/** \brief Set Main Stack Pointer
|
447 |
|
448 |
This function assigns the given value to the Main Stack Pointer (MSP).
|
449 |
|
450 |
\param [in] topOfMainStack Main Stack Pointer value to set
|
451 |
*/
|
452 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
453 |
{ |
454 |
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); |
455 |
} |
456 |
|
457 |
|
458 |
/** \brief Get Priority Mask
|
459 |
|
460 |
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
461 |
|
462 |
\return Priority Mask value
|
463 |
*/
|
464 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
465 |
{ |
466 |
uint32_t result; |
467 |
|
468 |
__ASM volatile ("MRS %0, primask" : "=r" (result) ); |
469 |
return(result);
|
470 |
} |
471 |
|
472 |
|
473 |
/** \brief Set Priority Mask
|
474 |
|
475 |
This function assigns the given value to the Priority Mask Register.
|
476 |
|
477 |
\param [in] priMask Priority Mask
|
478 |
*/
|
479 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
480 |
{ |
481 |
__ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
482 |
} |
483 |
|
484 |
|
485 |
#if (__CORTEX_M >= 0x03) |
486 |
|
487 |
/** \brief Enable FIQ
|
488 |
|
489 |
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
490 |
Can only be executed in Privileged modes.
|
491 |
*/
|
492 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) |
493 |
{ |
494 |
__ASM volatile ("cpsie f"); |
495 |
} |
496 |
|
497 |
|
498 |
/** \brief Disable FIQ
|
499 |
|
500 |
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
501 |
Can only be executed in Privileged modes.
|
502 |
*/
|
503 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) |
504 |
{ |
505 |
__ASM volatile ("cpsid f"); |
506 |
} |
507 |
|
508 |
|
509 |
/** \brief Get Base Priority
|
510 |
|
511 |
This function returns the current value of the Base Priority register.
|
512 |
|
513 |
\return Base Priority register value
|
514 |
*/
|
515 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
516 |
{ |
517 |
uint32_t result; |
518 |
|
519 |
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
520 |
return(result);
|
521 |
} |
522 |
|
523 |
|
524 |
/** \brief Set Base Priority
|
525 |
|
526 |
This function assigns the given value to the Base Priority register.
|
527 |
|
528 |
\param [in] basePri Base Priority value to set
|
529 |
*/
|
530 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
531 |
{ |
532 |
__ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
533 |
} |
534 |
|
535 |
|
536 |
/** \brief Get Fault Mask
|
537 |
|
538 |
This function returns the current value of the Fault Mask register.
|
539 |
|
540 |
\return Fault Mask register value
|
541 |
*/
|
542 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
543 |
{ |
544 |
uint32_t result; |
545 |
|
546 |
__ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
547 |
return(result);
|
548 |
} |
549 |
|
550 |
|
551 |
/** \brief Set Fault Mask
|
552 |
|
553 |
This function assigns the given value to the Fault Mask register.
|
554 |
|
555 |
\param [in] faultMask Fault Mask value to set
|
556 |
*/
|
557 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
558 |
{ |
559 |
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
560 |
} |
561 |
|
562 |
#endif /* (__CORTEX_M >= 0x03) */ |
563 |
|
564 |
|
565 |
#if (__CORTEX_M == 0x04) |
566 |
|
567 |
/** \brief Get FPSCR
|
568 |
|
569 |
This function returns the current value of the Floating Point Status/Control register.
|
570 |
|
571 |
\return Floating Point Status/Control register value
|
572 |
*/
|
573 |
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
574 |
{ |
575 |
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
576 |
uint32_t result; |
577 |
|
578 |
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
579 |
return(result);
|
580 |
#else
|
581 |
return(0); |
582 |
#endif
|
583 |
} |
584 |
|
585 |
|
586 |
/** \brief Set FPSCR
|
587 |
|
588 |
This function assigns the given value to the Floating Point Status/Control register.
|
589 |
|
590 |
\param [in] fpscr Floating Point Status/Control value to set
|
591 |
*/
|
592 |
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
593 |
{ |
594 |
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
595 |
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); |
596 |
#endif
|
597 |
} |
598 |
|
599 |
#endif /* (__CORTEX_M == 0x04) */ |
600 |
|
601 |
|
602 |
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
603 |
/* TASKING carm specific functions */
|
604 |
|
605 |
/*
|
606 |
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
607 |
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
608 |
* Including the CMSIS ones.
|
609 |
*/
|
610 |
|
611 |
#endif
|
612 |
|
613 |
/*@} end of CMSIS_Core_RegAccFunctions */
|
614 |
|
615 |
|
616 |
#endif /* __CORE_CMFUNC_H */ |