AMiRo-OS

/************************************************************************************//**

* \file         Source\ARMCM4_STM32\can.c

* \brief        Bootloader CAN communication interface source file.

* \ingroup      Target_ARMCM4_STM32

* \internal

*----------------------------------------------------------------------------------------

*                          C O P Y R I G H T

*----------------------------------------------------------------------------------------

*   Copyright (c) 2013  by Feaser    http://www.feaser.com    All rights reserved

*

*----------------------------------------------------------------------------------------

*                            L I C E N S E

*----------------------------------------------------------------------------------------

* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or

* modify it under the terms of the GNU General Public License as published by the Free

* Software Foundation, either version 3 of the License, or (at your option) any later

* version.

*

* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;

* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

* PURPOSE. See the GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License along with OpenBLT.

* If not, see <http://www.gnu.org/licenses/>.

*

* A special exception to the GPL is included to allow you to distribute a combined work

* that includes OpenBLT without being obliged to provide the source code for any

* proprietary components. The exception text is included at the bottom of the license

* file <license.html>.

*

* \endinternal

****************************************************************************************/

#define CAN_DEBUG       (0)

/****************************************************************************************

* Include files

****************************************************************************************/

#include "boot.h"                                /* bootloader generic header          */

#if (CAN_DEBUG > 0)

#include <helper.h>

#endif

#if (BOOT_COM_CAN_ENABLE > 0 || BOOT_GATE_CAN_ENABLE > 0)

/****************************************************************************************

* Type definitions

****************************************************************************************/

/** \brief CAN transmission mailbox layout. */

typedef struct

{

  volatile blt_int32u TIR;

  volatile blt_int32u TDTR;

  volatile blt_int32u TDLR;

  volatile blt_int32u TDHR;

} tCanTxMailBox;

/** \brief CAN reception FIFO mailbox layout. */

typedef struct

{

  volatile blt_int32u RIR;

  volatile blt_int32u RDTR;

  volatile blt_int32u RDLR;

  volatile blt_int32u RDHR;

} tCanRxFIFOMailBox;

/** \brief CAN filter register layout. */

typedef struct

{

  volatile blt_int32u FR1;

  volatile blt_int32u FR2;

} tCanFilter;

/** \brief CAN controller register layout. */

typedef struct

{

  volatile blt_int32u MCR;

  volatile blt_int32u MSR;

  volatile blt_int32u TSR;

  volatile blt_int32u RF0R;

  volatile blt_int32u RF1R;

  volatile blt_int32u IER;

  volatile blt_int32u ESR;

  volatile blt_int32u BTR;

  blt_int32u          RESERVED0[88];

  tCanTxMailBox       sTxMailBox[3];

  tCanRxFIFOMailBox   sFIFOMailBox[2];

  blt_int32u          RESERVED1[12];

  volatile blt_int32u FMR;

  volatile blt_int32u FM1R;

  blt_int32u          RESERVED2;

  volatile blt_int32u FS1R;

  blt_int32u          RESERVED3;

  volatile blt_int32u FFA1R;

  blt_int32u          RESERVED4;

  volatile blt_int32u FA1R;

  blt_int32u          RESERVED5[8];

  tCanFilter          sFilterRegister[28];

} tCanRegs;

/****************************************************************************************

* Macro definitions

****************************************************************************************/

/** \brief Reset request bit. */

#define CAN_BIT_RESET    ((blt_int32u)0x00008000)

/** \brief Initialization request bit. */

#define CAN_BIT_INRQ     ((blt_int32u)0x00000001)

/** \brief Initialization acknowledge bit. */

#define CAN_BIT_INAK     ((blt_int32u)0x00000001)

/** \brief Sleep mode request bit. */

#define CAN_BIT_SLEEP    ((blt_int32u)0x00000002)

/** \brief Filter 0 selection bit. */

#define CAN_BIT_FILTER0  ((blt_int32u)0x00000001)

/** \brief Filter 14 selection bit. */

#define CAN_BIT_FILTER14 ((blt_int32u)0x00004000)

/** \brief Filter init mode bit. */

#define CAN_BIT_FINIT    ((blt_int32u)0x00000001)

/** \brief Transmit mailbox 0 empty bit. */

#define CAN_BIT_TME0     ((blt_int32u)0x04000000)

/** \brief Transmit mailbox request bit. */

#define CAN_BIT_TXRQ     ((blt_int32u)0x00000001)

/** \brief Release FIFO 0 mailbox bit. */

#define CAN_BIT_RFOM0    ((blt_int32u)0x00000020)

#if (BOOT_GATE_CAN_ENABLE > 0)

blt_bool commandSend;

#endif /* BOOT_GATE_CAN_ENABLE > 0 */

/****************************************************************************************

* Register definitions

****************************************************************************************/

#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)

/** \brief Macro for accessing CAN1 controller registers. */

#define CANx             ((tCanRegs *) (blt_int32u)0x40006400)

#else

/** \brief Macro for accessing CAN2 controller registers. */

#define CANx             ((tCanRegs *) (blt_int32u)0x40006800)

#endif

/** \brief Macro for accessing CAN1 controller registers. */

#define CAN1             ((tCanRegs *) (blt_int32u)0x40006400)

/****************************************************************************************

* Type definitions

****************************************************************************************/

/** \brief Structure type for grouping CAN bus timing related information. */

typedef struct t_can_bus_timing

{

  blt_int8u tseg1;                                    /**< CAN time segment 1          */

  blt_int8u tseg2;                                    /**< CAN time segment 2          */

} tCanBusTiming;

/****************************************************************************************

* Local constant declarations

****************************************************************************************/

/** \brief CAN bittiming table for dynamically calculating the bittiming settings.

 *  \details According to the CAN protocol 1 bit-time can be made up of between 8..25

 *           time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC

 *           always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *

 *           100%. This array contains possible and valid time quanta configurations with

 *           a sample point between 68..78%.

 */

static const tCanBusTiming canTiming[] =

{                       /*  TQ | TSEG1 | TSEG2 | SP  */

                        /* ------------------------- */

    {  5, 2 },          /*   8 |   5   |   2   | 75% */

    {  6, 2 },          /*   9 |   6   |   2   | 78% */

    {  6, 3 },          /*  10 |   6   |   3   | 70% */

    {  7, 3 },          /*  11 |   7   |   3   | 73% */

    {  8, 3 },          /*  12 |   8   |   3   | 75% */

    {  9, 3 },          /*  13 |   9   |   3   | 77% */

    {  9, 4 },          /*  14 |   9   |   4   | 71% */

    { 10, 4 },          /*  15 |  10   |   4   | 73% */

    { 11, 4 },          /*  16 |  11   |   4   | 75% */

    { 12, 4 },          /*  17 |  12   |   4   | 76% */

    { 12, 5 },          /*  18 |  12   |   5   | 72% */

    { 13, 5 },          /*  19 |  13   |   5   | 74% */

    { 14, 5 },          /*  20 |  14   |   5   | 75% */

    { 15, 5 },          /*  21 |  15   |   5   | 76% */

    { 15, 6 },          /*  22 |  15   |   6   | 73% */

    { 16, 6 },          /*  23 |  16   |   6   | 74% */

    { 16, 7 },          /*  24 |  16   |   7   | 71% */

    { 16, 8 }           /*  25 |  16   |   8   | 68% */

};

int counter = 0;

/************************************************************************************//**

** \brief     Search algorithm to match the desired baudrate to a possible bus

**            timing configuration.

** \param     baud The desired baudrate in kbps. Valid values are 10..1000.

** \param     prescaler Pointer to where the value for the prescaler will be stored.

** \param     tseg1 Pointer to where the value for TSEG2 will be stored.

** \param     tseg2 Pointer to where the value for TSEG2 will be stored.

** \return    BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE

**            otherwise.

**

****************************************************************************************/

static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u *prescaler,

                                  blt_int8u *tseg1, blt_int8u *tseg2)

{

  blt_int8u  cnt;

  /* loop through all possible time quanta configurations to find a match */

  for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)

  {

    if (((BOOT_CPU_SYSTEM_SPEED_KHZ/4) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)

    {

      /* compute the prescaler that goes with this TQ configuration */

      *prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/4)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));

      /* make sure the prescaler is valid */

      if ( (*prescaler > 0) && (*prescaler <= 1024) )

      {

        /* store the bustiming configuration */

        *tseg1 = canTiming[cnt].tseg1;

        *tseg2 = canTiming[cnt].tseg2;

        /* found a good bus timing configuration */

        return BLT_TRUE;

      }

    }

  }

  /* could not find a good bus timing configuration */