amiro-lld / drivers / PCAL6524 / v1 / alld_PCAL6524.h @ 9466e34d
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1 | e3287406 | Thomas Schöpping | /*
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2 | AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
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3 | Copyright (C) 2016..2019 Thomas Schöpping et al.
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4 | |||
5 | This program is free software: you can redistribute it and/or modify
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6 | it under the terms of the GNU Lesser General Public License as published by
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7 | the Free Software Foundation, either version 3 of the License, or
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8 | (at your option) any later version.
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9 | |||
10 | This program is distributed in the hope that it will be useful,
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11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 | GNU Lesser General Public License for more details.
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14 | |||
15 | You should have received a copy of the GNU Lesser General Public License
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16 | along with this program. If not, see <http://www.gnu.org/licenses/>.
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17 | */
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18 | |||
19 | /**
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20 | 9466e34d | Thomas Schöpping | * @file alld_PCAL6524.h
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21 | e3287406 | Thomas Schöpping | * @brief GPIO extender macros and structures.
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22 | *
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23 | * @addtogroup lld_gpioext
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24 | * @{
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25 | */
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26 | |||
27 | 9466e34d | Thomas Schöpping | #ifndef AMIROLLD_PCAL6524_H
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28 | #define AMIROLLD_PCAL6524_H
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29 | e3287406 | Thomas Schöpping | |
30 | #include <amiro-lld.h> |
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31 | |||
32 | ef078306 | Thomas Schöpping | /******************************************************************************/
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33 | /* CONSTANTS */
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34 | /******************************************************************************/
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35 | |||
36 | e3287406 | Thomas Schöpping | /**
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37 | * @brief Maximum I2C frequency.
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38 | */
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39 | #define PCAL6524_LLD_I2C_MAXFREQUENCY 1000000 |
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40 | |||
41 | /**
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42 | * @brief A falling edge indicats an interrupt.
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43 | */
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44 | #define PCAL6524_LLD_INT_EDGE APAL_GPIO_EDGE_FALLING
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45 | |||
46 | ef078306 | Thomas Schöpping | /******************************************************************************/
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47 | /* SETTINGS */
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48 | /******************************************************************************/
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49 | |||
50 | /******************************************************************************/
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51 | /* CHECKS */
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52 | /******************************************************************************/
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53 | |||
54 | /******************************************************************************/
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55 | /* DATA STRUCTURES AND TYPES */
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56 | /******************************************************************************/
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57 | |||
58 | e3287406 | Thomas Schöpping | /**
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59 | * @brief The PCAL6524Driver sruct.
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60 | */
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61 | typedef struct { |
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62 | apalI2CDriver_t* i2cd; |
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63 | apalI2Caddr_t addr; |
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64 | } PCAL6524Driver; |
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65 | |||
66 | /**
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67 | * @brief Possible I2C address configurations.
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68 | */
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69 | enum {
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70 | PCAL6524_LLD_I2C_ADDR_FIXED = 0x0020u, /**< Fixed part of the I2C address. */ |
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71 | PCAL6524_LLD_I2C_ADDR_SCL = 0x0020u, /**< ADDR pin connected to SCL. */ |
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72 | PCAL6524_LLD_I2C_ADDR_SDA = 0x0021u, /**< ADDR pin connected to SDA. */ |
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73 | PCAL6524_LLD_I2C_ADDR_VSS = 0x0022u, /**< ADDR pin connected to VSS. */ |
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74 | PCAL6524_LLD_I2C_ADDR_VDD = 0x0023u, /**< ADDR pin connected to VDD. */ |
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75 | PCAL6524_LLD_I2C_ADDR_DEVICEID = 0x007Cu, /**< Special address to read device ID information. */ |
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76 | }; |
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77 | |||
78 | /**
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79 | * @brief Command bit to enable auto-incrementation of command value.
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80 | * @details Can be added (ORed) to any command value.
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81 | */
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82 | #define PCAL6524_LLD_CMD_AUTOINCREMENT 0x80u |
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83 | |||
84 | /**
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85 | * @brief The total number of registers that can be accessed.
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86 | * @note This is the maximum number of bytes that may be read or written continuously.
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87 | */
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88 | #define PCAL6524_LLD_NUM_REGISTERS 52 |
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89 | |||
90 | typedef union { |
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91 | uint8_t raw[3];
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92 | struct {
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93 | uint16_t name : 12;
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94 | uint16_t part : 9;
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95 | uint8_t revision : 3;
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96 | }; |
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97 | } pcal6524_lld_deviceid_t; |
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98 | |||
99 | /**
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100 | * @brief Control commands for the PCAL6524.
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101 | */
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102 | typedef enum { |
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103 | PCAL6524_LLD_CMD_INPUT_P0 = 0x00u, /**< read only */ |
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104 | PCAL6524_LLD_CMD_INPUT_P1 = 0x01u, /**< read only */ |
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105 | PCAL6524_LLD_CMD_INPUT_P2 = 0x02u, /**< read only */ |
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106 | PCAL6524_LLD_CMD_OUTPUT_P0 = 0x04u, /**< read/write */ |
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107 | PCAL6524_LLD_CMD_OUTPUT_P1 = 0x05u, /**< read/write */ |
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108 | PCAL6524_LLD_CMD_OUTPUT_P2 = 0x06u, /**< read/write */ |
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109 | PCAL6524_LLD_CMD_POLARITYINVERSION_P0 = 0x08u, /**< read/write */ |
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110 | PCAL6524_LLD_CMD_POLARITYINVERSION_P1 = 0x09u, /**< read/write */ |
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111 | PCAL6524_LLD_CMD_POLARITYINVERSION_P2 = 0x0Au, /**< read/write */ |
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112 | PCAL6524_LLD_CMD_CONFIGURATION_P0 = 0x0Cu, /**< read/write */ |
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113 | PCAL6524_LLD_CMD_CONFIGURATION_P1 = 0x0Du, /**< read/write */ |
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114 | PCAL6524_LLD_CMD_CONFIGURATION_P2 = 0x0Eu, /**< read/write */ |
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115 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0A = 0x40u, /**< read/write */ |
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116 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0B = 0x41u, /**< read/write */ |
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117 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1A = 0x42u, /**< read/write */ |
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118 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1B = 0x43u, /**< read/write */ |
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119 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2A = 0x44u, /**< read/write */ |
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120 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2B = 0x45u, /**< read/write */ |
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121 | PCAL6524_LLD_CMD_INPUTLATCH_P0 = 0x48u, /**< read/write */ |
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122 | PCAL6524_LLD_CMD_INPUTLATCH_P1 = 0x49u, /**< read/write */ |
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123 | PCAL6524_LLD_CMD_INPUTLATCH_P2 = 0x4Au, /**< read/write */ |
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124 | PCAL6524_LLD_CMD_PUPDENABLE_P0 = 0x4Cu, /**< read/write */ |
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125 | PCAL6524_LLD_CMD_PUPDENABLE_P1 = 0x4Du, /**< read/write */ |
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126 | PCAL6524_LLD_CMD_PUPDENABLE_P2 = 0x4Eu, /**< read/write */ |
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127 | PCAL6524_LLD_CMD_PUPDSELECTION_P0 = 0x50u, /**< read/write */ |
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128 | PCAL6524_LLD_CMD_PUPDSELECTION_P1 = 0x51u, /**< read/write */ |
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129 | PCAL6524_LLD_CMD_PUPDSELECTION_P2 = 0x52u, /**< read/write */ |
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130 | PCAL6524_LLD_CMD_INTERRUPTMASK_P0 = 0x54u, /**< read/write */ |
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131 | PCAL6524_LLD_CMD_INTERRUPTMASK_P1 = 0x55u, /**< read/write */ |
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132 | PCAL6524_LLD_CMD_INTERRUPTMASK_P2 = 0x56u, /**< read/write */ |
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133 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P0 = 0x58u, /**< read only */ |
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134 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P1 = 0x59u, /**< read only */ |
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135 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P2 = 0x5Au, /**< read only */ |
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136 | PCAL6524_LLD_CMD_OUTPUTCONFIGURATION = 0x5Cu, /**< read/write */ |
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137 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P0A = 0x60u, /**< read/write */ |
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138 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P0B = 0x61u, /**< read/write */ |
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139 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P1A = 0x62u, /**< read/write */ |
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140 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P1B = 0x63u, /**< read/write */ |
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141 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P2A = 0x64u, /**< read/write */ |
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142 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P2B = 0x65u, /**< read/write */ |
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143 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P0 = 0x68u, /**< write only */ |
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144 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P1 = 0x69u, /**< write only */ |
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145 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P2 = 0x6Au, /**< write only */ |
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146 | PCAL6524_LLD_CMD_INPUTSTATUS_P0 = 0x6Cu, /**< read only */ |
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147 | PCAL6524_LLD_CMD_INPUTSTATUS_P1 = 0x6Du, /**< read only */ |
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148 | PCAL6524_LLD_CMD_INPUTSTATUS_P2 = 0x6Eu, /**< read only */ |
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149 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P0 = 0x70u, /**< read/write */ |
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150 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P1 = 0x71u, /**< read/write */ |
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151 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P2 = 0x72u, /**< read/write */ |
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152 | PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P0 = 0x74u, /**< read/write */ |
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153 | PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P1 = 0x75u, /**< read/write */ |
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154 | PCAL6524_LLD_CMD_SWITCHDEBOUNCECOUNT = 0x76u, /**< read/write */ |
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155 | } pcal6524_lld_cmd_t; |
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156 | |||
157 | /**
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158 | * @brief Input register bit values.
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159 | * @details The bits in the input register reflect the incoming logic levels per pin.
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160 | * If a pin is configured as ouput, the bit reflects th set value or is forced to 0 in case the outpus is configured as open-drain.
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161 | * If a pin is configured as input with latched interrupts, reading the according port will reset the input value and clear the interrupt.
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162 | */
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163 | typedef enum { |
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164 | PCAL6524_LLD_INPUT_LOW = 0b0,
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165 | PCAL6524_LLD_INPUT_HIGH = 0b1,
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166 | } pcal6524_lld_input_t; |
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167 | |||
168 | /**
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169 | * @brief Output register bit values.
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170 | * @details Defines the logic level to be driven by output pins.
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171 | * The default value (after reset) is 0b1 (high),
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172 | */
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173 | typedef enum { |
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174 | PCAL6524_LLD_OUTPUT_LOW = 0b0,
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175 | PCAL6524_LLD_OUTPUT_HIGH = 0b1,
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176 | } pcal6524_lld_output_t; |
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177 | |||
178 | /**
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179 | * @brief Polarity inversion register values.
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180 | * @details Allows to inverse the logic values written to the input register.
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181 | * The default value (after reset) is 0b0 (disabled).
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182 | */
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183 | typedef enum { |
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184 | PCAL6524_LLD_POLARITYINVERSION_DISABLED = 0b0,
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185 | PCAL6524_LLD_POLARITYINVERSION_ENABLED = 0b1,
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186 | } pcal6524_lld_polarityinversion_t; |
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187 | |||
188 | /**
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189 | * @brief Configuration regsiter bit values.
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190 | * @details Configures the direction of the I/O pins to either high-impedance input or output.
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191 | * The default value (after reset) is 0b1 (input).
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192 | */
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193 | typedef enum { |
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194 | PCAL6524_LLD_CONFIGURATION_INPUT = 0b1,
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195 | PCAL6524_LLD_CONFIGURATION_OUTPUT = 0b0,
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196 | } pcal6524_lld_configuration_t; |
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197 | |||
198 | /**
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199 | * @brief Output drive strength register mask values.
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200 | * @details Configures maximum current of output pins can be defined via a 2 bit mask per pin.
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201 | * Toggling multiple output pins simultaneously a peak current may induce noise to supply voltage and ground.
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202 | * By lowering the maximum current per pin. this effect can be minimized.
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203 | * The default value (after reset) is 0b11 (factor 1x)
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204 | */
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205 | typedef enum { |
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206 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_25 = 0b00,
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207 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_5 = 0b01,
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208 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_75 = 0b10,
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209 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_1 = 0b11,
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210 | } pcal6524_lld_outputdrivestrength_t; |
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211 | |||
212 | /**
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213 | * @brief Input latch register bit values.
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214 | * @details Allows to latch interrupt and input states per pin, if an interrupt occurred.
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215 | * The default value (after reset) is 0b0 (disabled).
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216 | */
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217 | typedef enum { |
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218 | PCAL6524_LLD_INPUTLATCH_ENABLED = 0b1,
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219 | PCAL6524_LLD_INPUTLATCH_DISABLED = 0b0,
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220 | } pcal6524_lld_inputlatch_t; |
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221 | |||
222 | /**
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223 | * @brief Pull-up/Pull-down enable register bis values.
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224 | * @details Configures per pin whether the pull-up/pull-down resistors shall be enabled.
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225 | * If a pin is configured as open-drain output, the setting in this register are overridden and the resistors are disconnected.
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226 | * The default value (after reset) is 0b0 (disabled).
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227 | */
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228 | typedef enum { |
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229 | PCAL6524_LLD_PUPD_ENABLED = 0b1,
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230 | PCAL6524_LLD_PUPD_DISABLED = 0b0,
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231 | } pcal6524_lld_pupdenable_t; |
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232 | |||
233 | /**
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234 | * @brief Pull-up/Pull-dpwn selection register bit values.
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235 | * @details Selects between pull-up and pull-down resistor (100 kΩ) per pin.
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236 | * Has no effect if the according bit is the pull-up/pull-down enable register is disabled.
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237 | * The default value (after reset) is 0b1 (pull-up).
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238 | */
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239 | typedef enum { |
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240 | PCAL6524_LLD_PUPDSELECTION_PULLUP = 0b1,
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241 | PCAL6524_LLD_PUPDSELECTION_PULLDOWN = 0b0,
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242 | } pcal6524_lld_pupdselection_t; |
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243 | |||
244 | /**
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245 | * @brief Interrupt mask register bit values.
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246 | * @details Allows to enable (value 0) or disable (value 1) interrupts per pin.
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247 | * The default value (after reset) is 0b1 (interrupt disabled).
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248 | */
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249 | typedef enum { |
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250 | PCAL6524_LLD_INTERRUPTMASK_ENABLED = 0b0,
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251 | PCAL6524_LLD_INTERRUPTMASK_DSIABLED = 0b1,
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252 | } pcal6524_lld_interruptmask_t; |
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253 | |||
254 | /**
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255 | * @brief Interrupt status register bit value.
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256 | * @details Indicates whether an interrupt occurred per pin.
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257 | * After reset the register is initialized with 0b0 (no interrupt occurred yet).
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258 | */
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259 | typedef enum { |
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260 | PCAL6524_LLD_INTERRUPTSTATUS_ACTIVE = 0b1,
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261 | PCAL6524_LLD_INTERRUPTSTATUS_INACTIVE = 0b0,
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262 | } pcal6542_lld_interruptstatus_t; |
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263 | |||
264 | /**
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265 | * @brief Output port configuration register mask of valid bits.
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266 | */
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267 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK 0x07u |
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268 | |||
269 | /**
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270 | * @brief Output port configuration register mask for I/O port 0.
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271 | */
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272 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT0 0x01u |
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273 | |||
274 | /**
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275 | * @brief Output port configuration register mask for I/O port 1.
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276 | */
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277 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT1 0x02u |
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278 | |||
279 | /**
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280 | * @brief Output port configuration register mask for I/O port 2.
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281 | */
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282 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT2 0x04u |
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283 | |||
284 | /**
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285 | * @brief Output port configuration register bit values.
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286 | * @details Configures all ouput pins per port to be push-pull or open-drain.
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287 | * The default value (after reset) is 0b0 (push-pull).
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288 | */
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289 | typedef enum { |
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290 | PCAL6524_LLD_OUTPUTCONFIGURATION_PUSHPULL = 0b0,
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291 | PCAL6524_LLD_OUTPUTCONFIGURATION_OPENDRAIN = 0b1,
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292 | } pcal6524_lld_outputconfiguration_t; |
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293 | |||
294 | /**
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295 | * @brief Interrupt edge register mask values.
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296 | * @details Configures the type of event that would cause an interrupt per pin.
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297 | * The default value (after reset) is 0b00 (level triggered).
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298 | */
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299 | typedef enum { |
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300 | PCAL6524_LLD_INTERRUPTEDGE_LEVELTRIGGERED = 0b00,
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301 | PCAL6524_LLD_INTERRUPTEDGE_RISINGEDGE = 0b01,
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302 | PCAL6524_LLD_INTERRUPTEDGE_FALLINGEDGE = 0b10,
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303 | PCAL6524_LLD_INTERRUPTEDGE_ANYEDGE = 0b11,
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304 | } pcal6524_lld_interruptedge_t; |
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305 | |||
306 | /**
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307 | * @brief Input status register bit values.
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308 | * @details Reflects the current logic level per pin similar to the input register.
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309 | * However, values are not latched and reading the register will not reset interrupts.
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310 | */
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311 | typedef enum { |
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312 | PCAL6524_LLD_INPUTSTATUS_LOW = 0b0,
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313 | PCAL6524_LLD_INPUTSTATUS_HIGH = 0b1,
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314 | } pcal6524_lld_inputstatus_t; |
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315 | |||
316 | /**
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317 | * @brief Individual pin output configuration register bit values.
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318 | * @details Can be used to invert the port-wide push-pull/open-drain configuration via the ouput port configuration register per pin.
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319 | * the default value (after reset) is 0b0 (not inverted).
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320 | */
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321 | typedef enum { |
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322 | PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_PORT = 0b0,
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323 | PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_INVERTED = 0b1,
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324 | } pcal6524_lld_individualpinoutputconfiguration_t; |
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325 | |||
326 | /**
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327 | * @brief Switch debounce enable register bit values.
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328 | * @details Allows to enable debounce functionality for I/O ports 0 and 1.
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329 | * In order to use the debounce feature, an oscillator signal must be applied to pin 0 of port 0.
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330 | * The default value (after reset) is 0b0 (disabled).
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331 | */
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332 | typedef enum { |
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333 | PCAL6524_LLD_SWITCHDEBOUNCE_ENABLED = 0b1,
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334 | PCAL6524_LLD_SWITCHDEBOUNCE_DISABLED = 0b0,
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335 | } pcal6524_lld_switchdebounceenable_t; |
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336 | |||
337 | ef078306 | Thomas Schöpping | /******************************************************************************/
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338 | /* MACROS */
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339 | /******************************************************************************/
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340 | |||
341 | /******************************************************************************/
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342 | /* EXTERN DECLARATIONS */
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343 | /******************************************************************************/
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344 | |||
345 | e3287406 | Thomas Schöpping | #ifdef __cplusplus
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346 | extern "C" { |
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347 | #endif
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348 | uint8_t pcal6524_lld_cmd_groupsize(const pcal6524_lld_cmd_t cmd);
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349 | |||
350 | // apalExitStatus_t pcal6524_lld_read_id(const PCAL6524Driver* const pcal6524d, uint8_t* const data, const apalTime_t timeout);
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351 | apalExitStatus_t pcal6524_lld_read_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout); |
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352 | apalExitStatus_t pcal6524_lld_write_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t data, const apalTime_t timeout); |
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353 | apalExitStatus_t pcal6524_lld_read_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout); |
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354 | apalExitStatus_t pcal6524_lld_write_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const apalTime_t timeout); |
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355 | apalExitStatus_t pcal6524_lld_read_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const uint8_t length, const apalTime_t timeout); |
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356 | apalExitStatus_t pcal6524_lld_write_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const uint8_t length, const apalTime_t timeout); |
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357 | #ifdef __cplusplus
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358 | } |
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359 | #endif
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360 | |||
361 | ef078306 | Thomas Schöpping | /******************************************************************************/
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362 | /* INLINE FUNCTIONS */
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363 | /******************************************************************************/
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364 | |||
365 | 9466e34d | Thomas Schöpping | #endif /* AMIROLLD_PCAL6524_H */ |
366 | e3287406 | Thomas Schöpping | |
367 | /** @} */
|