amiro-os / modules / DiWheelDrive_1-1 / board.c @ 2a9f9ad7
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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019 Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief DiWheeDrive v1.1 Board specific initializations.
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*
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* @addtogroup diwheeldrive_board
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* @{
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*/
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#include <hal.h> |
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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const PALConfig pal_default_config = {
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#if STM32_HAS_GPIOA
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, |
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#endif
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#if STM32_HAS_GPIOB
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, |
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#endif
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#if STM32_HAS_GPIOC
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, |
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#endif
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#if STM32_HAS_GPIOD
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, |
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#endif
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#if STM32_HAS_GPIOE
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{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, |
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#endif
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#if STM32_HAS_GPIOF
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{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, |
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#endif
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#if STM32_HAS_GPIOG
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{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, |
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#endif
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}; |
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#endif
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/**
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* @brief Early initialization code.
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* @details This initialization must be performed just after stack setup
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* and before any other initialization.
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*/
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void __early_init(void) { |
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stm32_clock_init(); |
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} |
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/**
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* @brief Board-specific initialization code.
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* @todo Add your board-specific code, if any.
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*/
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void boardInit(void) { |
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/*
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* Several I/O pins are re-mapped:
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* JTAG disabled and SWJ enabled
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* TIM2 to the PA15/PB3/PA2/PA3 pins.
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* TIM3 to PC6/PC7 pins.
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* USART3 to the PC10/PC11 pins.
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* I2C1 to the PB8/PB9 pins.
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*/
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AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE | |
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AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | |
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AFIO_MAPR_TIM3_REMAP_FULLREMAP | |
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AFIO_MAPR_USART3_REMAP_PARTIALREMAP | |
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AFIO_MAPR_I2C1_REMAP; |
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} |
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/** @} */
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