amiro-os / modules / NUCLEO-L476RG / mcuconf.h @ 2a9f9ad7
History | View | Annotate | Download (14.5 KB)
1 |
/*
|
---|---|
2 |
AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
|
3 |
Copyright (C) 2016..2019 Thomas Schöpping et al.
|
4 |
|
5 |
This program is free software: you can redistribute it and/or modify
|
6 |
it under the terms of the GNU General Public License as published by
|
7 |
the Free Software Foundation, either version 3 of the License, or
|
8 |
(at your option) any later version.
|
9 |
|
10 |
This program is distributed in the hope that it will be useful,
|
11 |
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
GNU General Public License for more details.
|
14 |
|
15 |
You should have received a copy of the GNU General Public License
|
16 |
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
17 |
*/
|
18 |
|
19 |
/*
|
20 |
* STM32L4xx drivers configuration.
|
21 |
* The following settings override the default settings present in
|
22 |
* the various device driver implementation headers.
|
23 |
* Note that the settings for each driver only have effect if the whole
|
24 |
* driver is enabled in halconf.h.
|
25 |
*
|
26 |
* IRQ priorities:
|
27 |
* 15...0 Lowest...Highest.
|
28 |
*
|
29 |
* DMA priorities:
|
30 |
* 0...3 Lowest...Highest.
|
31 |
*/
|
32 |
|
33 |
#ifndef MCUCONF_H
|
34 |
#define MCUCONF_H
|
35 |
|
36 |
#define STM32L4xx_MCUCONF
|
37 |
#define STM32L476_MCUCONF
|
38 |
#define STM32L486_MCUCONF
|
39 |
|
40 |
/*
|
41 |
* HAL driver system settings.
|
42 |
*/
|
43 |
#define STM32_NO_INIT FALSE
|
44 |
#define STM32_VOS STM32_VOS_RANGE1
|
45 |
#define STM32_PVD_ENABLE FALSE
|
46 |
#define STM32_PLS STM32_PLS_LEV0
|
47 |
#define STM32_HSI16_ENABLED FALSE
|
48 |
#define STM32_LSI_ENABLED TRUE
|
49 |
#define STM32_HSE_ENABLED FALSE
|
50 |
#define STM32_LSE_ENABLED TRUE
|
51 |
#define STM32_MSIPLL_ENABLED TRUE
|
52 |
#define STM32_MSIRANGE STM32_MSIRANGE_4M
|
53 |
#define STM32_MSISRANGE STM32_MSISRANGE_4M
|
54 |
#define STM32_SW STM32_SW_PLL
|
55 |
#define STM32_PLLSRC STM32_PLLSRC_MSI
|
56 |
#define STM32_PLLM_VALUE 1 |
57 |
#define STM32_PLLN_VALUE 80 |
58 |
#define STM32_PLLP_VALUE 7 |
59 |
#define STM32_PLLQ_VALUE 6 |
60 |
#define STM32_PLLR_VALUE 4 |
61 |
#define STM32_HPRE STM32_HPRE_DIV1
|
62 |
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
63 |
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
64 |
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
|
65 |
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
66 |
#define STM32_MCOPRE STM32_MCOPRE_DIV1
|
67 |
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
|
68 |
#define STM32_PLLSAI1N_VALUE 72 |
69 |
#define STM32_PLLSAI1P_VALUE 7 |
70 |
#define STM32_PLLSAI1Q_VALUE 6 |
71 |
#define STM32_PLLSAI1R_VALUE 6 |
72 |
#define STM32_PLLSAI2N_VALUE 72 |
73 |
#define STM32_PLLSAI2P_VALUE 7 |
74 |
#define STM32_PLLSAI2R_VALUE 6 |
75 |
|
76 |
/*
|
77 |
* Peripherals clock sources.
|
78 |
*/
|
79 |
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
|
80 |
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
|
81 |
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
|
82 |
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
|
83 |
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
|
84 |
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
|
85 |
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
|
86 |
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
|
87 |
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
|
88 |
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
|
89 |
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
|
90 |
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
|
91 |
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
|
92 |
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
|
93 |
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
|
94 |
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
|
95 |
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
|
96 |
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
97 |
|
98 |
/*
|
99 |
* IRQ system settings.
|
100 |
*/
|
101 |
#define STM32_IRQ_EXTI0_PRIORITY 6 |
102 |
#define STM32_IRQ_EXTI1_PRIORITY 6 |
103 |
#define STM32_IRQ_EXTI2_PRIORITY 6 |
104 |
#define STM32_IRQ_EXTI3_PRIORITY 6 |
105 |
#define STM32_IRQ_EXTI4_PRIORITY 6 |
106 |
#define STM32_IRQ_EXTI5_9_PRIORITY 6 |
107 |
#define STM32_IRQ_EXTI10_15_PRIORITY 6 |
108 |
#define STM32_IRQ_EXTI1635_38_PRIORITY 6 |
109 |
#define STM32_IRQ_EXTI18_PRIORITY 6 |
110 |
#define STM32_IRQ_EXTI19_PRIORITY 6 |
111 |
#define STM32_IRQ_EXTI20_PRIORITY 6 |
112 |
#define STM32_IRQ_EXTI21_22_PRIORITY 15 |
113 |
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 |
114 |
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 |
115 |
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 |
116 |
#define STM32_IRQ_TIM1_CC_PRIORITY 7 |
117 |
|
118 |
/*
|
119 |
* ADC driver system settings.
|
120 |
*/
|
121 |
#define STM32_ADC_DUAL_MODE FALSE
|
122 |
#define STM32_ADC_COMPACT_SAMPLES FALSE
|
123 |
#define STM32_ADC_USE_ADC1 FALSE
|
124 |
#define STM32_ADC_USE_ADC2 FALSE
|
125 |
#define STM32_ADC_USE_ADC3 TRUE
|
126 |
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
127 |
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
128 |
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
129 |
#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
130 |
#define STM32_ADC_ADC2_DMA_PRIORITY 2 |
131 |
#define STM32_ADC_ADC3_DMA_PRIORITY 2 |
132 |
#define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
133 |
#define STM32_ADC_ADC3_IRQ_PRIORITY 5 |
134 |
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
135 |
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
136 |
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
137 |
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
138 |
|
139 |
/*
|
140 |
* CAN driver system settings.
|
141 |
*/
|
142 |
#define STM32_CAN_USE_CAN1 TRUE
|
143 |
#define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
144 |
|
145 |
/*
|
146 |
* DAC driver system settings.
|
147 |
*/
|
148 |
#define STM32_DAC_DUAL_MODE FALSE
|
149 |
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
150 |
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
151 |
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
152 |
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
153 |
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
154 |
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
155 |
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
156 |
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
157 |
|
158 |
/*
|
159 |
* GPT driver system settings.
|
160 |
*/
|
161 |
#define STM32_GPT_USE_TIM1 FALSE
|
162 |
#define STM32_GPT_USE_TIM2 FALSE
|
163 |
#define STM32_GPT_USE_TIM3 FALSE
|
164 |
#define STM32_GPT_USE_TIM4 FALSE
|
165 |
#define STM32_GPT_USE_TIM5 FALSE
|
166 |
#define STM32_GPT_USE_TIM6 FALSE
|
167 |
#define STM32_GPT_USE_TIM7 FALSE
|
168 |
#define STM32_GPT_USE_TIM8 FALSE
|
169 |
#define STM32_GPT_USE_TIM15 FALSE
|
170 |
#define STM32_GPT_USE_TIM16 FALSE
|
171 |
#define STM32_GPT_USE_TIM17 FALSE
|
172 |
#define STM32_GPT_TIM1_IRQ_PRIORITY 7 |
173 |
#define STM32_GPT_TIM2_IRQ_PRIORITY 7 |
174 |
#define STM32_GPT_TIM3_IRQ_PRIORITY 7 |
175 |
#define STM32_GPT_TIM4_IRQ_PRIORITY 7 |
176 |
#define STM32_GPT_TIM5_IRQ_PRIORITY 7 |
177 |
#define STM32_GPT_TIM6_IRQ_PRIORITY 7 |
178 |
#define STM32_GPT_TIM7_IRQ_PRIORITY 7 |
179 |
#define STM32_GPT_TIM8_IRQ_PRIORITY 7 |
180 |
|
181 |
/*
|
182 |
* I2C driver system settings.
|
183 |
*/
|
184 |
#define STM32_I2C_USE_I2C1 FALSE
|
185 |
#define STM32_I2C_USE_I2C2 FALSE
|
186 |
#define STM32_I2C_USE_I2C3 TRUE
|
187 |
#define STM32_I2C_BUSY_TIMEOUT 50 |
188 |
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
189 |
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
190 |
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
191 |
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
192 |
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
193 |
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
194 |
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
195 |
#define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
196 |
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
197 |
#define STM32_I2C_I2C1_DMA_PRIORITY 3 |
198 |
#define STM32_I2C_I2C2_DMA_PRIORITY 3 |
199 |
#define STM32_I2C_I2C3_DMA_PRIORITY 3 |
200 |
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
201 |
|
202 |
/*
|
203 |
* ICU driver system settings.
|
204 |
*/
|
205 |
#define STM32_ICU_USE_TIM1 FALSE
|
206 |
#define STM32_ICU_USE_TIM2 FALSE
|
207 |
#define STM32_ICU_USE_TIM3 FALSE
|
208 |
#define STM32_ICU_USE_TIM4 FALSE
|
209 |
#define STM32_ICU_USE_TIM5 FALSE
|
210 |
#define STM32_ICU_USE_TIM8 FALSE
|
211 |
#define STM32_ICU_USE_TIM15 FALSE
|
212 |
#define STM32_ICU_TIM1_IRQ_PRIORITY 7 |
213 |
#define STM32_ICU_TIM2_IRQ_PRIORITY 7 |
214 |
#define STM32_ICU_TIM3_IRQ_PRIORITY 7 |
215 |
#define STM32_ICU_TIM4_IRQ_PRIORITY 7 |
216 |
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 |
217 |
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 |
218 |
|
219 |
/*
|
220 |
* PWM driver system settings.
|
221 |
*/
|
222 |
#define STM32_PWM_USE_ADVANCED FALSE
|
223 |
#define STM32_PWM_USE_TIM1 FALSE
|
224 |
#define STM32_PWM_USE_TIM2 FALSE
|
225 |
#define STM32_PWM_USE_TIM3 FALSE
|
226 |
#define STM32_PWM_USE_TIM4 FALSE
|
227 |
#define STM32_PWM_USE_TIM5 FALSE
|
228 |
#define STM32_PWM_USE_TIM8 FALSE
|
229 |
#define STM32_PWM_USE_TIM15 FALSE
|
230 |
#define STM32_PWM_USE_TIM16 FALSE
|
231 |
#define STM32_PWM_USE_TIM17 FALSE
|
232 |
#define STM32_PWM_TIM1_IRQ_PRIORITY 7 |
233 |
#define STM32_PWM_TIM2_IRQ_PRIORITY 7 |
234 |
#define STM32_PWM_TIM3_IRQ_PRIORITY 7 |
235 |
#define STM32_PWM_TIM4_IRQ_PRIORITY 7 |
236 |
#define STM32_PWM_TIM5_IRQ_PRIORITY 7 |
237 |
#define STM32_PWM_TIM8_IRQ_PRIORITY 7 |
238 |
|
239 |
/*
|
240 |
* RTC driver system settings.
|
241 |
*/
|
242 |
#define STM32_RTC_PRESA_VALUE 32 |
243 |
#define STM32_RTC_PRESS_VALUE 1024 |
244 |
#define STM32_RTC_CR_INIT 0 |
245 |
#define STM32_RTC_TAMPCR_INIT 0 |
246 |
|
247 |
/*
|
248 |
* SDC driver system settings.
|
249 |
*/
|
250 |
#define STM32_SDC_USE_SDMMC1 FALSE
|
251 |
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
|
252 |
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 |
253 |
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 |
254 |
#define STM32_SDC_SDMMC_CLOCK_DELAY 10 |
255 |
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 |
256 |
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 |
257 |
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
258 |
|
259 |
/*
|
260 |
* SERIAL driver system settings.
|
261 |
*/
|
262 |
#define STM32_SERIAL_USE_USART1 FALSE
|
263 |
#define STM32_SERIAL_USE_USART2 TRUE
|
264 |
#define STM32_SERIAL_USE_USART3 FALSE
|
265 |
#define STM32_SERIAL_USE_UART4 FALSE
|
266 |
#define STM32_SERIAL_USE_UART5 FALSE
|
267 |
#define STM32_SERIAL_USE_LPUART1 FALSE
|
268 |
#define STM32_SERIAL_USART1_PRIORITY 12 |
269 |
#define STM32_SERIAL_USART2_PRIORITY 12 |
270 |
#define STM32_SERIAL_USART3_PRIORITY 12 |
271 |
#define STM32_SERIAL_UART4_PRIORITY 12 |
272 |
#define STM32_SERIAL_UART5_PRIORITY 12 |
273 |
#define STM32_SERIAL_LPUART1_PRIORITY 12 |
274 |
|
275 |
/*
|
276 |
* SPI driver system settings.
|
277 |
*/
|
278 |
#define STM32_SPI_USE_SPI1 FALSE
|
279 |
#define STM32_SPI_USE_SPI2 FALSE
|
280 |
#define STM32_SPI_USE_SPI3 FALSE
|
281 |
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
282 |
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
283 |
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
284 |
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
285 |
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
286 |
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
287 |
#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
288 |
#define STM32_SPI_SPI2_DMA_PRIORITY 1 |
289 |
#define STM32_SPI_SPI3_DMA_PRIORITY 1 |
290 |
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
291 |
#define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
292 |
#define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
293 |
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
294 |
|
295 |
/*
|
296 |
* ST driver system settings.
|
297 |
*/
|
298 |
#define STM32_ST_IRQ_PRIORITY 8 |
299 |
#define STM32_ST_USE_TIMER 2 |
300 |
|
301 |
/*
|
302 |
* TRNG driver system settings.
|
303 |
*/
|
304 |
#define STM32_TRNG_USE_RNG1 FALSE
|
305 |
|
306 |
/*
|
307 |
* UART driver system settings.
|
308 |
*/
|
309 |
#define STM32_UART_USE_USART1 FALSE
|
310 |
#define STM32_UART_USE_USART2 TRUE
|
311 |
#define STM32_UART_USE_USART3 FALSE
|
312 |
#define STM32_UART_USE_UART4 FALSE
|
313 |
#define STM32_UART_USE_UART5 FALSE
|
314 |
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
315 |
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) |
316 |
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
317 |
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
318 |
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
319 |
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
320 |
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) |
321 |
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
322 |
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
323 |
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
324 |
#define STM32_UART_USART1_IRQ_PRIORITY 12 |
325 |
#define STM32_UART_USART2_IRQ_PRIORITY 12 |
326 |
#define STM32_UART_USART3_IRQ_PRIORITY 12 |
327 |
#define STM32_UART_UART4_IRQ_PRIORITY 12 |
328 |
#define STM32_UART_UART5_IRQ_PRIORITY 12 |
329 |
#define STM32_UART_USART1_DMA_PRIORITY 0 |
330 |
#define STM32_UART_USART2_DMA_PRIORITY 0 |
331 |
#define STM32_UART_USART3_DMA_PRIORITY 0 |
332 |
#define STM32_UART_UART4_DMA_PRIORITY 0 |
333 |
#define STM32_UART_UART5_DMA_PRIORITY 0 |
334 |
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
335 |
|
336 |
/*
|
337 |
* USB driver system settings.
|
338 |
*/
|
339 |
#define STM32_USB_USE_OTG1 FALSE
|
340 |
#define STM32_USB_OTG1_IRQ_PRIORITY 14 |
341 |
#define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
342 |
|
343 |
/*
|
344 |
* WDG driver system settings.
|
345 |
*/
|
346 |
#define STM32_WDG_USE_IWDG FALSE
|
347 |
|
348 |
/*
|
349 |
* WSPI driver system settings.
|
350 |
*/
|
351 |
#define STM32_WSPI_USE_QUADSPI1 FALSE
|
352 |
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
353 |
|
354 |
#endif /* MCUCONF_H */ |